CN113098294A - Zero voltage switch realizing device of series capacitor DC-DC converter - Google Patents

Zero voltage switch realizing device of series capacitor DC-DC converter Download PDF

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CN113098294A
CN113098294A CN202110569158.0A CN202110569158A CN113098294A CN 113098294 A CN113098294 A CN 113098294A CN 202110569158 A CN202110569158 A CN 202110569158A CN 113098294 A CN113098294 A CN 113098294A
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zvs
power switch
current
switch
voltage
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CN113098294B (en
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程林
黄迪
苑竞艺
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University of Science and Technology of China USTC
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The present disclosure provides a zero voltage switch implementation apparatus of a series capacitor dc-dc converter, including: the power voltage reduction circuit is used for converting the high-voltage direct current into alternating current; the ZVS circuit is used for charging and discharging the parasitic capacitance of the switching node of the power voltage reduction circuit; the output filter circuit is used for stabilizing the alternating current provided by the power voltage reduction circuit into direct current and providing energy for an output load; and the zero voltage detection and dead time control circuit is used for detecting whether the ZVS circuit is finished and generating corresponding dead time, and comprises a zero voltage detection module and a dead time control circuit.

Description

Zero voltage switch realizing device of series capacitor DC-DC converter
Technical Field
The present disclosure relates to the field of circuit technologies, and in particular, to a zero voltage switching implementation apparatus for a series capacitor dc-dc converter.
Background
The existing high-Voltage dc-dc converter uses a high-Voltage power switch, which causes a large parasitic capacitance at a switch node, so that a ZVS (Zero-Voltage Switching) technology needs to be adopted to improve the conversion efficiency.
The conventional resonant dc-dc converter can realize ZVS of the power switch, but the power switch with a higher withstand voltage value is often required. In general, in a power switch having a higher withstand voltage, the conduction resistance and the parasitic capacitance are larger, which causes larger conduction loss and switching loss, and deteriorates energy conversion efficiency. The series capacitor DC-DC converter has the advantages of reducing the withstand voltage value of a power switch, improving the duty ratio and the like, and is widely applied to the high-voltage DC-DC converter. Because the input power supply voltage is high, the power switch generally needs to adopt a high-voltage MOS (Metal-Oxide-Semiconductor) transistor, so that a switch node has a large parasitic capacitance, and when the switch is switched, charges on the parasitic capacitance are discharged and wasted, thereby seriously reducing the conversion efficiency. In order to improve the efficiency of the converter, the ZVS technology is required to be adopted in the existing series capacitor dc-dc converter.
FIG. 1 is a schematic diagram of a series-capacitor DC-DC Converter using the resonant effect of an external inductor and capacitor to realize ZVS [ refer to Tu C, Chen R, Ngo K.series-reactors Buck Converter-sensitivity demodulation [ J ]]IEEE Transactions on Power Electronics, 2021, PP (99): 1-1. Inductor LZVSAnd a capacitor CZVSForm a resonant circuit 101, SAH、SAL、SBH、SBLIs a power switch of the converter, and has parasitic capacitances C at switch nodes SWA, SWB and SWCAL、CBLAnd CCL. When the power switch is switched, the larger voltage change of the switch node can cause the power switch to have larger current to flow, and the switching loss and the current pressure of the power switch are seriously increased. While in-flight capacitor CFlyAn inductor L is connected between the switching node SWA and the switchZVSAnd a capacitor CZVSZVS circuit 101 is configured to recover switching losses and reduce current stress of the power switches. The working principle is as follows: before the power switch is opened, the parasitic capacitance of the switch node passes through LZVSAnd CZVSThe formed ZVS circuit completes charging and discharging. Fig. 2 shows the key waveforms for implementing ZVS in the series capacitor dc-dc converter shown in fig. 1. With power switch SAHImplementation of ZVS as an example, LZVSAnd CZVSAt resonance, the resonant circuit 101 passes through the flying capacitor CFlyParasitic capacitance C to SWC pointCLCharging is carried out due to CFlyThe voltage difference between the two ends is kept at Vin/2, therefore when t8Time of day, CZVSVoltage VC at two endsZVSTo reach VinIn case/2, the ZVS circuit completes the pair CCLIs charged toVin，SAHSwitching on at zero voltage, the turn-on loss is significantly reduced. Working principle and S for realizing ZVS by other power switchesAHThe same is true. As shown in FIG. 2, LZVSAnd CZVSAt resonance, VCZVSThe variation range is-Vin/2～+Vin(V) all power switches need to have a voltage withstanding value of VinHigh voltage device of SAH、SAL、SBLThe power switch voltage pressure is doubled. Series capacitor DC-DC converter without ZVS, only SBHIt is necessary to use a withstand voltage value of VinThe voltage withstanding value of the other three power switches is only Vin/2. In general, in a power switch having a higher breakdown voltage, the conduction resistance and the parasitic capacitance are larger, which causes larger conduction loss and switching loss, and deteriorates energy conversion efficiency. Therefore, the resonant ZVS technique increases the voltage stress of the power switch, thereby reducing the efficiency advantage of the ZVS technique.
Disclosure of Invention
Technical problem to be solved
Based on the above problems, the present disclosure provides a zero voltage switch implementation apparatus for a series capacitor dc-dc converter, so as to alleviate technical problems that in the prior art, a resonant ZVS technology increases a voltage pressure of a power switch, thereby weakening an efficiency advantage brought by the ZVS technology.
(II) technical scheme
The present disclosure provides a zero voltage switch implementation apparatus of a series capacitor dc-dc converter, including: power step-down circuit for converting high voltage dc power to ac power, comprising: power switch SAHAnd an input voltage VinConnecting; flying capacitor CFlyOne end of the power switch S is connected with the power switch through a switch node SWCAHConnecting; power on SALThrough switch node SWA and flying capacitor CFlyThe other ends of the two are connected; power switch SBHThrough switch node SWC and said power switch SAHConnecting; and a power switch SBLThrough a switch node SWB and said power switch SBHConnecting; ZVS circuit for reducing powerThe stray capacitance of the switch node of the circuit is charged and discharged, two ends of the ZVS circuit are respectively connected with the switch node SWA and the switch node SWB, and the ZVS circuit comprises an inductor L which is arranged in seriesZVSAnd a capacitor CZVS(ii) a The output filter circuit is used for stabilizing the alternating current provided by the power voltage reduction circuit into direct current and providing energy for an output load, and comprises: inductors L respectively connected to the two ends of the ZVS and arranged in parallelAAnd an inductance LB(ii) a And a capacitor C and an inductor LAAnd an inductance LBConnecting; and the zero voltage detection and dead time control circuit is used for detecting whether the ZVS circuit is finished and generating corresponding dead time, and comprises a zero voltage detection module and a dead time control circuit.
According to the embodiment of the disclosure, in the state 1, the inductance LZVSAnd LAThe difference in current is the parasitic capacitance C of the switch nodes SWA and SWCALAnd CCLCharging, to power switch SAHParasitic capacitance C ofAHDischarge is performed due to flying capacitor CFlyThe voltage across the terminals is kept at half the input voltage, and the potential of the switching node SWC gradually rises with the potential of the switching node SWA.
According to the embodiment of the disclosure, in the state 2, the SWA point potential of the switch node rises to a half of the input voltage, the SWC point potential rises to the input voltage, and the zero voltage detection module detects that the power switch SAHAfter the voltage difference between the two ends of the source and the drain is 0, the dead time control circuit controls SAHWhen the switch is turned on, the potential of the switch node SWA is higher than that of the SWB point, and the inductor LZVSCorresponding current iLZVSFlows from SWB to SWA and gradually decreases to 0 and reverses.
In state 3, power switch S, according to an embodiment of the disclosureAHTurn-off, inductance LZVSCorresponding current iLZVSAnd an inductance LAThe current direction is the same, and the parasitic capacitance CALAnd CCLDischarge, parasitic capacitance CAHAnd (6) charging.
In state 4, power switch S, according to an embodiment of the present disclosureALIs turned on by SALThe current flowing from the source to the drain is equal to the current flowing through the inductor LA、LBAnd a power switch SBLThe sum of the currents of, the inductance LZVSIs greater than the inductance LBThe current of (2).
In state 5, power switch S, according to an embodiment of the present disclosureBLTurn-off, inductance LZVSAnd LBThe difference in current is the parasitic capacitance C of the switch node SWBBLCharging, to power switch SBHParasitic capacitance C ofBHThe discharge is performed, and the potential at the switching node SWB gradually rises.
In state 6, the zero voltage detection and dead time control circuit detects that the switch node SWB has risen to the power switch SBHDrain potential of (V)in/2 dead time control circuit controls power switch SBHOpening; the potential of the switch node SWB is higher than that of the switch node SWA, and ZVS inductive current iL flowing from the SWA to the SWBZVSGradually decreases to 0 and reverses.
In state 7, power switch S, according to an embodiment of the disclosureBHTurn-off, inductance LZVSCorresponding current iLZVSAnd an inductance LBThe current direction is the same, and the parasitic capacitance CBLDischarge, parasitic capacitance CBHAnd (6) charging.
In state 8, power switch S, according to an embodiment of the disclosureBLIs turned on by the power switch SBLThe current flowing from the source to the drain is equal to the current flowing through the inductor LA、LBAnd a power switch SALThe sum of the currents of, the inductance LZVSCorresponding current iLZVSGreater than inductance LAThe current of (2).
Power switch S according to an embodiment of the disclosureAHAnd SALFlying capacitor CFlyAnd an inductance LAForm a subconverter PhaseA, a power switch SBHAnd SBLAnd an inductor LBForm a subconverter PhaseB when the inductor current I isLA、ILBDirection of and ZVS inductance LZVSCurrent iLZVSWhen the directions are opposite, iLZVSMust be specific to the inductive current ILA、ILBPeak value of large, ZVS inductive current and inductive current ILA、ILBThe difference between the minimum values is Idiff，minA、Idiff，minBAnd can be represented by the formulae (1) and (2).
Figure BDA0003080564880000041
Figure BDA0003080564880000042
LZVSThe energy of the power switch is larger than that of the parasitic capacitor, so that ZVS of the power switch can be realized; the ZVS inductance value L is taken under the condition that PhaseA and PhaseB power switches are opened at zero voltage respectivelyZVS，A、LZVS，BAnd can be represented by the formulas (3) and (4), and the final ZVS inductance LZVSSelecting LZVS，AAnd LZVS，BThe medium and small values meet the condition that the two-phase power switch can realize ZVS;
Figure BDA0003080564880000043
Figure BDA0003080564880000044
wherein D isADuty ratio of PhaseA, DBIs the duty cycle of PhaseB, fswIs the operating frequency of the converter.
(III) advantageous effects
According to the technical scheme, the zero-voltage switch implementation device of the series capacitor dc-dc converter disclosed by the disclosure has at least one or part of the following beneficial effects:
(1) the withstand voltage value of the power switch cannot be increased;
(2) the conversion efficiency of the converter can be effectively improved.
Drawings
Fig. 1 is a schematic structural diagram of a series capacitor dc-dc converter in the prior art, which utilizes the resonance effect of an external inductor capacitor to realize ZVS.
Fig. 2 is a schematic diagram of a key waveform of the series capacitor dc-dc converter shown in fig. 1 for implementing ZVS.
Fig. 3 is a schematic diagram of a frame and a principle of a ZVS implementation method for a series capacitor dc-dc converter according to an embodiment of the disclosure.
Fig. 4 is a schematic circuit topology diagram of a method for implementing ZVS of a series capacitor dc-dc converter according to an embodiment of the present disclosure.
Fig. 5 is a schematic diagram of operating states 1-8 of the serial capacitance dc-dc converter ZVS implementation method shown in fig. 4.
Fig. 6 is a waveform diagram illustrating an operation of the series capacitor dc-dc converter ZVS implementation method shown in fig. 4.
Fig. 7 is a schematic diagram illustrating the operation principle of the zero voltage detection and dead time control circuit according to the embodiment of the disclosure.
Fig. 8 is a schematic diagram of operation timing sequences of the zero voltage detection circuit 2041, the non-overlap clock 2042, and the maximum dead time circuit 2043 according to the embodiment of the present disclosure.
Fig. 9 is a schematic diagram of withstand voltage values of each power switch and capacitor according to the embodiment of the disclosure.
Detailed Description
The utility model provides a zero voltage switch of series capacitance DC-DC converter realizes the zero voltage switch of series capacitance DC-DC converter through adopting plus inductance capacitance, when can realizing high efficiency, does not increase the voltage pressure of power switch.
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
In an embodiment of the present disclosure, there is provided a zero voltage switching implementation apparatus of a series capacitor dc-dc converter, as shown in fig. 3 to 9, the zero voltage switching implementation apparatus of the series capacitor dc-dc converter including:
power step-down circuit for converting high voltage dc power to ac power, comprising:
power switch SAHAnd an input voltage VinConnecting;
flying capacitor CFlyOne end of the power switch S is connected with the power switch through a switch node SWCAHConnecting;
power on SALThrough switch node SWA and flying capacitor CFlyThe other ends of the two are connected;
power switch SBHThrough switch node SWC and said power switch SAHConnecting; and
power switch SBLThrough a switch node SWB and said power switch SBHConnecting;
the ZVS circuit is used for charging and discharging parasitic capacitance of a switch node of the power voltage reduction circuit, two ends of the ZVS circuit are respectively connected with the switch node SWA and the switch node SWB, and the ZVS circuit comprises an inductor L which is arranged in seriesZVSAnd a capacitor CZVS；
The output filter circuit is used for stabilizing the alternating current provided by the power voltage reduction circuit into direct current and providing energy for an output load, and comprises:
inductors L respectively connected to the two ends of the ZVS and arranged in parallelAAnd an inductance LB(ii) a And a capacitor C and an inductor LAAnd an inductance LBConnecting; and
the zero voltage detection and dead time control circuit is used for detecting whether the ZVS circuit is finished and generating corresponding dead time and comprises a zero voltage detection module and a dead time control circuit.
According to an embodiment of the present disclosure, a ZVS implementation method for a series capacitor dc-dc converter is shown in fig. 3, and includes: (Power step-down circuit 201, ZVS circuit 202, output filter circuit 203, zero voltage detection and dead time control circuit 204.)
Power switch S according to an embodiment of the disclosureAHAnd SALFlying capacitor CFlyAnd an inductance LAThe constructed subconverter PhaseA; power switch SBHAnd SBLAnd an inductor LBAnd constituting a subconverter PhaseB.
According to the embodiment of the disclosure, the operating principle of the series capacitor dc-dc converter ZVS circuit provided by the disclosure is as follows: (the power step-down circuit 201, ZVS circuit 202, and output filter circuit 203 can be operated in 8 states, Mode1-8, depending on the timing of the converter operation.
At Mode1, the inductor LZVSAnd LAThe difference in current is the parasitic capacitance C of the switch nodes SWA and SWCALAnd CCLCharging, to CAHDischarge is performed due to flying capacitor CFlyThe voltage at both ends is kept at VinAnd/2, the potential of the switching node SWC gradually rises with the potential of the switching node SWA.
At Mode2, the SWA point potential rises to Vin(ii)/2, increase of SWC Point potential to VinDetection of power switch S by ZVS detection moduleAHAfter the voltage difference between the two ends of the source and the drain is 0, the dead time control circuit controls SAHAnd (4) opening. The potential of the switch node SWA is higher than that of the SWB point, and the ZVS inductive current iLZVSFlows from SWB to SWA and gradually decreases to 0 and reverses.
At Mode3, power switch SAHOff, iLZVSAnd an inductance LAThe current direction is the same, and the parasitic capacitance CALAnd CCLDischarge, CAHAnd (6) charging.
At Mode4, power switch SALIs turned on by SALIs equal to the current flowing through LA、LBAnd SBLThe sum of the currents of, the inductance LZVSCurrent of greater than LBThe current of (2).
At Mode5, power switch SBLTurn-off, inductance LZVSAnd LBThe difference in current is the parasitic capacitance C of the switch node SWBBLCharging, to CBHThe discharge is performed, and the potential at the SWB point gradually rises.
At Mode6, the ZVS detection module detects the potential of the switch node SWB rising to the power switch SBHDrain potential of (V)in/2 dead time control circuit control SBHAnd (4) opening. Potential ratio of switch node SWBThe ZVS inductive current i flowing from SWA to SWB is high in SWA point potentialLZVSGradually decreases to 0 and reverses.
At Mode7, power switch SBHTurn-off, ZVS inductor current and inductor LBThe current direction is the same, and the parasitic capacitance CBLDischarge, CBHAnd (6) charging.
At Mode8, power switch SBLIs turned on by SBLIs equal to the current flowing through LA、LBAnd SALThe sum of the currents of, the inductance LZVSCurrent of greater than LAThe current of (2).
According to the embodiments of the present disclosure, the composition and the function of each circuit are explained:
the power step-down circuit 201 includes four power switches SAH、SAL、SBH、SBLAnd flying capacitor CFlyThe high-voltage direct current is converted into alternating current; the ZVS circuit 202 comprises an inductor and a capacitor, and is used for charging and discharging a switch node parasitic capacitor of the power stage circuit; the output filter circuit 203 comprises an inductor and a capacitor, and is used for stabilizing the alternating current provided by the power step-down circuit into direct current to provide energy for an output load; and a zero voltage detection and dead time control circuit 204 for detecting whether ZVS is completed and generating a corresponding dead time.
Referring to fig. 4, fig. 4 is a schematic circuit topology diagram of a method for implementing a series capacitor dc-dc converter ZVS according to an embodiment of the present disclosure. As shown in FIG. 4, CBHAnd CAHAre respectively a power switch SBHAnd SAHParasitic capacitance between source and drain, CAL、CBLAnd CCLParasitic capacitances to ground at switch nodes SWA, SWB and SWC, respectively.
The present disclosure provides a quasi square wave (ZVS) implementation method suitable for a series capacitor dc-dc converter.
Referring to fig. 5 and fig. 6, fig. 5 is a working state diagram of the series capacitor dc-dc converter ZVS implementation method provided by the present disclosure shown in fig. 4, and fig. 6 is a working waveform diagram of the ZVS implementation method provided by the present disclosure shown in fig. 4. The working state can be divided into 8 parts according to the working state diagram and the waveform diagram.
Model[t0-t1]: PhaseA' S high side power switch SAHAnd a low side power switch SALOff, parasitic capacitance CAL、CCLAnd CAHAnd ZVS inductance LZVSResonance, CAHDischarging it to V by resonant currentCAH0, flowing through CALAnd CCLRespectively charging them to VCAL＝Vin/2、VCcL＝Vin. At this time, the main inductive current ILADirection and LZVSCurrent iLZVSIn the opposite direction, CAL、CCLAnd CAHIs equal to ILAAnd iLZVSDifference of current, and the resonance current follows iLZVSIncreasing and decreasing.
When C is presentALFrom 0 to Vin/2，CCLFrom V to VinIncrease to Vin，CAHIs at a voltage of VinAfter/2 is reduced to 0, the resonant current starts to flow through SAHThe body diode of (1). Body diode conduction generally results in large power losses. Therefore, ZVS detect and dead time control circuit 204 is required to be SAHAnd SALThe turn-on of (c) produces a suitable dead time to reduce this loss.
Mode2[t1-t2]: SWA point potential of the switch node rises to Vin(ii)/2, increase of SWC Point potential to Vin，LZVSThe voltage across the inductor is Vin/2，iLZVSAt SAHOn period DAIncrease in T (D)AThe duty cycle of PhaseA). ZVS inductor current must be greater than ILAThere is enough energy to charge and discharge the parasitic capacitance, otherwise, SAHZVS turn-on cannot be achieved. At this time, S flowsAHHas a current of ILAAnd iLZVSAnd (4) summing.
Mode3[t2-t3]: power switch SAHOff, ILADirection of (1) and iLZVSDirection of (1)Same, parasitic capacitance CAL、CCLAnd CAHIs equal to ILAAnd iLZVSIn addition, the direction of the resonant current is opposite to that under Mode 1. Suitable dead time also needs to be set in order to reduce the body diode losses.
Mode4[t3-t4]: power switch SALAnd SBLOpening, PhaseA and PhaseB into the freewheeling phase, LZVSThe voltage difference between the two ends is 0, and the current thereof is kept constant. Flows through SALCurrent i ofSALAbsolute value equal to main inductor current ILAAnd ZVS inductor current iLZVSAnd (4) summing.
Mode5[t4-t5]: PhaseB' S high side power switch SBHAnd a low side power switch SBLOff, parasitic capacitance CBLAnd CBHAnd LZVSResonance, CBHDischarging it to V by resonant currentCBH0, flowing through CBLIs charged to VCAL＝Vin/2. At this time, the main inductive current ILBDirection and LZVSThe current direction is opposite, so that C flowsBLAnd CBHIs equal to ILBAnd iLZVSThe difference in current. When C is presentBLFrom 0 to Vin/2、CBHIs at a voltage of VinAfter/2 is reduced to 0, the resonant current starts to flow through SBHThe body diode of (1). To reduce SBHBody diode losses, a suitable dead time needs to be set.
Mode6[t5-t6]：CBHIs reduced to 0, CBLIs raised to VinAfter/2, S of PhaseBBHOpen in ZVS. L isZVSVoltage at both ends is Vin/2，iLZVSAt the power switch SBHOn period DBLinear increase within T (D)BThe duty cycle of PhaseB). i.e. iLZVSMust be greater than ILBThere is enough energy to charge and discharge the parasitic capacitance, otherwise, SBHZVS turn-on cannot be achieved. At this time, S flowsBHCurrent is ILBAnd iLZVSAnd (4) summing.
Mode7[t6-t7]：SBHOff, ILBDirection of (1) and iLZVSIn the same direction of (C)BLAnd CBHIs equal to ILBAnd iLZVSIn addition, the direction of the resonant current is opposite to that under Mode 5. At Mode7, ZVS detection and dead-time control circuit 204 needs to generate a suitable dead-time to reduce body diode losses.
Mode8[t7-t8]：SBLAnd SALOpening, PhaseA and PhaseB into the freewheeling phase, LZVSThe voltage difference between the two ends is 0, and the current thereof is kept constant. Flows through SBLCurrent i ofSBLAbsolute value equal to ILBAnd iLZVSAnd (4) summing.
When the main inductive current ILA、ILBDirection of and ZVS inductance LZVSCurrent iLZVSWhen the directions are opposite, iLZVSMust be larger than the main inductive current, the difference between the peak value of the ZVS inductive current and the minimum value of the main inductive current is Idiff，minA、Idiff，minBAnd can be represented by the formulae (1) and (2).
Figure BDA0003080564880000091
Figure BDA0003080564880000092
LZVSMust be larger than the parasitic capacitance to achieve ZVS of the power switch. The ZVS inductance value L is taken under the condition that PhaseA and PhaseB power switches are opened at zero voltage respectivelyZVS，A、LZVS，BAnd may be represented by formulas (3) and (4). Final ZVS inductance LZVSSelecting LZVS，AAnd LZVS，BThe smaller value of the two-phase power switch meets the condition that the two-phase power switch can realize ZVS.
Figure BDA0003080564880000093
Figure BDA0003080564880000094
Wherein f isswIs the operating frequency of the dc-dc converter.
According to an embodiment of the present disclosure, the zero voltage detection and dead time control circuit 204 is configured to detect whether ZVS is completed and generate a corresponding dead time. Referring to FIG. 7, FIG. 7 shows a ZVS detect and dead band control circuit of the present disclosure, where CLK is the control signal, VH、VLRespectively, the gate terminal control signals of the high-side power switch and the low-side power switch. The operation timings of the zero voltage detection circuit 2041, the non-overlap clock 2042, and the maximum dead time circuit 2043 are as shown in fig. 8. A zero voltage detection circuit 2041 for judging whether ZVS is completed or not when V isSWWhen the potential is greater than or equal to the drain voltage of the power switch, a feedback signal V is outputFBAnd changes to high level to enable the high-side power switch driving signal. A non-overlap clock circuit 2042 for generating a non-overlap control signal VupAnd VdownAnd the high-side power switch and the low-side power switch of the same phase are prevented from being switched on at the same time.
The maximum dead time circuit 2043 is used for preventing the high-side power switch from not being turned on in one period due to the fact that the charging time of the ZVS circuit for the parasitic capacitance of the switching node is longer than the high-level time of the CLK signal, and enabling the system to work in an error state. If V is within the maximum dead timeFBGoes high, then VFBAn enable signal as a high side power switch control signal; if V is within the maximum dead timeFBIf it fails to go high, it is set to VMaxDeadTimeAs an enable signal for the high side power switch control signal.
Because the input power supply voltage of the circuit is generally higher, each power switch needs to adopt a high-voltage power device, and the specific withstand voltage values of each power switch and the capacitor are shown in fig. 9. Due to CZVSDC voltage, C, for balancing the switching nodes of two phases of the converter onlyZVSThe voltage at two ends is maintained at about 0V, and the voltage withstanding value of the power switch is not increased, so the ZVS implementation method does not increase the voltage pressure of each power switch.
The key points of the disclosure are as follows: the series capacitance converter ZVS is realized without increasing the withstand voltage value of the power switch.
By the proposed technique, a pair of inductive capacitors L is introduced between two switching nodes SWA and SWBZVSAnd CZVSAnd forming a ZVS circuit, sequentially charging the parasitic capacitance of the power stage switch node in the dead time, and judging whether ZVS is finished or not by using a zero voltage detection and dead time control circuit. Therefore, by calculating the amount of charge that needs to be transferred during the dead time, the desired L can be deducedZVSAnd CZVSAnd realizing ZVS of the converter. At the same time, due to CZVSDC voltage, C, for balancing the switching nodes of two phases of the converter onlyZVSThe voltage at two ends is maintained at about 0V, the withstand voltage value of the power switch cannot be increased, so the ZVS implementation method does not increase the voltage pressure of each power switch, and the comparison of various conditions is referred to as the following table 1:
withstand voltage value Not implementing ZVS Resonant ZVS technique Quasi square wave ZVS technique
Vin SBH Is free of SBH
Vin/2 SAH，SAL，SBL SAH，SBH，SAL，SBL SAH，SAL，SBL
TABLE 1
So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. Further, the above definitions of the various elements and methods are not limited to the various specific structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by those of ordinary skill in the art.
From the above description, those skilled in the art should have clear understanding of the zero-voltage switching implementation apparatus of the series capacitor dc-dc converter of the present disclosure.
In summary, the present disclosure provides a zero-voltage switching implementation apparatus for a series capacitor dc-dc converter, in which a pair of inductors L is introduced between two switching nodesZVSAnd a capacitor CZVSAnd forming a ZVS network, sequentially charging the parasitic capacitance of the power stage switch node in the dead time, and judging whether ZVS is finished or not by using a zero voltage detection and dead time control circuit. Therefore, by calculating the amount of charge that needs to be transferred during the dead time, the desired L can be deducedZVSAnd CZVSAnd realizing ZVS of the converter. At the same time, due to CZVSDC voltage, C, for balancing the switching nodes of two phases of the converter onlyZVSThe voltage at two ends is maintained at about 0V, and the voltage withstanding value of the power switch is not increased, so the ZVS implementation method does not increase the voltage pressure of each power switch. The invention provides a method for realizing series capacitor DC-DC converter ZVS,compared with the prior art, the withstand voltage value of the power switch can not be increased, and accordingly, the efficiency of the converter can be further improved.
It should also be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, used in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure.
And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.
Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify a corresponding element does not by itself connote any ordinal number of the element or any ordering of one element from another or the order of manufacture, and the use of the ordinal numbers is only used to distinguish one element having a certain name from another element having a same name.
In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.
Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Also in the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims (10)

1. A zero-voltage switching implementation of a series capacitor dc-dc converter, comprising:
power step-down circuit for converting high voltage dc power to ac power, comprising:
power switch SAHAnd an input voltage VinConnecting;
flying capacitor CFlyOne end of the power switch S is connected with the power switch through a switch node SWCAHConnecting;
power on SALThrough switch node SWA and flying capacitor CFlyThe other ends of the two are connected;
power switch SBHThrough switch node SWC and said power switch SAHConnecting; and
power switch SBLThrough openingA switching node SWB and the power switch SBHConnecting;
the ZVS circuit is used for charging and discharging parasitic capacitance of a switch node of the power voltage reduction circuit, two ends of the ZVS circuit are respectively connected with the switch node SWA and the switch node SWB, and the ZVS circuit comprises an inductor L which is arranged in seriesZVSAnd a capacitor CZVs；
The output filter circuit is used for stabilizing the alternating current provided by the power voltage reduction circuit into direct current and providing energy for an output load, and comprises:
inductors L respectively connected to the two ends of the ZVS and arranged in parallelAAnd an inductance LB(ii) a And
capacitor C and inductor LAAnd an inductance LBConnecting; and
the zero voltage detection and dead time control circuit is used for detecting whether the ZVS circuit is finished and generating corresponding dead time and comprises a zero voltage detection module and a dead time control circuit.
2. The zero-voltage switching implementation of a series capacitance DC-DC converter as claimed in claim 1,
in the state 1, the inductor LZVSAnd LAThe difference in current is the parasitic capacitance C of the switch nodes SWA and SWCALAnd CCLCharging, to power switch SAHParasitic capacitance C ofAHDischarge is performed due to flying capacitor CFlyThe voltage across the terminals is kept at half the input voltage, and the potential of the switching node SWC gradually rises with the potential of the switching node SWA.
3. The zero-voltage switching implementation of a series capacitance DC-DC converter as claimed in claim 1,
in the state 2, the SWA point potential of the switch node rises to half of the input voltage, the SWC point potential rises to the input voltage, and the zero voltage detection module detects the power switch SAHAfter the voltage difference between the two ends of the source and the drain is 0, the dead time control circuit controls SAHWhen the switch is turned on, the potential of the switch node SWA is higher than that of the SWB point, and the inductor LZVSCorresponding current iLZVSFlows from SWB to SWA and gradually decreases to 0 and reverses.
4. The zero-voltage switching implementation of a series capacitance DC-DC converter as claimed in claim 1,
in state 3, the power switch SAHTurn-off, inductance LZVSCorresponding current iLZVSAnd an inductance LAThe current direction is the same, and the parasitic capacitance CALAnd CCLDischarge, parasitic capacitance CAHAnd (6) charging.
5. The zero-voltage switching implementation of a series capacitance DC-DC converter as claimed in claim 1,
in state 4, the power switch SALIs turned on by SALThe current flowing from the source to the drain is equal to the current flowing through the inductor LA、LBAnd a power switch SBLThe sum of the currents of, the inductance LZVSIs greater than the inductance LBThe current of (2).
6. The zero-voltage switching implementation of a series capacitance DC-DC converter as claimed in claim 1,
in state 5, the power switch SBLTurn-off, inductance LZVSAnd LBThe difference in current is the parasitic capacitance C of the switch node SWBBLCharging, to power switch SBHParasitic capacitance C ofBHThe discharge is performed, and the potential at the switching node SWB gradually rises.
7. The zero-voltage switching implementation of a series capacitance DC-DC converter as claimed in claim 1,
in state 6, the zero voltage detection and dead time control circuit detects the rise of the potential of the switch node SWB to the power switch SBHDrain potential of (V)in/2 dead time control circuit controls power switch SBHOpening; the potential of the switch node SWB is higher than that of the switch node SWA, and ZVS inductive current iL flowing from the SWA to the SWBZVSGradually decreases to 0 and reverses.
8. The zero-voltage switching implementation of a series capacitance DC-DC converter as claimed in claim 1,
in state 7, the power switch SBHTurn-off, inductance LZVSCorresponding current iLZVSAnd an inductance LBThe current direction is the same, and the parasitic capacitance CBLDischarge, parasitic capacitance CBHAnd (6) charging.
9. The zero-voltage switching implementation of a series capacitance DC-DC converter as claimed in claim 1,
in state 8, the power switch SBLIs turned on by the power switch SBLThe current flowing from the source to the drain is equal to the current flowing through the inductor LA、LBAnd a power switch SALThe sum of the currents of, the inductance LZVSCorresponding current iLZVSGreater than inductance LAThe current of (2).
10. The series capacitor DC-DC converter zero voltage switching implementation device, power switch S, of claim 1AHAnd SALFlying capacitor CFlyAnd an inductance LAForm a subconverter PhaseA, a power switch SBHAnd SBLAnd an inductor LBForm a subconverter PhaseB when the inductor current I isLA、ILBDirection of and ZVS inductance LZVSCurrent iLZVSWhen the directions are opposite, iLZVSMust be specific to the inductive current ILA、ILBPeak value of large, ZVS inductive current and inductive current ILA、ILBThe difference between the minimum values is Idiff，minA、Idiff，minBAnd can be represented by the formulae (1) and (2).
Figure FDA0003080564870000031
Figure FDA0003080564870000032
LZVSThe energy of the power switch is larger than that of the parasitic capacitor, so that ZVS of the power switch can be realized; the ZVS inductance value L is taken under the condition that PhaseA and PhaseB power switches are opened at zero voltage respectivelyZVS，A、LZVS，BAnd can be represented by the formulas (3) and (4), and the final ZVS inductance LZVSSelecting LZVS，AAnd LZVS，BThe medium and small values meet the condition that the two-phase power switch can realize ZVS;
Figure FDA0003080564870000033
Figure FDA0003080564870000034
wherein D isADuty ratio of PhaseA, DBIs the duty cycle of PhaseB, fswIs the operating frequency of the converter.
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