CN113097306B - MOS device, manufacturing method thereof and ESD protection circuit - Google Patents

MOS device, manufacturing method thereof and ESD protection circuit Download PDF

Info

Publication number
CN113097306B
CN113097306B CN202110330027.7A CN202110330027A CN113097306B CN 113097306 B CN113097306 B CN 113097306B CN 202110330027 A CN202110330027 A CN 202110330027A CN 113097306 B CN113097306 B CN 113097306B
Authority
CN
China
Prior art keywords
conductive
side wall
source region
mos device
conductive channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110330027.7A
Other languages
Chinese (zh)
Other versions
CN113097306A (en
Inventor
刘琪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze Memory Technologies Co Ltd
Original Assignee
Yangtze Memory Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Priority to CN202110330027.7A priority Critical patent/CN113097306B/en
Publication of CN113097306A publication Critical patent/CN113097306A/en
Application granted granted Critical
Publication of CN113097306B publication Critical patent/CN113097306B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention provides a MOS device, a manufacturing method thereof and an ESD protection circuit. The MOS device comprises a semiconductor substrate, a grid structure arranged on the surface of the semiconductor substrate, a drain region and a source region which are arranged in the semiconductor substrate and positioned on two sides of the grid structure, and a first side wall which is arranged on the surface of the semiconductor substrate and positioned on one side of the grid structure. The grid structure comprises a first side wall adjacent to the drain region, and the first side wall covers the first side wall of the grid structure and the drain region. When the MOS device is used for ESD protection, the first side wall, the grid structure and the source region of the MOS device are grounded, so that zero potential is added to the first side wall, the effect of reducing and dispersing the electric field on the surface of the drain region can be achieved, the voltage withstand capability of the drain region is improved, and the breakdown voltage of the MOS device can be improved without increasing the size of the MOS device.

Description

MOS device, manufacturing method thereof and ESD protection circuit
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a MOS device for ESD protection, a method for manufacturing the same, and an ESD protection circuit including the MOS device.
Background
The grounded gate N-type field effect transistor (Gate Grounded NMOS, abbreviated as GGNMOS) is widely used in ESD (Electro Static Discharge, abbreviated as ESD) protection circuits in low/medium voltage applications due to its good compatibility with process platforms and excellent current drain capability.
Since the electrostatic current is usually large, it is generally required to connect a plurality of GGNMOS in parallel as an ESD protection device to improve the electrostatic protection capability of the ESD protection circuit. However, the connection area for grounding the gates of the GGNMOS in the existing ESD protection circuit is usually disposed at the outermost sides of the GGNMOS, so that parasitic resistances corresponding to the GGNMOS in different positions are different, and further parasitic transistors corresponding to the GGNMOS in different positions cannot be turned on at the same time, which results in poor uniformity of turning on the GGNMOS. When some of the GGNMOSs are turned on, other GGNMOSs are not easily turned on and cannot play a role in electrostatic protection, so that not only is the electrostatic protection capability of the ESD protection circuit reduced, but also the turned-on GGNMOSs may be broken down due to over-high discharge current. Therefore, the poor turn-on uniformity of GGNMOS also limits its application in high voltage applications.
In the prior art, the on resistance is generally improved by increasing the distance between the drain electrode and the grid electrode of the GGNMOS, so that the discharge current is reduced, and the problem that the GGNMOS is broken down due to poor on uniformity of a plurality of GGNMOSs is effectively solved. However, this method causes an increase in the size of the GGNMOS, increasing the production cost.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the invention provides the MOS device, the manufacturing method thereof and the ESD protection circuit, and the side wall of the MOS device covering the drain region is grounded, so that the effect of reducing and dispersing the electric field on the surface of the drain region can be achieved, the voltage withstand capability of the drain region is improved, the breakdown voltage of the MOS device can be improved on the basis of not increasing the size of the MOS device, and the risk of breakdown of the MOS device when the MOS device is used for ESD protection is reduced.
In order to achieve the above object, according to one aspect of the present invention, there is provided a MOS device, including a semiconductor substrate, a gate structure disposed on a surface of the semiconductor substrate, drain and source regions disposed in the semiconductor substrate and located at two sides of the gate structure, and a first sidewall disposed on a surface of the semiconductor substrate and located at one side of the gate structure; the grid structure comprises a first side wall adjacent to the drain region, and the first side wall covers the first side wall of the grid structure and the drain region; when the MOS device is used for ESD protection, the first side wall, the grid structure and the source region are grounded.
The invention also provides a manufacturing method of the MOS device, which comprises the following steps: providing a semiconductor substrate, and forming a gate structure on the surface of the semiconductor substrate; doping ions are respectively injected into the semiconductor substrate at two sides of the gate structure, so that a drain region and a source region are respectively formed at two sides of the gate structure; forming a first side wall and a second side wall on two sides of the grid structure respectively, wherein the first side wall covers the side wall on one side of the grid structure and the drain region, and the second side wall covers the side wall on the other side of the grid structure and the source region; and forming a first conductive channel, a second conductive channel and a third conductive channel which are respectively and electrically connected with the first side wall, the grid structure and the source region in one-to-one correspondence, wherein when the MOS device is used for ESD protection, the first conductive channel, the second conductive channel and the third conductive channel are all used for grounding so that the first side wall, the grid structure and the source region are also respectively grounded.
In still another aspect, the present invention further provides an ESD protection circuit, including a plurality of the MOS devices described above, where the plurality of MOS devices are disposed in parallel.
Compared with the prior art, the invention has the following beneficial effects: when the MOS device is used for ESD protection, the first side wall covering the drain region of the MOS device is grounded, so that zero potential is added to the first side wall, the effect of reducing and dispersing the electric field on the surface of the drain region can be achieved, the voltage withstand capability of the drain region can be improved, the breakdown voltage of the MOS device can be improved on the basis of not increasing the size of the MOS device, and the risk of breakdown of the MOS device when the MOS device is used for ESD protection is reduced.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a schematic partial cross-sectional structure of a MOS device according to an embodiment of the present invention.
Fig. 2 is a flowchart of a method for manufacturing a MOS device according to an embodiment of the present invention.
Fig. 3 is a sub-flowchart of step S3 in fig. 2.
Fig. 4 is a schematic diagram of sequentially forming a first oxide layer and a first nitride layer on a semiconductor substrate and a gate structure.
Fig. 5 is a schematic diagram of the first oxide layer and the first nitride layer shown in fig. 4 after etching to form a slot and an opening, wherein an ohmic connection layer is disposed in the opening.
Fig. 6 is a schematic view of the slots and openings shown in fig. 5, respectively, with a second nitride layer formed therein.
Fig. 7 is a sub-flowchart of step S4 in fig. 2.
Fig. 8 is a schematic view of the first nitride layer and the second nitride layer of fig. 6 covered with a second oxide layer.
Fig. 9 is a schematic diagram of forming a first via hole, a second via hole, and a third via hole after etching the second oxide layer shown in fig. 8.
Fig. 10 is a schematic diagram of forming a fourth through hole, a fifth through hole and a sixth through hole after etching the first nitride layer and the second nitride layer shown in fig. 9, wherein the first through hole and the fourth through hole are communicated to form a first channel, the second through hole and the fifth through hole are communicated to form a second channel, and the third through hole and the sixth through hole are communicated to form a third channel.
Fig. 11 is a schematic diagram of the first, second and third conductive channels shown in fig. 10 after the first, second and third channels are filled with a conductive medium.
Description of main reference numerals:
semiconductor substrate 10
Gate structure 20
First side wall 21
Second side wall 22
Slotting 23
Opening 24
Drain region 30
Heavily doped drain region 31
Lightly doped drain region 32
Source region 40
Heavily doped source region 41
Lightly doped source region 42
First side wall 51
Second side wall 52
First conductive path 61
Second conductive path 62
Third conductive via 63
Conductive layer 70
Ohmic contact layer 80
First through hole 91
Second through hole 92
Third through hole 93
Fourth through hole 94
Fifth through hole 95
Sixth through hole 96
First oxide layer 501
First nitride layer 502
Second nitride layer 503
Second oxide layer 504
The invention will be further described in the following detailed description in conjunction with the above-described figures.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
Referring to fig. 1, the present invention provides a MOS device, which includes a semiconductor substrate 10, a gate structure 20 disposed on a surface of the semiconductor substrate 10, a drain region 30 and a source region 40 disposed in the semiconductor substrate 10 and located at two sides of the gate structure 20, and a first sidewall 51 and a second sidewall 52 disposed on a surface of the semiconductor substrate 10 and located at two sides of the gate structure 20.
The semiconductor substrate 10 may be a silicon substrate, a germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate, may be a substrate including another element semiconductor or a compound semiconductor (for example, a gallium arsenide substrate, an indium phosphide substrate, or a silicon carbide substrate), or may be a composite substrate formed by stacking at least two of the above substrates. Further, the semiconductor substrate 10 may be lightly doped with P-type impurity ions (e.g., boron ions, indium ions, etc.) to become a P-type semiconductor substrate, or lightly doped with N-type impurity ions (e.g., arsenic ions, phosphorus ions, etc.) to become an N-type semiconductor substrate. As shown in fig. 1, in one embodiment of the present invention, the semiconductor substrate 10 is a P-type semiconductor substrate. In other embodiments, the semiconductor substrate 10 may be an N-type semiconductor substrate.
The gate structure 20 includes a gate dielectric layer (not shown) disposed on the surface of the semiconductor substrate 10 and a gate electrode (not shown) disposed on the surface of the gate dielectric layer, and the specific structure, function or forming process of the gate structure 20 is the same as that of the gate structure in the prior art, and is not described herein.
The drain region 30 and the source region 40 are doped regions formed by implanting dopant ions into the semiconductor substrate 10, wherein the dopant ions are of a different type from the impurity ions lightly doped in the semiconductor substrate 10. In the process of implanting the dopant ions into the semiconductor substrate 10 to form the drain region 30 and the source region 40, the implantation process of the dopant ions includes two ion implantations, the first ion implantation forms the respective lightly doped regions of the drain region 30 and the source region 40, and the second ion implantation forms the respective heavily doped regions of the drain region 30 and the source region 40, that is, the drain region 30 and the source region 40 include a lightly doped region and a heavily doped region, respectively, and the respective heavily doped regions of the drain region 30 and the source region 40 are located above and surrounded by the respective lightly doped regions. In one embodiment of the present invention, as shown in fig. 1, the drain region 30 and the source region 40 are both N-type doped regions formed by implanting N-type doped ions into the P-type semiconductor substrate, the drain region 30 includes an N-type heavily doped drain region 31 and an N-type lightly doped drain region 32, the source region 40 includes an N-type heavily doped source region 41 and an N-type lightly doped source region 42, and the MOS device is an NMOS device. In other embodiments, when the semiconductor substrate 10 is an N-type semiconductor substrate, the drain region 30 and the source region 40 may be P-type doped regions formed by implanting P-type doped ions into the N-type semiconductor substrate, and the MOS device may be a PMOS device.
The first sidewall 51 and the second sidewall 52 each include at least one oxide layer (e.g., a silicon dioxide layer) and/or at least one nitride layer (e.g., a silicon nitride layer). In one embodiment of the present invention, as shown in fig. 1, the first sidewall 51 and the second sidewall 52 are each formed by a first oxide layer and a first nitride layer, and the first nitride layer covers a side of the first oxide layer away from the semiconductor substrate 10.
It can be appreciated that the preparation of the semiconductor substrate 10, the gate structure 20, the drain region 30, the source region 40, the first sidewall 51 and the second sidewall 52 may be realized by conventional means in the prior art, and thus will not be described herein.
As shown in fig. 1, the gate structure 20 includes a first sidewall 21 adjacent to the drain region 30 and a second sidewall 22 adjacent to the source region 40, the first sidewall 51 covers the first sidewall 21 and the drain region 30 of the gate structure 20, and the second sidewall 52 covers the second sidewall 22 and the source region 40 of the gate structure 20. It should be noted that, when the MOS device provided by the present invention is used for ESD protection, the first side wall 51, the gate structure 20 and the source region 40 are all grounded, i.e., the MOS device may be a gate-grounded NMOS device or a gate-grounded PMOS device. By grounding the first side wall 51, the first side wall 51 becomes a field plate with zero potential, which can reduce and disperse the electric field on the surface of the drain region 30, so that the electric field on the surface of the drain region 30 becomes uniform, which is favorable for improving the voltage withstand capability of the drain region 30, thereby improving the breakdown voltage of the MOS device and reducing the risk of breakdown of the MOS device when the MOS device is used for ESD protection. Furthermore, the MOS device improves its breakdown voltage by grounding the first side wall 51, which does not increase the size of the MOS device, and thus does not increase the production cost.
Specifically, in one embodiment of the present invention, the MOS device further includes a first conductive channel 61, a second conductive channel 62, and a third conductive channel 63 corresponding to the first sidewall 51, the gate structure 20, and the source region 40 in a one-to-one correspondence. When the MOS device is used for ESD protection, the first conductive channel 61, the second conductive channel 62 and the third conductive channel 63 are all used for grounding, so that the first sidewall 51, the gate structure 20 and the source region 40 are grounded through the respective corresponding conductive channels. It should be noted that, the first conductive path 61, the second conductive path 62 and the third conductive path 63 may be common conductive elements such as conductive wires, or may be conductive paths formed by filling conductive media in a plurality of paths formed by the MOS device through an etching process, where the conductive media include, but are not limited to, tungsten, copper, aluminum, polysilicon, silicide or any combination thereof, and conductive materials filled in the first conductive path 61, the second conductive path 62 and the third conductive path 63 may be the same or different.
Further, in one embodiment of the present invention, the MOS device further includes a conductive layer 70 for grounding, one ends of the first conductive channel 61, the second conductive channel 62 and the third conductive channel 63 are respectively and correspondingly electrically connected to the first side wall 51, the gate structure 20 and the source region 40, and the other ends of the first conductive channel 61, the second conductive channel 62 and the third conductive channel 63 are respectively and electrically connected to the conductive layer 70, so that the first side wall 51, the gate structure 20 and the source region 40 are respectively grounded. In this embodiment, the first side wall 51, the gate structure 20 and the source region 40 are electrically connected to the grounded conductive layer 70 through the corresponding first conductive channel 61, second conductive channel 62 and third conductive channel 63, respectively, so that the first side wall 51, the gate structure 20 and the source region 40 are at the same potential, which is beneficial to improving the ESD protection capability of the MOS device. Of course, in other embodiments, the end of the first conductive channel 61 away from the first sidewall 51 may not be electrically connected to the conductive layer 70 and grounded through other forms.
The conductive layer 70 may be made of a conductive metal, such as copper or aluminum, or a conductive non-metallic material, such as graphite. In one embodiment of the present invention, the conductive layer 70 is a copper sheet.
As shown in fig. 1, the gate structure 20 has a first surface connected between the first sidewall 21 and the second sidewall 22, that is, a side surface of the gate structure 20 away from the semiconductor substrate 10, a slot 23 is formed between the first sidewall 51 and the second sidewall 52, the slot 23 exposes at least a portion of the first surface, and an end of the second conductive channel 62 away from the conductive layer 70 is electrically connected to the first surface of the gate structure 20 through the slot 23. As shown in fig. 1, the second side wall 52 is provided with an opening 24 at a position corresponding to the heavily doped source region 41 of the source region 40, the opening 24 exposes at least a portion of the heavily doped source region 41, and one end of the third conductive channel 63, which is far away from the conductive layer 70, is electrically connected to the heavily doped source region 41 through the opening 24. Note that, after the third conductive channel 63 passes through the second sidewall 52 through the opening 24, the opening 24 is filled with silicon nitride.
Preferably, in one embodiment of the present invention, the MOS device further includes an ohmic connection layer 80, and the ohmic connection layer 80 is disposed in the opening 24 and electrically connected between an end of the third conductive via 63 remote from the conductive layer 70 and the heavily doped source region 41 of the source region 40. The portion of the heavily doped source region 41 exposed through the opening 24 has better contact with the ohmic connection layer 80, so that the contact resistance between the third conductive channel 63 and the heavily doped source region 41 can be reduced, a better ohmic connection effect is achieved, and the reliability of the electrical connection between the third conductive channel 63 and the heavily doped source region 41 is improved.
The ohmic connection layer 80 may cover the entire surface of the portion of the heavily doped source region 41 exposed through the opening 24, or may cover only a portion of the surface of the portion of the heavily doped source region 41 exposed through the opening 24, so long as the ohmic connection between the third conductive via 63 and the heavily doped source region 41 is achieved.
Wherein the ohmic connection layer 80 is made of a material including, but not limited to, copper, aluminum, or silicide. In one embodiment of the present invention, the ohmic connection layer 80 is made of silicide.
In summary, when the MOS device provided by the present invention is used for ESD protection, the first side wall 51 covering the drain region 30 is grounded, so that zero potential is added to the first side wall 51, which can play a role in reducing and dispersing the electric field on the surface of the drain region 30, and can improve the voltage withstand capability of the drain region 30, thereby improving the breakdown voltage of the MOS device and reducing the risk of breakdown of the MOS device when the MOS device is used for ESD protection. Moreover, the overall structure of the MOS device is substantially the same as that of the existing MOS device with the grounded gate, but the self-breakdown voltage is improved by grounding the first side wall 51, so that the size of the MOS device is not increased, and further, the production cost is not increased.
Referring to fig. 2, the present invention further provides a method for manufacturing the MOS device, where the method specifically includes the following steps:
in step S1, a semiconductor substrate 10 is provided, and a gate structure 20 is formed on a surface of the semiconductor substrate 10. The semiconductor substrate 10 may be a silicon substrate, a germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate, may be a substrate including another element semiconductor or a compound semiconductor (for example, a gallium arsenide substrate, an indium phosphide substrate, or a silicon carbide substrate), or may be a composite substrate formed by stacking at least two of the above substrates; further, the semiconductor substrate 10 may be lightly doped with P-type impurity ions (e.g., boron ions, indium ions, etc.) to become a P-type semiconductor substrate, or lightly doped with N-type impurity ions (e.g., arsenic ions, phosphorus ions, etc.) to become an N-type semiconductor substrate; the gate structure 20 includes a gate dielectric layer disposed on the surface of the semiconductor substrate 10 and a gate electrode disposed on the surface of the gate dielectric layer, and the specific structure, function or forming process of the gate structure 20 is the same as that of the gate structure in the prior art, and is not described herein.
In step S2, dopant ions are respectively implanted into the semiconductor substrate 10 at both sides of the gate structure 20 to form drain regions 30 and source regions 40 at both sides of the gate structure 20, respectively. The doping ions are of different types from the impurity ions lightly doped in the semiconductor substrate 10, and the doping ion implantation process includes two ion implantations, the first ion implantation forms lightly doped regions of the drain region 30 and the source region 40, respectively, and the second ion implantation forms heavily doped regions of the drain region 30 and the source region 40, respectively, that is, the drain region 30 and the source region 40 include a lightly doped region and a heavily doped region, respectively, and the heavily doped regions of the drain region 30 and the source region 40 are located above and surrounded by the lightly doped regions, respectively.
In step S3, a first side wall 51 and a second side wall 52 are respectively formed on two sides of the gate structure 20, the first side wall 51 covers the side wall on one side of the gate structure 20 and the drain region 30, and the second side wall 52 covers the side wall on the other side of the gate structure 20 and the source region 40. The first sidewall 51 and the second sidewall 52 each include at least one oxide layer (e.g., a silicon dioxide layer) and/or at least one nitride layer (e.g., a silicon nitride layer), and the first oxide layer 501 and the first nitride layer 502 may be formed by one or more thin film deposition processes, which include, but are not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof, which are not described herein.
In step S4, a first conductive channel 61, a second conductive channel 62, and a third conductive channel 63 are formed, which are electrically connected to the first side wall 51, the gate structure 20, and the source region 40 in a one-to-one correspondence, respectively, wherein when the MOS device is used for ESD protection, the first conductive channel 61, the second conductive channel 62, and the third conductive channel 63 are all used for grounding, so that the first side wall 51, the gate structure 20, and the source region 40 are also grounded respectively.
The first conductive path 61, the second conductive path 62 and the third conductive path 63 may be conductive elements commonly used as wires, or may be conductive paths formed by filling conductive media in a plurality of paths formed by etching, wherein the conductive media include, but are not limited to, tungsten, copper, aluminum, polysilicon, silicide or any combination thereof, and conductive substances filled in the first conductive path 61, the second conductive path 62 and the third conductive path 63 may be the same or different.
When the MOS device manufactured by the manufacturing method of the MOS device is used for ESD protection, the first side wall 51 covering the drain region 30 is grounded, so that the first side wall 51 is a field plate added with zero potential, the effect of reducing and dispersing the electric field on the surface of the drain region 30 can be achieved, the electric field on the surface of the drain region 30 is further uniform, the voltage withstand capability of the drain region 30 is improved, breakdown voltage of the MOS device manufactured by the manufacturing method can be improved, and the risk of breakdown of the MOS device when the MOS device is used for ESD protection is reduced. Furthermore, when the prepared MOS device is used for ESD protection, the self-breakdown voltage is improved only by grounding the first side wall 51, so that the size of the MOS device is not increased, and further, the production cost is not increased.
In some embodiments of the present invention, the semiconductor substrate 10 is a P-type semiconductor substrate, and the drain region 30 and the source region 40 are both N-type doped regions formed by implanting N-type doped ions into the P-type semiconductor substrate, so that the MOS device manufactured according to the manufacturing method is an NMOS device with grounded gate. Of course, in other embodiments of the present invention, the semiconductor substrate 10 may be an N-type semiconductor substrate, and the drain region 30 and the source region 40 may be P-type doped regions formed by implanting P-type dopant ions into the N-type semiconductor substrate, so that the MOS device manufactured according to the manufacturing method is a PMOS device with a grounded gate.
Referring to fig. 3 to 5, in one embodiment of the present invention, the first sidewall 51 and the second sidewall 52 are each formed by a first oxide layer 501 and a first nitride layer 502, and the first nitride layer 502 covers a side of the first oxide layer 501 away from the semiconductor substrate 10. In the method for manufacturing the MOS device, the step of forming the first sidewall 51 and the second sidewall 52 on two sides of the gate structure 20 in step S3 specifically includes:
in step S31, as shown in fig. 4, a first oxide layer 501 is formed, where the first oxide layer 501 covers the gate structure 20 and the drain region 30 and the source region 40 on both sides thereof.
In step S32, as shown in fig. 4, a first nitride layer 502 is formed, and the first nitride layer 502 covers the first oxide layer 501.
In step S33, as shown in fig. 5, the first nitride layer 502 and the first oxide layer 501 that cover the surface of the gate structure 20 are sequentially etched to form a slot 23 penetrating through the first nitride layer 502 and the first oxide layer 501, where the slot 23 exposes at least a portion of the first surface of the gate structure 20, and the first nitride layer 502 and the first oxide layer 501 that are located on one side of the slot 23 form the first sidewall 51, the first nitride layer 502 and the first oxide layer 501 that are located on the other side of the slot 23 form the second sidewall 52, and the first sidewall 51 is separated from the second sidewall 52. The gate structure 20 includes a first sidewall 21 and a second sidewall 22 disposed opposite to each other, the first sidewall 21 is adjacent to the drain region 30, the second sidewall 22 is adjacent to the source region 40, the first sidewall 51 covers the first sidewall 21 and the drain region 30 of the gate structure 20, and the second sidewall 52 covers the second sidewall 22 and the source region 40 of the gate structure 20. A first surface of the gate structure 20, i.e., a side surface of the gate structure 20 remote from the semiconductor substrate 10, is connected between the first sidewall 21 and the second sidewall 22.
Referring to fig. 1 and fig. 5 together, in one embodiment of the present invention, the source region 40 includes a heavily doped region (i.e. the heavily doped source region 41 shown in fig. 1), and the step S33 of etching the first nitride layer and the first oxide layer covered on the surface of the gate structure in sequence further includes:
the first nitride layer 502 and the first oxide layer 501 are sequentially etched at positions corresponding to the heavily doped regions to form openings 24 (see fig. 5) penetrating the first nitride layer 502 and the first oxide layer 501, so that one end of the third conductive channel 63 penetrates the second sidewall 52 through the openings 24 and is electrically connected to the heavily doped regions (see fig. 1).
Before etching to form the trench 23 and the opening 24, a patterned photoresist layer may be formed on the surface of the first nitride layer 502, and the first nitride layer 502 and the first oxide layer 501 may be etched with the patterned photoresist layer as a mask to form the trench 23 and the opening 24. The slot 23 and the opening 24 are formed in the same etching process flow, which is beneficial to reducing etching steps and shortening the manufacturing time of the MOS device. Of course, in other embodiments, the slot 23 and the opening 24 may be formed separately in different etching process flows, and the opening 24 may be formed before the slot 23 or after the slot 23, which is not limited thereto.
Referring to fig. 1 and 6 again, in step S4, the step of forming a first conductive channel 61, a second conductive channel 62 and a third conductive channel 63 electrically connected to the first sidewall 51, the gate structure 20 and the source region 40 in a one-to-one correspondence manner includes:
in a first step, as shown in fig. 6, a second nitride layer 503 is formed in the trench 23 and the opening 24, such that the second nitride layer 503 covers the first surface of the gate structure 20 and the surface of the heavily doped region of the source region 40. Specifically, the portion of the first surface exposed through the slot 23 and the portion of the heavily doped region (i.e., the heavily doped source region 41 shown in fig. 1) exposed through the opening 24 are covered. The openings 24 and the two second nitride layers 503 in the trenches 23 may be formed simultaneously in the same process flow, or may be formed separately in different process flows. When the opening 24 and the two second nitride layers 503 in the trench 23 are formed in different process flows, the second nitride layers 503 in the trench 23 may be formed first, or the second nitride layers 503 in the opening 24 may be formed first. Preferably, in one embodiment of the present invention, the openings 24 and the two second nitride layers 503 in the trenches 23 are formed simultaneously in the same process flow, which is beneficial to shortening the manufacturing time of the MOS device.
In the second step, as shown in fig. 1, the first conductive channel 61, the second conductive channel 62 and the third conductive channel 63 are formed and electrically connected to the first sidewall 51, the gate structure 20 and the source region 40 in a one-to-one correspondence manner, wherein the second conductive channel 62 passes through the second nitride layer 503 in the trench 23, and the third conductive channel 63 passes through the second nitride layer 503 in the opening 24.
It is understood that the second nitride layer 503 may be the same or different from the first nitride layer 502. Preferably, in the embodiment of the present invention, the second nitride layer 503 and the first nitride layer 502 are both silicon nitride layers, so that the first conductive via 61, the second conductive via 62 and the third conductive via 63 are formed simultaneously in the same conductive via forming process.
Specifically, referring to fig. 7 to 11, the step S4 of forming the first conductive channel 61, the second conductive channel 62 and the third conductive channel 63 electrically connected to the first sidewall 51, the gate structure 20 and the source region 40 in a one-to-one correspondence manner specifically includes:
in step S41, as shown in fig. 8, after forming the second nitride layer 503 in the trench 23 and the opening 24, a second oxide layer 504 is formed, so that the second oxide layer 504 covers the first sidewall 51, the second sidewall 52, and the second nitride layer 503 in the trench 23 and the opening 24.
In this embodiment of the present invention, the materials of the second oxide layer 504 and the first oxide layer 501 may be the same or different, and in this embodiment, the second oxide layer 504 and the first oxide layer 501 are both silicon dioxide layers. It should be noted that, the second nitride layer 503 and the second oxide layer 504 may be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof, which are not described herein.
In step S42, as shown in fig. 9, the second oxide layer 504 covering the first sidewall 51 and the second nitride layer 503 is etched to form a first via 91, a second via 92 and a third via 93 penetrating the second oxide layer 504, respectively, where the first via 91 exposes at least a portion of the first nitride layer 502 of the first sidewall 51, and the second via 92 and the third via 93 expose at least a portion of the second nitride layer 503 in the slot 23 and the opening 24, respectively. It may be appreciated that before the second oxide layer 504 is etched, a patterned photoresist layer may be formed on the surface of the second oxide layer 504, and the second oxide layer 504 may be etched with the patterned photoresist layer as a mask, so as to form the first via 91, the second via 92, and the third via 93.
In step S43, as shown in fig. 10, the first nitride layer 502 exposed through the first via hole 91 and the second nitride layer 503 exposed through the second via hole 92 and the third via hole 93 are etched to form a fourth via hole 94 penetrating through the first nitride layer 502, a fifth via hole 95 penetrating through the second nitride layer 503 in the groove 23 and a sixth via hole 96 penetrating through the second nitride layer 503 in the opening 24, so that the first via hole 91 and the fourth via hole 94 are communicated to form a first channel, the second via hole 92 and the fifth via hole 95 are communicated to form a second channel, and the third via hole 93 and the sixth via hole 96 are communicated to form a third channel.
In step S44, as shown in fig. 11, the first channel, the second channel and the third channel are filled with a conductive medium, so as to form the first conductive channel 61, the second conductive channel 62 and the third conductive channel 63, respectively. Thereby, one end of the first conductive channel 61 is brought into contact with the first oxide layer 501 of the first sidewall 51, one end of the second conductive channel 62 is brought into contact with the first surface of the gate structure 20 through the slot 23, and one end of the third conductive channel 63 is brought into contact with the surface of the heavily doped source region 41 of the source region 40 through the opening 24. Wherein the conductive medium includes but is not limited to tungsten, copper, aluminum, polysilicon, silicide or any combination thereof, and the conductive substances filled in the first, second and third channels may be the same or different. In an embodiment of the present invention, the conductive material filled in the first channel, the second channel and the third channel is preferably tungsten.
As described above, in one embodiment of the present invention, the first conductive path 61, the second conductive path 62 and the third conductive path 63 are formed simultaneously in the same conductive path forming process, which is beneficial to reducing the process steps and shortening the manufacturing time of the MOS device. It should be understood that, in other embodiments, the first conductive path 61, the second conductive path 62 and the third conductive path 63 may be formed in a plurality of conductive path forming processes, and each of the first conductive path 61, the second conductive path 62 and the third conductive path 63 may be formed in a separate process, and any two of the first conductive path 61, the second conductive path 62 and the third conductive path 63 may be formed in the same process, and the other may be formed in a separate process, which is not limited thereto.
Preferably, as shown in fig. 5, in one embodiment of the present invention, before the step of forming the second nitride layer 503 in the trench 23 and the opening 24, the method for manufacturing the MOS device further includes the steps of: an ohmic connection layer 80 is formed within the opening 24, the ohmic connection layer 80 covering a portion of the heavily doped region of the source region 40 (i.e., the heavily doped source region 41) exposed through the opening 24. Therefore, after the third conductive channel 63 is formed, the ohmic connection layer 80 is electrically connected between the third conductive channel 63 and the heavily doped source region 41, and the heavily doped source region 41 has better contact with the ohmic connection layer 80 through the exposed portion of the opening 24, so that the contact resistance between the third conductive channel 63 and the heavily doped source region 41 can be reduced, a better ohmic connection effect is achieved, and the reliability of the electrical connection between the two is improved.
The ohmic connection layer 80 may cover the entire surface of the portion of the heavily doped source region 41 exposed through the opening 24, or may cover only a portion of the surface of the portion of the heavily doped source region 41 exposed through the opening 24, so long as the ohmic connection between the third conductive via 63 and the heavily doped source region 41 is achieved.
Wherein the ohmic connection layer 80 is made of a material including, but not limited to, copper, aluminum, or silicide. In one embodiment of the present invention, the ohmic connection layer 80 is made of silicide.
Further, referring to fig. 1 again, in one embodiment of the present invention, the method for manufacturing the MOS device further includes the following steps after step S4:
a conductive layer 70 is formed, the conductive layer 70 being for grounding. Wherein the conductive layer 70 may be made of a conductive metal (e.g., copper or aluminum) or a conductive non-metallic material (e.g., graphite), in one embodiment of the present invention, the conductive layer 70 is a copper sheet.
One ends of the first conductive path 61, the second conductive path 62, and the third conductive path 63 are electrically connected to the conductive layer 70, respectively. Therefore, the first side wall 51, the gate structure 20 and the source region 40 are electrically connected to the grounded conductive layer 70 through the corresponding first conductive channel 61, the second conductive channel 62 and the third conductive channel 63, respectively, so that the first side wall 51, the gate structure 20 and the source region 40 are at the same potential, which is beneficial to improving the ESD protection capability of the MOS device. It will be appreciated that, in other embodiments, the end of the first conductive channel 61 away from the first side wall 51 may not be electrically connected to the conductive layer 70, and may be grounded in other manners, which may also have an effect of improving the breakdown voltage of the MOS device.
The MOS device manufactured by the above manufacturing method has other functions and features similar to those of the foregoing MOS device, and the detailed description will refer to the relevant content of the foregoing MOS device and will not be repeated here.
Further, the invention also provides an ESD protection circuit, which comprises a plurality of MOS devices, wherein the MOS devices are arranged in parallel to improve the electrostatic discharge capacity. Each MOS device has the advantage of high breakdown voltage, and when the ESD protection circuit is used for electrostatic discharge, each MOS device is not easy to break down and has long service life.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.

Claims (14)

1. A MOS device, comprising:
a semiconductor substrate;
a gate structure arranged on the surface of the semiconductor substrate;
the drain region and the source region are arranged in the semiconductor substrate and positioned at two sides of the grid structure;
The first side wall is arranged on the surface of the semiconductor substrate and positioned at one side of the grid structure; and
a conductive layer grounded when the MOS device is used for ESD protection;
the grid structure comprises a first side wall adjacent to the drain region, and the first side wall covers the first side wall and the drain region;
when the MOS device is used for ESD protection, the first side wall, the grid structure and the source region are all electrically connected to the conductive layer, and the first side wall, the grid structure and the source region are in the same potential and are all grounded.
2. The MOS device of claim 1, further comprising a first conductive channel, a second conductive channel, and a third conductive channel in one-to-one correspondence with the first sidewall, the gate structure, and the source region, the first sidewall, the gate structure, and the source region respectively being in corresponding electrical connection with respective corresponding conductive channels;
when the MOS device is used for ESD protection, the first conductive channel, the second conductive channel and the third conductive channel are all electrically connected to the conductive layer, so that the first side wall, the gate structure and the source region are in the same potential and are all grounded.
3. The MOS device of claim 2, further comprising a second sidewall on the surface of the semiconductor substrate and on the other side of the gate structure, the gate structure further comprising a second sidewall adjacent to the source region, the second sidewall covering the second sidewall of the gate structure and the source region;
the source region comprises a heavily doped region, and one end of the third conductive channel passes through the position of the second side wall corresponding to the heavily doped region and is electrically connected with the heavily doped region.
4. The MOS device of claim 3, further comprising an ohmic connection layer electrically connected between one end of the third conductive channel and the heavily doped region.
5. The MOS device of any of claims 1 to 4, wherein the semiconductor substrate is a P-type semiconductor substrate, the drain region and the source region are both N-type doped regions formed by implanting N-type dopant ions into the P-type semiconductor substrate, and the MOS device is an NMOS device; or alternatively
The semiconductor substrate is an N-type semiconductor substrate, the drain region and the source region are P-type doped regions formed by implanting P-type doped ions into the N-type semiconductor substrate, and the MOS device is a PMOS device.
6. A method of manufacturing a MOS device, comprising:
providing a semiconductor substrate, and forming a gate structure on the surface of the semiconductor substrate;
doping ions are respectively injected into the semiconductor substrate at two sides of the gate structure, so that a drain region and a source region are respectively formed at two sides of the gate structure;
forming a first side wall and a second side wall on two sides of the grid structure respectively, wherein the first side wall covers the side wall on one side of the grid structure and the drain region, and the second side wall covers the side wall on the other side of the grid structure and the source region; and
and forming a first conductive channel, a second conductive channel and a third conductive channel which are respectively and correspondingly and electrically connected with the first side wall, the grid structure and the source region one by one, wherein when the MOS device is used for ESD protection, the first conductive channel, the second conductive channel and the third conductive channel are electrically connected to a grounded conductive layer so that the first side wall, the grid structure and the source region are in the same electric potential and are grounded.
7. The method for manufacturing a MOS device of claim 6, wherein the step of forming the first sidewall and the second sidewall on both sides of the gate structure comprises:
Forming a first oxide layer, wherein the first oxide layer covers the grid structure and the drain region and the source region at two sides of the grid structure;
forming a first nitride layer, wherein the first nitride layer covers the first oxide layer; and
etching the first nitride layer and the first oxide layer which cover the surface of the grid structure in sequence to form a slot penetrating through the first nitride layer and the first oxide layer, wherein the slot exposes at least one part of the first surface of the grid structure, the first nitride layer and the first oxide layer which are positioned at one side of the slot form the first side wall, the first nitride layer and the first oxide layer which are positioned at the other side of the slot form the second side wall, and the first side wall is separated from the second side wall; the first surface is remote from the semiconductor substrate.
8. The method of manufacturing a MOS device of claim 7, wherein the source region comprises a heavily doped region, and the step of sequentially etching the first nitride layer and the first oxide layer overlying the surface of the gate structure further comprises:
and sequentially etching the first nitride layer and the first oxide layer at positions corresponding to the heavily doped region to form an opening penetrating through the first nitride layer and the first oxide layer, so that one end of the third conductive channel penetrates through the second side wall through the opening and is electrically connected to the heavily doped region.
9. The method of manufacturing a MOS device of claim 8, wherein the step of forming a first conductive via, a second conductive via, and a third conductive via electrically connected to the first sidewall, the gate structure, and the source region, respectively, in a one-to-one correspondence comprises:
forming a second nitride layer in the grooves and the openings, so that the second nitride layer covers the first surface of the gate structure and the surface of the heavily doped region of the source region;
and forming the first conductive channel, the second conductive channel and the third conductive channel, and respectively and electrically connecting the first side wall, the gate structure and the source region in a one-to-one correspondence manner, wherein the second conductive channel passes through the second nitride layer in the slot, and the third conductive channel passes through the second nitride layer in the opening.
10. The method of manufacturing a MOS device of claim 9, wherein the second nitride layer is made of the same material as the first nitride layer, the first conductive channel, the second conductive channel, and the third conductive channel are formed simultaneously in the same conductive channel forming process, and the step of forming the first conductive channel, the second conductive channel, and the third conductive channel electrically connected to the first sidewall, the gate structure, and the source region in one-to-one correspondence respectively specifically comprises:
Forming a second oxide layer after forming a second nitride layer in the groove and the opening, so that the second oxide layer covers the first side wall, the second side wall and the second nitride layer in the groove and the opening;
etching the second oxide layer covered on the first side wall and the second nitride layer to form a first through hole, a second through hole and a third through hole penetrating through the second oxide layer, wherein the first through hole exposes at least a part of the first nitride layer of the first side wall, and the second through hole and the third through hole expose at least a part of the second nitride layer in the slot and the opening respectively;
etching the first nitride layer exposed through the first through hole and the second nitride layer exposed through the second through hole and the third through hole to form a fourth through hole penetrating through the first nitride layer, a fifth through hole penetrating through the second nitride layer in the slot and a sixth through hole penetrating through the second nitride layer in the opening, so that the first through hole and the fourth through hole are communicated to form a first channel, the second through hole and the fifth through hole are communicated to form a second channel, and the third through hole and the sixth through hole are communicated to form a third channel; and
And filling conductive media into the first channel, the second channel and the third channel respectively to form the first conductive channel, the second conductive channel and the third conductive channel respectively.
11. The method of manufacturing a MOS device of claim 10, wherein prior to the step of forming a second nitride layer within the trench and the opening, further comprising:
and forming an ohmic connection layer in the opening, wherein the ohmic connection layer covers the part of the heavily doped region of the source region exposed through the opening, so that the ohmic connection layer is electrically connected between one end of the third conductive channel and the heavily doped region.
12. The method of manufacturing a MOS device according to claim 10 or 11, wherein after the step of forming the first conductive path, the second conductive path, and the third conductive path, the method further comprises:
forming a conductive layer, wherein the conductive layer is used for grounding; and
and one ends of the first conductive channel, the second conductive channel and the third conductive channel are respectively and electrically connected with the conductive layer.
13. The method for manufacturing a MOS device according to claim 6, wherein the semiconductor substrate is a P-type semiconductor substrate, the drain region and the source region are both N-type doped regions formed by implanting N-type dopant ions into the P-type semiconductor substrate, and the MOS device is an NMOS device; or alternatively
The semiconductor substrate is an N-type semiconductor substrate, the drain region and the source region are P-type doped regions formed by injecting P-type doped ions into the N-type semiconductor substrate, and the MOS device is a PMOS device.
14. An ESD protection circuit comprising a plurality of MOS devices according to any one of claims 1 to 5, the plurality of MOS devices being arranged in parallel.
CN202110330027.7A 2021-03-27 2021-03-27 MOS device, manufacturing method thereof and ESD protection circuit Active CN113097306B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110330027.7A CN113097306B (en) 2021-03-27 2021-03-27 MOS device, manufacturing method thereof and ESD protection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110330027.7A CN113097306B (en) 2021-03-27 2021-03-27 MOS device, manufacturing method thereof and ESD protection circuit

Publications (2)

Publication Number Publication Date
CN113097306A CN113097306A (en) 2021-07-09
CN113097306B true CN113097306B (en) 2023-05-30

Family

ID=76670599

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110330027.7A Active CN113097306B (en) 2021-03-27 2021-03-27 MOS device, manufacturing method thereof and ESD protection circuit

Country Status (1)

Country Link
CN (1) CN113097306B (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3063085D1 (en) * 1979-05-30 1983-06-16 Xerox Corp Monolithic hvmosfet array
JPH07321312A (en) * 1994-05-24 1995-12-08 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
KR101051684B1 (en) * 2008-12-02 2011-07-25 매그나칩 반도체 유한회사 Electrostatic discharge protection device and manufacturing method
CN103035681B (en) * 2012-08-13 2015-08-19 上海华虹宏力半导体制造有限公司 The manufacture method of RF LDMOS device
CN107039498A (en) * 2016-02-04 2017-08-11 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Also Published As

Publication number Publication date
CN113097306A (en) 2021-07-09

Similar Documents

Publication Publication Date Title
US9252239B2 (en) Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts
US8466026B2 (en) Semiconductor device and method for manufacturing the same
US20110291186A1 (en) Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts
US20070176239A1 (en) Trenched MOSFETS with improved ESD protection capability
US20090065888A1 (en) Semiconductor device and a method of manufacturing the same
US8643101B2 (en) High voltage metal oxide semiconductor device having a multi-segment isolation structure
KR20150128563A (en) Semiconductor device
US10529819B2 (en) High voltage Schottky diode and manufacturing method thereof
CN113196500B (en) Semiconductor device and method for manufacturing the same
CN105679811A (en) Semiconductor device and method for manufacturing same
WO2011093953A2 (en) High voltage scrmos in bicmos process technologies
US8035161B2 (en) Semiconductor component
CN112635540A (en) LDMOS device and preparation method thereof
CN113097306B (en) MOS device, manufacturing method thereof and ESD protection circuit
CN112447829A (en) High voltage device and method for manufacturing the same
CN111092075A (en) Trench transistor structure and manufacturing method thereof
KR20160030030A (en) Semiconductor device
CN110491941B (en) High voltage device and method for manufacturing the same
US11996444B2 (en) Semiconductor device and manufacturing method of semiconductor device
US9825141B2 (en) Three dimensional monolithic LDMOS transistor
CN110931480B (en) Transistor element for electrostatic protection, method for manufacturing the same, and electrostatic protection device
CN116207045A (en) High voltage CMOS device and method for fabricating the same
CN116598332A (en) High voltage MOSFET device, manufacturing method and device
CN117410317A (en) High voltage device with multiple field plates and method of manufacturing the same
CN111384148A (en) Semiconductor assembly and its manufacturing method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant