CN113096709A - Physical unclonable function circuit and operation method thereof - Google Patents
Physical unclonable function circuit and operation method thereof Download PDFInfo
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- CN113096709A CN113096709A CN202110267847.6A CN202110267847A CN113096709A CN 113096709 A CN113096709 A CN 113096709A CN 202110267847 A CN202110267847 A CN 202110267847A CN 113096709 A CN113096709 A CN 113096709A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
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Abstract
The invention discloses a physical unclonable function circuit and an operation method thereof, belonging to the field of circuit design and comprising the following steps: the memristor array comprises a control module, a memristor array and a comparison amplifying circuit; the control module is used for selecting memristor units in an ith row and a jth column and memristor units in an ith row and a jth +1 column in the memristor array based on an externally input excitation signal; conducting an ith row of the memristor array, applying a high-level signal to a jth column of the memristor array, applying a low-level signal to a j +1 th column of the memristor array, and enabling the rest columns to be in a suspended state, so that the selected memristor unit forms a series circuit to perform voltage division operation, and the source line output where the ith row of the memristor array is located is a voltage division signal at a middle voltage division point of the series circuit; the comparison amplifying circuit is used for comparing the magnitude of the voltage division signal with the reference voltage to obtain a response signal; the invention is not influenced by crosstalk current, has higher accuracy of response result and greatly reduces the error rate.
Description
Technical Field
The present invention relates to the field of circuit design, and more particularly, to a physical unclonable function circuit and a method of operating the same.
Background
With the rapid development of electronic technology and internet of things (IoT), the security of hardware terminals is more and more concerned, and the encryption algorithm and the terminals have the problems of poor computing capability, limited resources and the like; moreover, the key obtained by the traditional encryption algorithm can be easily invaded and tampered by a third party, and is easily attacked by invasion to cause the cracking of the password, so that the safety performance of the equipment cannot be guaranteed, and therefore higher-level safety application is required, an unpredictable and unique random entropy source of the key is guaranteed, and the key can be safely and reliably stored, and therefore the concept of a physical unclonable function is provided.
Physically Unclonable Functions (PUFs) are in practical sense fingerprints of hardware, and a unique response is obtained for different PUF cells by the same stimulus. This also makes PUFs a popular study of current hardware security. The PUF utilizes a unique identifier generated by inevitable process deviation of a physical device in a process manufacturing process and self physical characteristics as an entropy source for key extraction, and has uniqueness, randomness and unclonability. Oxide-based memristors are an emerging non-volatile memory (NVM) that have large variability in resistance value distribution due to the random switching mechanism of oxygen vacancy generation and migration, which adds significant design challenges to the design of NVM. However, hardware-safe applications often contain true random variations, the variability of memristors can be exploited to design physically unclonable functions, and the random switching mechanism of oxygen vacancies can serve as a good source of entropy. The variability described above is due to the randomness created by the conductive filaments that are made up of oxygen vacancies between the two metal electrodes, where the conductive filaments can undergo reversible rupture and growth.
The PUF design related to the current memristor selects two memristor units to perform read comparison of currents by utilizing the selection of a stimulation (challenge) input as the unit addresses of the memristors, specifically R1 and R2 of the memristor units selected by the addresses, the read currents I1 and I2 flowing through the two units are compared, and the comparison result between the two currents is output through a final comparison amplifying circuit. If N bits need to be obtained, the operations are operated for N times, the method belongs to a typical strong PUF design and has more corresponding Pairs (CRPs), but in the operation process, the influence of crosstalk current cannot be avoided, so that the error rate is increased to a great extent, the Response result does not accord with the theoretical value, and the phenomenon that the HD is biased to be 1 or 0 occurs. In addition, in the address selection process, unselected units are all input with low level or grounded, which increases power consumption to a certain extent, and thus a PUF circuit structure with lower power consumption, more accurate output and better practicability is required.
Disclosure of Invention
In view of the above drawbacks and needs of the prior art, the present invention provides a physically unclonable function circuit and an operating method thereof, which solve the technical problem of low accuracy of response result due to the influence of crosstalk current in the prior art.
In order to achieve the above object, in a first aspect, the present invention provides a physical unclonable function circuit, including: the memristor array comprises a control module, a memristor array and a comparison amplifying circuit;
the control module is respectively connected with each word line and each bit line of the memristor array; the source line of the memristor array is connected with the first input end of the comparison amplifying circuit, and the second input end of the comparison amplifying circuit is connected with a reference voltage Vref；
The control module is used for selecting memristor units in an ith row and a jth column and memristor units in an ith row and a jth +1 column in the memristor array based on an externally input excitation signal; conducting an ith row of the memristor array, applying a high-level signal to a jth column of the memristor array, applying a low-level signal to a j +1 th column of the memristor array, and enabling the rest columns to be in a suspended state, so that the selected memristor unit forms a series circuit to perform voltage division operation, and the source line output where the ith row of the memristor array is located is a voltage division signal at a middle voltage division point of the series circuit; wherein i ═ 0,1, 2.. m-1; j ═ 0,1,2,. n-1; m is the row number of the memristor array, and n is the column number of the memristor array;
the comparison amplifying circuit is used for comparing the divided voltage signal with a reference voltage VrefTo obtain a response signal.
Further preferably, the control module includes: the logic control unit, word line decoder, bit line decoder and transistor switch array;
the output end of the logic control unit is respectively connected with the input end of the word line decoder, the input end of the bit line decoder, the input end of the transistor switch array and the enabling end of the comparison amplifying circuit; the output end of the word line decoder is connected with each word line of the memristor array, and the output end of the bit line decoder is connected with the enabling end of the transistor switch array; the output end of the transistor switch array is connected with each bit line of the memristor array; the number of transistors in the transistor switch array is the same as the number of columns of the memristor array, and the output end of each transistor in the transistor switch array is connected with each bit line in the memristor array in a one-to-one correspondence mode;
the logic control unit is used for controlling the word line decoder to decode row address information in the excitation signal to obtain a row selection middle address of the memristor array so as to determine a selected row i of the memristor array and conduct the memristor unit on the selected row i;
controlling a bit line decoder to decode column address information in external excitation to obtain a column selection address of the memristor array so as to determine a selected column j and a selected column j +1 of the memristor array; and controlling the transistor switch array to open the corresponding transistor switch, so that a bit line where the selected column j is positioned receives a high-level signal, and a bit line where the selected column j +1 is positioned receives a low-level signal, so that the selected memristor units in the ith row and the jth column and the memristor units in the ith row and the jth +1 column are conducted to form a series circuit to perform voltage division operation, and all unselected memristor units are in a non-conducting state.
Further preferably, the transistors in the transistor switch array are NMOS transistors, gates of the NMOS transistors are enable terminals of the transistors, drains of the NMOS transistors are input terminals of the transistors, and sources of the NMOS transistors are output terminals of the transistors.
Further preferably, the comparison amplifying circuit is a sense amplifier.
Further preferably, a random resistance value distribution formed by a high resistance state of each memristor cell in the memristor array after the arming and resetting operations is used as an entropy source of the PUF key.
Further preferably, if the divided voltage signal is smaller than the reference value VrefThen the response signal is "0"; otherwise, the response signal is "1".
Further preferably, the source lines of the memristor array are connected to the same bus, and are connected to the first input end of the comparison amplifying circuit through the bus;
the above-mentioned reference voltage VrefThe method is a median of voltage values of all memristor units when all memristors in the memristor array are in a high-resistance state.
Further preferably, the number of the comparison amplifying circuits is the same as the number of rows of the memristor array; the first input end of each comparison amplifying circuit is connected with each source line in the memristor array in a one-to-one correspondence mode;
reference voltage V connected to each comparison and amplification circuitrefWhen all the memristors on the source line correspondingly connected with the comparison amplifying circuit are in a high-impedance state, the median of the voltage values of all the memristor units on the source line is obtained.
In a second aspect, the present invention provides a method for operating the physical unclonable function circuit of the first aspect, including the steps of:
s1, selecting memristor units in the ith row and the jth column and memristor units in the ith row and the jth +1 column in the memristor array based on an externally input excitation signal; conducting an ith row of the memristor array, applying a high-level signal to a jth column of the memristor array, applying a low-level signal to a j +1 th column of the memristor array, and enabling the rest columns to be in a suspended state, so that the selected memristor unit forms a series circuit to perform voltage division operation, and the source line output where the ith row of the memristor array is located is a voltage division signal at a middle voltage division point of the series circuit; wherein i ═ 0,1, 2.. m-1; j ═ 0,1,2,. n-1; m is the row number of the memristor array, and n is the column number of the memristor array;
s2, comparing the divided voltage signal with a reference voltage VrefTo obtain a response signal.
Further preferably, a 1-bit response signal is obtained every time the excitation signal is input; respectively inputting N times of excitation signals to obtain N response signals to form N-bit response signals; wherein N is a positive integer.
Generally, by the above technical solution conceived by the present invention, the following beneficial effects can be obtained:
1. the invention provides a physical unclonable function circuit, wherein each time two adjacent memristor units are gated, a high-level signal and a low-level signal are respectively applied, and other non-gated memristor units are suspended, so that the selected memristor units form a series circuit to perform voltage division operation; according to the invention, the response signal is read by comparing the magnitude of the voltage division signal with the magnitude of the reference voltage, so that the influence of crosstalk current is avoided, the accuracy of the response result is higher, and finally, the read data is more stable.
2. According to the physical unclonable function circuit, address selection is carried out through the bit decoder, the bit decoder gates two adjacent memristor units each time, and other ungated units are in a suspended state and are not applied with excitation signals, so that the physical unclonable function circuit can achieve lower power consumption in the working period.
3. The physical unclonable function circuit comprises a transistor switch array, the switching conditions of a selected unit and unselected units can be controlled through the design of the transistor switch array, a logic control unit controls an enabling end of the transistor switch array after address selection, two bit line ends of the selected memristor unit respectively receive high and low levels, and unselected memristor storage units are all placed in a non-conducting state, so that the selected memristor unit forms a series circuit to perform voltage division operation, the influence of crosstalk current is avoided, and the bit error rate is reduced to a great extent.
4. According to the physical unclonable function circuit provided by the invention, each source line of the memristor array can be connected to the same bus and is connected with the first input end of the comparison amplifying circuit through the bus, so that the reading operation can be carried out by sharing the SL source line, and the circuit design area occupied by more sensitive amplifiers is avoided.
5. The reading times of the physical unclonable function circuit provided by the invention are determined by the writing times of the excitation signal, the reading value of single operation is 1bit, when the reading value of N bits needs to be obtained, N times of writing operation needs to be carried out, and N challenge response pairs can be obtained in the N times of writing operation, so that the unpredictability of response bits is expanded to a great extent; and the accuracy of output response reading is greatly improved by the successive reading operation.
6. The physical unclonable function circuit provided by the invention comprises a memristor array, and the resistance value of the memristor unit is randomly changed in different reading and writing periods, so that the entropy source used before can be changed by updating the resistance value of the memristor storage unit by using the cycle period, thereby achieving the purpose of reconstruction, and the physical unclonable function circuit provided by the invention has better reconfigurability.
Drawings
FIG. 1 is a schematic diagram of a physical unclonable function circuit according to the present invention;
FIG. 2 is a schematic diagram of a transistor switch array in a physically unclonable function circuit according to the present invention;
FIG. 3 is a schematic diagram of the output read logic of the physical unclonable function circuit according to the present invention;
fig. 4 is a schematic diagram of a physical unclonable function circuit according to embodiment 1 of the present invention;
fig. 5 is a schematic diagram of a physical unclonable function circuit according to embodiment 2 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
In order to achieve the above object, in a first aspect, the present invention provides a physical unclonable function circuit, as shown in fig. 1, including: the memristor-based power supply comprises a control module 1, a memristor array 2 and a comparison amplifying circuit 3;
the control module 1 is respectively connected with each word line and bit line of the memristor array 2; the source line of the memristor array 2 is connected with the first input end of the comparison amplifying circuit 3, and the second input end of the comparison amplifying circuit 3 is connected with the reference voltage Vref；
The control module 1 is used for selecting memristor units in an ith row and a jth column and memristor units in an ith row and a jth +1 column in the memristor array 2 based on an externally input excitation signal; conducting the ith row of the memristor array 2, applying a high-level signal to the jth column of the memristor array 2, applying a low-level signal to the jth +1 column of the memristor array 2, and keeping the rest columns in a suspended state, so that the selected memristor unit forms a series circuit to perform voltage division operation, and the source line output of the ith row of the memristor array 2 is a voltage division signal at the middle voltage division point of the series circuit; wherein i ═ 0,1, 2.. m-1; j ═ 0,1,2,. n-1; m is the row number of the memristor array, and n is the column number of the memristor array;
the comparison amplifying circuit 3 is used for comparing the divided voltage signal with a reference voltage VrefTo obtain a response signal.
The comparison and amplification circuit 3 is preferably a sense amplifier and comprises two input ends and an output end, wherein the input end SA _ IN1 is connected with a circuit middle voltage division point of two selected series units, namely a source line where the ith row of the memristor array is located; the other input terminal SA _ IN2 is connected with a reference voltage VrefAnd the output end is SA _ OUT.
The physical unclonable function circuit is a PUF circuit based on voltage division type, two corresponding addresses are selected through input, a pulse signal is applied to corresponding excitation, the resistance values of two memristor units are compared in a mode of voltage division of two cells, and a 1-bit response bit is finally output through a comparison amplifying circuit.
Preferably, the control module 1 comprises: a logic control unit 11, a word line decoder 12, a bit line decoder 13, and a transistor switch array 14;
the output end of the logic control unit 11 is connected with the input end of the word line decoder 12, the input end of the bit line decoder 13, the input end of the transistor switch array 14 and the enable end of the comparison and amplification circuit respectively; the output end of the word line decoder 12 is connected with each word line of the memristor array 2, and the output end of the bit line decoder 13 is connected with the enabling end of the transistor switch array 14; the output end of the transistor switch array 14 is connected with each bit line of the memristor array 2; the number of transistors in the transistor switch array 14 is the same as the number of columns of the memristor array 2, the number of transistors in the transistor switch array is the same as the number of columns of the memristor array, and the output end of each transistor in the transistor switch array is connected with each bit line in the memristor array in a one-to-one correspondence manner; the transistors in the transistor switch array are numbered according to 0,1, 2.. n-1, and the output end of the jth transistor is correspondingly connected with the jth column bit line of the memristor array 2;
preferably, the transistors in the transistor switch array 14 are NMOS transistors, the gates of which are the enabling terminals of the transistors, the drains of which are the input terminals of the transistors, and the sources of which are the output terminals of the transistors. Specifically, as shown in fig. 2, the transistor switch array 14 in this embodiment is composed of n NMOSFET transistors with small on-resistance, and its gate enable terminal and each output terminal B of the bit decoder0～n-1 are connected in one-to-one correspondence, the drain input is connected with the logic control unit 11, the source output is connected with the memristor array 2 bit line BL0～n-1 are connected in a one-to-one correspondence.
The logic control unit 11 controls the states of the transistor switch and the enable terminal EN of the comparison amplifying circuit 3, and the address selection of the word line decoder 12 and the bit line decoder 13, and is mainly used for dividing excitation signals of selected and unselected units and used as the address selection input of a decoder module; by applying a pulse excitation signal, an address is received and selected by a decoder, and generation of a read/write signal is controlled.
Specifically, the logic control unit 11 is configured to: 1) the word line decoder 12 is controlled to decode row address information in the excitation signal to obtain a row selection address of the memristor array 2 so as to determine a selected row i of the memristor array 2, and the memristor units on the selected row i are conducted; 2) controlling a bit line decoder 13 to decode column address information in external excitation to obtain a column selection address of the memristor array 2 so as to determine a selected column j and a selected column j +1 of the memristor array 2; and controlling the transistor switch array 14 to open the corresponding transistor switch, so that the bit line where the selected column j is positioned receives a high-level signal, and the bit line where the selected column j +1 is positioned receives a low-level signal, so that the selected memristor units in the ith row and the jth column and the memristor units in the ith row and the jth +1 column are conducted to form a series circuit to perform voltage division operation, and all unselected memristor units are in a non-conducting state.
In the control process, the selected memristor unit and the unselected memristor unit need to be operated respectively, and the selected memristor unit forms a series circuit. For example, bit line BL0The memristor unit receives the high level of a bit line decoder, bit line BL1The memristor unit receives the low level of a bit line decoder, and the memristor units on other unselected bit lines should receive the low level according to the decoder principle, but the bit line BL2～n-1The memristor units are controlled to be not conducted through the enabling end of the transistor switch array, so that the unselected units are in the closed state, and the transistor switch array is controlled by the logic control circuit. In this embodiment, when the bit decoder circuit is controlled by verilog programming, taking a 3-8-line decoder as an example, the correspondence between the address and the output is as follows: 3'd0, data _ out is 8' b0000_ 0011; 3'd1 data _ out is 8' b0000_ 0110; 3'd3, data _ out is 8' b0001_ 1000; 3'd4, data _ out is 8' b0011_ 0000; 3'd5 data _ out is 8' b0110_ 0000; 3'd6, data _ out is 8' b1100_ 0000; 3'd7, data _ out is 8' b1000_ 0001; that is, when the information inputted to the bit line decoder is 000, the transistors with the number 0 and the number 1 in the transistor switch array are turned on, and the bit line BL is set0A high level is applied to the column, at bit line BL1Applying a low level on the column; when the information input to the bit line decoder isAt 001, the transistors with number 1 and number 2 in the transistor switch array are turned on, and bit line BL is connected1A high level is applied to the column, at bit line BL2Applying a low level on the column; and so on.
The output of the bit decoder is used as an enabling signal of a grid switch of the transistor switch array to control the selection of the memristor unit; the voltage type circuit structure is based on the principle that two selected memristor units form a series circuit structure to carry out series voltage division to obtain a voltage division value. The cell set to 1 is the selected cell, the cell set to 0 is the unselected cell, the transistor of the selected cell is turned on, the logic control unit provides the drain input signal to the two cells, and the operating state of the logic control unit connected to the transistor switch drain terminal is the address corresponding output of the conventional decoder (for example, 3-8 line decoder 3'd0: data _ out: 8' b0000_ 0001). The corresponding transistor for the unselected cell is in an off state, i.e., a floating state.
Further, as shown in fig. 3, a schematic diagram of an output reading logic of a physical unclonable function circuit is shown, at this time, memristor units in the ith row and the jth column in the memristor array and memristor units in the ith row and the jth +1 column form a series circuit to perform voltage division operation, and a voltage division signal at a middle voltage division point of the series circuit, that is, a voltage division voltage value V is output through a source line where the ith row of the memristor array is locatedm(ii) a When the voltage value V is dividedmLess than a reference value VrefWhen the response signal is '0', the response signal is output by an output end SA _ OUT of the comparison amplifying circuit; when the partial pressure value VmGreater than or equal to a reference value VrefWhen the signal is "1", the response signal is "1", and the signal is output from the output terminal SA _ OUT of the comparison amplification circuit.
It should be noted that the states of the memristor device are divided into a low resistance state LRS and a high resistance state HRS, wherein the resistance distribution of the LRS is compact and continuous, and the discrete difference of the resistance distribution of the HRS is large, so that the high resistance state HRS can be used as the entropy source of the PUF circuit; in the invention, a random resistance value distribution formed by a high-resistance state HRS after each memristor unit of a memristor array is subjected to the formining and reset operations is used as an entropy source of a PUF key. Different memristor units are addressed based on an external excitation signal, high-low level signals are given to the selected units through the transistor switch array, and unselected units are in a suspended state. The selected memristor memory cells form a series circuit to perform voltage division operation, and a voltage division signal and a reference voltage are compared through a sensitive amplifier in a comparison amplification circuit to obtain a final response value of '0'/'1'.
Preferably, as shown in fig. 4, in an alternative embodiment 1, the source lines of the memristor array are connected to the same bus, and are connected to the first input terminal of the comparison amplifying circuit through the bus. This way of sharing the SL source line for read operations can avoid using more compare amplifier circuits to occupy circuit design area. In embodiment 1, configuration quenching operation is required to be performed on an initial state of a memristor to activate a conductive filament inside a memristor memory cell, the configured memristor presents a low-resistance state, then reset operation is performed on the memristor device, and the conductive filament inside the memristor memory cell is broken to present a high-resistance state; then setting the reference voltage V in a high-impedance staterefThe reference voltage VrefAccording to the voltage value setting of all memristor units in the memristor array, taking the median of the voltage values of all memristor units as the setting reference voltage VrefThe number of data "1" or "0" to be read is guaranteed to be 50% each.
Preferably, as shown in fig. 5, in an alternative embodiment 2, the number of the comparison amplifying circuits is the same as the number of rows of the memristor array; the first input end of each comparison amplifying circuit is connected with each source line in the memristor array in a one-to-one correspondence mode; namely, the comparison and amplification circuits are numbered according to 0,1, 2.. m-1, and a source line where the ith row of the memristor array is located is connected with the first input end of the ith comparison and amplification circuit. Reference voltage V connected to each comparison and amplification circuitrefWhen all the memristors on the source line correspondingly connected with the comparison amplifying circuit are in a high-impedance state, the median of the voltage values of all the memristor units on the source line is obtained. Note that, similarly to embodiment 1, the reference voltage V is set in a high-resistance staterefWhen the ith row of the memristor array is selected, the ith row is selectedTaking the median of all memristor unit voltage values as a reference voltage V accessed by a comparison amplifying circuit corresponding to the ith rowrefiEnsuring that the number of the read data of 1 or 0 respectively accounts for 50 percent; in addition, the comparison amplification circuit and the row lines are in one-to-one butt joint in the embodiment 2, so that the extra voltage division condition generated by the ith row to the ith row in the (i-1) th row under the condition of common source lines can be effectively avoided, and the reliability of the PUF circuit can be improved.
Examples 1 and 2 reference voltage V as describedrefThe selection mode can ensure the unbiased property of the reading result and the stability of the PUF circuit.
In a second aspect, the present invention provides a method for operating the physical unclonable function circuit of the first aspect, including the steps of:
s1, selecting memristor units in the ith row and the jth column and memristor units in the ith row and the jth +1 column in the memristor array based on an externally input excitation signal; conducting an ith row of the memristor array, applying a high-level signal to a jth column of the memristor array, applying a low-level signal to a j +1 th column of the memristor array, and enabling the rest columns to be in a suspended state, so that the selected memristor unit forms a series circuit to perform voltage division operation, and the source line output where the ith row of the memristor array is located is a voltage division signal at a middle voltage division point of the series circuit; wherein i ═ 0,1, 2.. m-1; j ═ 0,1,2,. n-1; m is the row number of the memristor array, and n is the column number of the memristor array;
s2, comparing the divided voltage signal with a reference voltage VrefTo obtain a response signal.
Preferably, a 1-bit response signal is obtained every time the excitation signal is input; respectively inputting N times of excitation signals to obtain N response signals to form N-bit response signals; n is a positive integer.
It should be noted that the physical unclonable function circuit provided by the invention is realized based on the characteristics of a memristor array, electrical activation is carried out by using a memristor device in a formiming process, and the distribution of different resistance values formed in the process of generating a conductive filament reset/set is used as an entropy source of a physical unclonable function. The operation of the PUF circuit is performed byThe on-off of the word line is controlled, the voltage division value of the selected memristor unit and a reference value V are carried out by writing an excitation signal into the word line and comparing an amplifying circuitrefThe PUF can be read and written once by comparing the two. The read times of the PUF circuit are determined by the write times of the stimulus signal. Generally, the output of a PUF circuit is composed of multiple bits, and since only one word line can be selected for writing at a time, the read value of a single operation is 1 bit; if the read value of N bits is to be obtained, N times of write operations are carried out; n challenge response pairs can be obtained in N writing operations, and the unpredictability of response bits is expanded to a great extent; and the accuracy of output response reading is greatly improved by the successive reading operation. For example, a 16-bit write operation is performed, an address signal generated by an input signal is detected by a 16-line word line decoder circuit, a read operation is performed when a high level is written, and a read operation is not performed when a low level is written, and a 16-bit response output can be finally obtained by repeating the operations 16 times.
Further, the PUF circuit provided by the invention can be reconstructed by performing C2C (cycle to cycle) operation on the memristor unit, and since the resistance value of the memristor unit is changed randomly in different reading and writing cycles, the resistance value of the memristor unit is updated by using the cycle, the previously used entropy source can be changed, and the reconstruction purpose can be achieved. The reconstruction is specifically implemented as follows: firstly, the SET voltage is reapplied to the memristor device to restore to the low resistance state LRS, then the same pulse reset voltage is applied to restore the memristor to the high resistance state HRS, and the operation steps S1-S2 are repeated.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A physically unclonable function circuit, comprising: the memristor array comprises a control module, a memristor array and a comparison amplifying circuit;
the control module is respectively connected with each word line and each bit line of the memristor array; the source line of the memristor array is connected with the first input end of the comparison amplifying circuit, and the second input end of the comparison amplifying circuit is connected with a reference voltage Vref；
The control module is used for selecting memristor units in an ith row and a jth column and memristor units in an ith row and a jth +1 column in the memristor array based on an externally input excitation signal; conducting an ith row of the memristor array, applying a high-level signal to a jth column of the memristor array, applying a low-level signal to a j +1 th column of the memristor array, and enabling the rest columns to be in a suspended state, so that the selected memristor unit forms a series circuit to perform voltage division operation, wherein the source line output of the ith row of the memristor array is a voltage division signal at a middle voltage division point of the series circuit; wherein i ═ 0,1, 2.. m-1; j ═ 0,1,2,. n-1; m is the row number of the memristor array, and n is the column number of the memristor array;
the comparison amplifying circuit is used for comparing the divided voltage signal with a reference voltage VrefTo obtain a response signal.
2. The physically unclonable function circuit of claim 1, wherein the control module comprises: the logic control unit, word line decoder, bit line decoder and transistor switch array;
the output end of the logic control unit is respectively connected with the input end of the word line decoder, the input end of the bit line decoder, the input end of the transistor switch array and the enabling end of the comparison amplifying circuit; the output end of the word line decoder is connected with each word line of the memristor array, and the output end of the bit line decoder is connected with the enabling end of the transistor switch array; the output end of the transistor switch array is connected with each bit line of the memristor array; the number of transistors in the transistor switch array is the same as the number of columns of the memristor array, and the output end of each transistor in the transistor switch array is connected with each bit line in the memristor array in a one-to-one correspondence mode;
the logic control unit is used for controlling the word line decoder to decode row address information in the excitation signal to obtain a row selection middle address of the memristor array so as to determine a selected row i of the memristor array and conduct the memristor unit on the selected row i;
controlling a bit line decoder to decode column address information in external excitation to obtain a column selection address of the memristor array so as to determine a selected column j and a selected column j +1 of the memristor array; and controlling the transistor switch array to open the corresponding transistor switches, so that the bit line where the selected column j is positioned receives a high-level signal, and the bit line where the selected column j +1 is positioned receives a low-level signal, so that the memristor units of the selected ith row and jth column and the memristor units of the ith row and jth +1 column are conducted to form a series circuit to perform voltage division operation, and all unselected memristor units are in a non-conducting state.
3. The physically unclonable function circuit of claim 2, wherein the transistors in the transistor switch array are NMOS transistors with gates being enable terminals, drains being input terminals, and sources being output terminals.
4. The physically unclonable function circuit of claim 1, wherein the comparison amplification circuit is a sense amplifier.
5. The physically unclonable function circuit of claim 1, wherein a random distribution of resistance values formed by high resistance states of each memristor cell in the memristor array after the forming and reset operations is used as an entropy source for PUF keys.
6. The physically unclonable function circuit of claim 1, wherein if the divided voltage signal is less than the reference value VrefThen the response signal is "0"; otherwise, the response signal is "1".
7. The physically unclonable function circuit of any of claims 1-6, wherein the source lines of the memristor array are connected to the same bus and are connected to the first input of the comparison amplification circuit through the bus;
the reference voltage VrefThe method is characterized in that when all memristors in the memristor array are in a high-resistance state, the median of voltage values of all memristor units is obtained.
8. The physically unclonable function circuit according to any of claims 1 to 6, wherein the number of comparison and amplification circuits is the same as the number of rows of the memristor array; the first input end of each comparison amplifying circuit is correspondingly connected with each source line in the memristor array one by one;
the reference voltage V accessed by each comparison amplifying circuitrefWhen all the memristors on the source line correspondingly connected with the comparison amplifying circuit are in a high-impedance state, the median of the voltage values of all the memristor units on the source line is obtained.
9. A method of operating a physically unclonable function circuit according to any of claims 1-8, comprising the steps of:
s1, selecting memristor units in the ith row and the jth column and memristor units in the ith row and the jth +1 column in the memristor array based on an externally input excitation signal; conducting an ith row of the memristor array, applying a high-level signal to a jth column of the memristor array, applying a low-level signal to a j +1 th column of the memristor array, and enabling the rest columns to be in a suspended state, so that the selected memristor unit forms a series circuit to perform voltage division operation, and the source line output where the ith row of the memristor array is located is a voltage division signal at a middle voltage division point of the series circuit; wherein i ═ 0,1, 2.. m-1; j ═ 0,1,2,. n-1; m is the row number of the memristor array, and n is the column number of the memristor array;
s2, comparing the divided voltage signal with a reference voltage VrefTo obtain a response signal.
10. The method of operating a physically unclonable function circuit according to claim 9, wherein a 1-bit response signal is obtained every time the stimulus signal is input; respectively inputting N times of excitation signals to obtain N response signals to form N-bit response signals; wherein N is a positive integer.
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