CN113095496B - Circuit and method for improving calculation precision of storage and calculation integrated array - Google Patents
Circuit and method for improving calculation precision of storage and calculation integrated array Download PDFInfo
- Publication number
- CN113095496B CN113095496B CN202110445555.7A CN202110445555A CN113095496B CN 113095496 B CN113095496 B CN 113095496B CN 202110445555 A CN202110445555 A CN 202110445555A CN 113095496 B CN113095496 B CN 113095496B
- Authority
- CN
- China
- Prior art keywords
- storage
- resistance
- array
- calculation
- additional circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/08—Learning methods
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- Biophysics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Computational Linguistics (AREA)
- Data Mining & Analysis (AREA)
- Artificial Intelligence (AREA)
- General Health & Medical Sciences (AREA)
- Molecular Biology (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Neurology (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a circuit and a method for improving calculation accuracy of a storage-calculation integrated array. The method can be used in the calculation of the neural state and can also be used for precision recovery in other multi-value storage by using a large-scale array. The normalized simulation precision of the calculation method of the kirchhoff equation set of the whole array on the interconnection resistance effect and the potential problem reaches more than 99 percent.
Description
Technical Field
The invention relates to the field of memories, in particular to a circuit and a method for improving calculation precision of a storage and calculation integrated array.
Background
Memories currently used in artificial intelligence computing include resistive random access memories, phase change memories, ferroelectric tunneling junctions, and the like. These memories implement the function of multivalued storage in different ways and can reproducibly implement the variation of resistance by adding a certain amount of voltage or current.
With the expansion of memory arrays and the improvement of requirements on calculation accuracy, the influence of the interconnection resistance effect and the sneak path problem in the arrays on the calculation is larger and larger, and the traditional method needs a large amount of calculation for incorporating the interconnection resistance effect and the sneak path problem into a training process by using a solution kirchhoff equation system for the whole array. Therefore, it is necessary to quickly obtain the calculation results of the interconnect resistance effect and the sneak circuit problem.
FIG. 1 shows a schematic diagram of Multiple Accumulation Computations (MAC) using a memory array under ideal conditions. The output current I is the sum of the currents flowing through all the memories of this column and has no relation to the memory storage states of the other columns. When the input voltage or the storage state of some memories is changed, the output current is correspondingly changed. This allows the output current to be correlated to the memory state and input voltage of each memory in the column.
Fig. 2 shows the correspondence of the structure of a Deep Neural Network (DNN) to a memory array. The structure of the deep learning network is composed of an input layer, a hidden layer and an output layer, wherein the number of the hidden layer(s) can be one or more, the layers are fully connected, namely, a certain neuron of the ith layer is connected with each neuron of the (i + 1) th layer, each neuron transmits information through a determined corresponding relation, and the corresponding relation is adjusted through a back propagation algorithm (BP), so that the learning purpose is achieved. Each column in the memory array represents a neuron, and the stored information of the column of the memory is read by inputting a smaller voltage V, namely the correspondence of the neuron and each neuron in the previous layer. The output current I is the sum of the output currents of an entire column of memories and is connected with the next layer of array, and the full connection of each neuron in the upper layer and the neuron in the next layer is formed. In the back propagation process, the stored information of the memory is changed through the fed-back current, and the corresponding relation of each neuron is adjusted to achieve the purpose of learning.
FIG. 3 is a schematic diagram of the memory array in an actual state, where RwlAnd RblV is the input voltage and I is the output current for the line resistance of the array. In the resistive crossbar array, each output current is not the sum of the currents output by the column of memory alone, and the sum of the currents output by the column of memory is subjected to a plurality of line resistances RwlAnd RblTotal current (e.g. R) in series with a memory, and in parallel with other potential loops1nBoth ends also contain R1i、R2i、R2nThree potential loops formed in series), when the memory array is large, the obtained value has a large deviation from the ideal value, and if the deviation is ignored in the calculation process, a large error is caused, and the learning precision of the whole model is reduced.
At present, the main solution to the interconnect resistance effect and sneak path problem is to incorporate it into the training process, and use kirchhoff equations to solve for the whole array, but in a larger array, the calculation for each memory cell requires thousands or even more equations to solve, which requires a lot of time to calculate these values. In deep learning networks, this lengthy computation cannot be tolerated.
Disclosure of Invention
Aiming at the defects of the interconnection resistance effect and the sneak path problem in the existing storage and calculation integrated array in the aspect of calculation rate, the invention provides a circuit and a method for improving the calculation precision of the storage and calculation integrated array.
In order to solve the technical problem, the technical scheme adopted by the invention is as follows: a circuit for improving the calculation accuracy of a storage and calculation integrated array comprises a first additional circuit and a second additional circuit, wherein the first additional circuit is connected to an input word line of the storage and calculation integrated array, has the same size as the number of lines of the storage and calculation integrated array, and comprises m first compensation elements which are connected in series at the input position of each line of the storage and calculation integrated array, and m is the number of lines of the storage and calculation integrated array; the second additional circuit is connected to the output bit lines of the calculation integrated array, has the same size as the number of columns of the calculation integrated array, and comprises n second compensation elements which are connected in series at the output of each column of the calculation integrated array, wherein n is the number of columns of the calculation integrated frame; the first additional circuit and the second additional circuit are connected with the storage and calculation integrated array in series, so that the resistance value of the storage and calculation integrated array is corrected; the first compensation element and the second compensation element are resistive elements.
Further, the first compensation element and the second compensation element are resistors, triodes or MOS tubes.
Further, the first compensation element has a resistance value of
RbiThe resistance of the first compensation element for the ith row, m is the number of rows in the storage body array, i is [1, m ]]，RblIs the line resistance on the bit line, RiIs the resistance of the memory cell corresponding to the word line in the ith row.
Further, the second compensation element has a resistance value of
RwjThe resistance of the second compensation element in the jth column, n is the number of rows in the integral array, j is equal to [1, n ]]，RwlIs the line resistance on the word line, RjIs the resistance of the memory cell corresponding to the j-th word line.
Further, the first additional circuit and the second additional circuit are reconfigured according to the line resistance and the array size of the integrated array.
Further, the same first additional circuit and the same second additional circuit are used for the integrated array with the same size and the same manufacturing process.
The invention also discloses a method for improving the calculation speed of the storage and calculation integrated array, which comprises the following steps: s01), inputting the resistance of the integrated array line resistor, including R on the bit lineblAnd line resistance R on the word linewl；
S02), inputting the number of rows and columns of the storage and calculation integrated array;
s03), obtaining hardware parameters of a correction framework, wherein the correction framework comprises a first additional circuit and a second additional circuit, the first additional circuit is connected to the input word line of the storage and calculation integrated array, the size of the first additional circuit is the same as the number of rows of the storage and calculation integrated array, the first additional circuit comprises m first compensation elements which are connected in series at the input of each row of the storage and calculation integrated array, and m is the number of rows of the storage and calculation integrated array; the second additional circuit is connected to the output bit lines of the calculation integrated array, has the same size as the number of columns of the calculation integrated array, and comprises n second compensation elements which are connected in series at the output of each column of the calculation integrated array, wherein n is the number of columns of the calculation integrated frame; the first additional circuit and the second additional circuit are connected with the storage and calculation integrated array in series, so that the resistance value of the storage and calculation integrated array is corrected;
s04), adjusting the correction framework circuit, adjusting the resistance value of the first compensation element and the resistance value of the second compensation element according to the row number and the line resistance of the storage and calculation integrated array:
the first compensating element has a resistance of
RbiFor the resistance of the first compensation element in row i, m is the number of rows of the storage bank, i e [1, m ]]，RblIs the line resistance on the bit line, RiIs the resistance value of the memory cell corresponding to the word line of the ith row;
the second compensating element has a resistance of
RwjThe resistance of the second compensation element in the jth column, n is the number of rows in the integral array, j is equal to [1, n ]]，RwlIs the line resistance on the word line, RjIs the resistance of the memory cell corresponding to the jth word line;
s05), judging whether the correction precision is achieved, if yes, carrying out array calculation, and if not, finely adjusting the first additional circuit and the second additional circuit by using software.
Furthermore, when the array is calculated, kirchhoff equation calculation is not carried out, the resistance value of the integrated array is added with the resistance value of the first additional circuit and the resistance value of the second additional circuit in series, and then the output current is obtained, so that the resistance value is normalized and corrected.
Further, the process of utilizing software to fine tune the first additional circuit and the second additional circuit is as follows: and equivalently adding the difference resistance value by adjusting the input according to the calculated difference between the resistance value and the hardware resistance value.
Further, the resistance value added through software does not exceed the resistance value change step length of the first additional circuit and the second additional circuit.
The invention has the beneficial effects that: the invention uses the series connection of the circuits to replace a large amount of equation solving processes, thereby improving the speed in the calculation of the nervous state. The method can be used in the calculation of the neural state and can also be used for precision recovery in other multi-value storage by using a large-scale array. The normalized simulation precision (taking 256 rows of array scale) of the kirchhoff equation set calculation method of the whole array on the interconnection resistance effect and the potential path problem reaches over 99 percent.
Drawings
FIG. 1 is a schematic diagram of an ideal case of multiple accumulation calculations using a memory array;
FIG. 2 is a diagram of the structure of a DNN deep neural network corresponding to a memory array;
FIG. 3 is a schematic diagram of the memory array in an actual state;
FIG. 4 is a circuit diagram of a memory array with resistance compensation by adding different types of devices; fig. 4a is a circuit diagram of resistance compensation through an additional resistor, fig. 4b is a circuit diagram of resistance compensation through an additional transistor, and fig. 4c is a circuit diagram of resistance compensation through an additional MOS transistor;
FIG. 5 is a multiplexing schematic of additional circuitry in the presence of multiple arrays of the same size;
FIG. 6 is a flowchart of example 2;
FIG. 7 is a diagram showing the specific parameters of the additional circuit resistance required for each column for different array sizes when the line resistance is 1 Ω;
FIG. 8 is a diagram illustrating specific parameters of additional circuit resistance required for each row for different array sizes when the line resistance is 1 Ω;
FIG. 9 is a graph comparing the method of applying additional resistors to the calculation of normalized resistance values of resistors in an array using the solution kirchhoff equation.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments.
Example 1
In a banked array, each column is subjected to RblThe influence and sneak problems are the same, R1nBoth ends also contain R1i、R2i、R2nPotential loop formed by three parts in series and output InPassing m RblSame as R1iBoth ends also contain R1n、R2n、R2iThree potential circuits formed by series connection and the same number of R when the Ii is outputblThis means that we only need to calculate the effect of the interconnect resistance effect and the sneak path problem in a certain column to approximately calculate the effect of each column.Similarly, the influence of the interconnection resistance effect and the potential problem on each row is the same, so that two reconfigurable circuits can be built through calculation in advance to quickly correct the influence of the interconnection resistance effect and the potential problem.
Based on this, the present embodiment discloses a circuit for improving the calculation accuracy of a banked array, as shown in fig. 4, the circuit adds a resistance value device on the basis of the original banked array, and specifically includes a first additional circuit connected to an input word line of the banked array and a second additional circuit connected to an output bit line of the banked array.
The first additional circuit is the same size as the number of rows of the bank array and includes m first compensation elements connected in series at the input of each row of the bank array, m being the number of rows of the bank array. The size of the second additional circuit is the same as the number of columns of the storage and calculation integrated array, the second additional circuit comprises n second compensation elements which are connected in series at the output of each column of the storage and calculation integrated array, and n is the number of columns of the storage and calculation integrated frame; the first additional circuit and the second additional circuit are connected with the storage and calculation integrated array in series, so that resistance value correction of the storage and calculation integrated array is achieved.
The first compensation element and the second compensation element can be resistors, triodes or MOS transistors, thereby forming three types of additional circuits, as shown in fig. 4a, 4b and 4c respectively.
In this embodiment, the first compensation element has a resistance value of
RbiThe resistance of the first compensation element for the ith row, m is the number of rows in the storage body array, i is [1, m ]]，RblIs the line resistance on the bit line, RiIs the resistance of the memory cell corresponding to the word line in the ith row.
The second compensating element has a resistance of
RwjThe resistance of the second compensation element in the jth column, n is the number of rows in the integral array, j is equal to [1, n ]]，RwlChinese character' yuLine resistance on the line, RjIs the resistance of the memory cell corresponding to the j-th word line.
The first compensation element and the second compensation element are respectively formed into two parts of the circuit A, B, so that a novel transverse resistor rod type array is formed, and the structure can effectively restore the resistance value precision of a memory in the transverse resistor rod type array.
First additional circuit for correcting RblAnd the influence of resistance change caused by part of potential loops, and a second additional circuit for correcting RwlAnd resistance change influence brought by the other part of potential loop, and the two parts of circuits can not be used independently. There is an optimum but not a unique value for the same array because the normalized resistance value is adjusted rather than a specific value, which means that a certain resistance value is added to the peripheral circuit at the same time, as long as the relative value of normalization is guaranteed to be constant.
The first additional circuit and the second additional circuit are reconfigured according to the line resistance and the array size of the memory integrated array. The method determines the line resistance and the array size of the memory array as unknown quantities, and different circuits can be reconstructed under the conditions of different array sizes and line resistances.
As shown in fig. 5, the same first additional circuit and the same second additional circuit are used for the same size and the same fabrication process of the integrated array. However, when the sizes of the memory arrays are different, the memory arrays cannot be directly used, and the specific state of the additional circuit needs to be changed for reconstruction calculation.
The first additional circuit and the second additional circuit are matched and cannot be used in a mixed mode. Otherwise, the compensation of the correction potential circuit is not complete, and the accuracy of the correction effect is reduced.
Example 2
The embodiment discloses a method for improving the calculation speed of a storage and calculation integrated array, which comprises the following steps as shown in FIG. 6:
s01), inputting the resistance of the integrated array line resistor including the line resistor R on the bit lineblAnd line resistance R on the word linewl；
S02), inputting the number of rows and columns of the storage and calculation integrated array;
s03), obtaining hardware parameters of a correction framework, wherein the correction framework comprises a first additional circuit and a second additional circuit, the first additional circuit is connected to the input word line of the storage and calculation integrated array, the size of the first additional circuit is the same as the number of rows of the storage and calculation integrated array, the first additional circuit comprises m first compensation elements which are connected in series at the input of each row of the storage and calculation integrated array, and m is the number of rows of the storage and calculation integrated array; the second additional circuit is connected to the output bit line of the storage and calculation integrated array, has the same size as the number of columns of the storage and calculation integrated array, and comprises n second compensation elements which are connected in series at the output of each column of the storage and calculation integrated array, wherein n is the number of columns of the storage and calculation integrated frame; the first additional circuit and the second additional circuit are connected with the storage and calculation integrated array in series, so that the resistance value of the storage and calculation integrated array is corrected;
s04), adjusting the correction framework circuit, adjusting the resistance of the first compensation element and the resistance of the second compensation element according to the number of rows and columns of the storage integrated array and the line resistance:
the first compensating element has a resistance of
RbiThe resistance of the first compensation element for the ith row, m is the number of rows in the storage body array, i is [1, m ]]，RblIs the line resistance on the bit line, RiIs the resistance of the memory cell corresponding to the word line in the ith row;
the second compensating element has a resistance of
RwjThe resistance of the second compensation element in the jth column, n is the number of rows in the integral array, j is equal to [1, n ]]，RwlIs the line resistance on the word line, RjIs the resistance of the memory cell corresponding to the jth word line;
s05), judging whether the correction precision is achieved, if yes, carrying out array calculation, and if not, finely adjusting the first additional circuit and the second additional circuit by using software.
When the array is calculated, kirchhoff equation calculation is not carried out, the resistance value of the storage and calculation integrated array is serially added with the resistance value of the first additional circuit and the resistance value of the second additional circuit, and then the output current is obtained, so that the resistance value is normalized and corrected.
The process of utilizing software to fine tune the first additional circuit and the second additional circuit is as follows: and equivalently adding the difference resistance value by adjusting the input according to the calculated difference between the resistance value and the hardware resistance value.
Specifically, the resistance value added through software does not exceed the resistance value change step length of the first additional circuit and the second additional circuit, and the method is only used as a solution for further improving the resistance value correction precision progress.
Fig. 7 and 8 show the specific parameters of the additional circuitry required for different array sizes with a line resistance of 1 Ω. Where the x-axis of fig. 7 represents the number of columns in the array, the y-axis is a specific one of such columns, and the z-axis is the value of the specific parameter of the circuit (e.g., when the array size is 200 columns, the specific parameter size of the 100 th column of the additional circuit is 200, and y is 100, the corresponding z value). The y-axis in fig. 8 represents the number of rows in the array, the x-axis is a particular one of such columns, and the z-axis is the value of a particular parameter of the circuit. The specific method is to determine the corresponding number of rows and columns, and two groups of circuits with the number and size of elements corresponding to the number of rows and columns can be obtained.
FIG. 9 shows a comparison of a method using additional circuitry and the use of the solution kirchhoff equation to calculate the normalized resistance of resistors in an array. By solving kirchhoff equation set, about 5% of errors can be caused by interconnection resistance effect and potential problem in an array with 256 column numbers, the errors can be well fitted by using an additional circuit method, and the fitting precision reaches more than 99%.
The invention uses the series connection of the circuits to replace a large amount of equation solving processes, thereby improving the speed in the calculation of the nervous state. The method can be used in the calculation of the neural state and can also be used for precision recovery in other multi-value storage by using a large-scale array. The normalized simulation precision (taking 256 rows of array scale) of the kirchhoff equation set calculation method of the whole array on the interconnection resistance effect and the potential path problem reaches over 99 percent.
The foregoing description is only for the basic principle and the preferred embodiments of the present invention, and modifications and substitutions by those skilled in the art are included in the scope of the present invention.
Claims (7)
1. A circuit for improving calculation accuracy of a storage and calculation integrated array is characterized in that: the first additional circuit is connected to the input word line of the storage and calculation integrated array, has the same size as the number of rows of the storage and calculation integrated array, and comprises m first compensation elements connected in series at the input of each row of the storage and calculation integrated array, and m is the number of rows of the storage and calculation integrated array; the second additional circuit is connected to the output bit lines of the storage and calculation integrated array, has the same size as the number of columns of the storage and calculation integrated array, and comprises n second compensation elements which are connected in series at the output of each column of the storage and calculation integrated array, wherein n is the number of columns of the storage and calculation integrated array; the first additional circuit and the second additional circuit are connected with the storage and calculation integrated array in series, so that the resistance value of the storage and calculation integrated array is corrected; the first compensation element and the second compensation element are resistive elements; the first compensating element has a resistance of
RbiThe resistance of the first compensation element for the ith row, m is the number of rows in the storage body array, i is [1, m ]]，RblIs the line resistance on the bit line, RiIs the resistance of the memory cell corresponding to the word line in the ith row; the second compensating element has a resistance of
RwjThe resistance of the second compensation element in the jth column, n is the number of columns of the integrated array, j is equal to [1, n ]]，RwlIs the line resistance on the word line, RjIs the resistance of the memory cell corresponding to the jth column word line.
2. The circuit for improving computational accuracy of a storage-integrated array of claim 1, wherein: the first compensation element and the second compensation element are resistors, triodes or MOS tubes.
3. The circuit for improving computational accuracy of a storage-integrated array of claim 1, wherein: the first additional circuit and the second additional circuit are reconfigured according to the line resistance and the array size of the memory integrated array.
4. The circuit for improving computational accuracy of a storage-integrated array of claim 1, wherein: the same first additional circuit and the same second additional circuit are used for the integrated storage arrays with the same size and the same manufacturing process.
5. A method for improving the calculation accuracy of a storage and calculation integrated array is characterized in that: the method comprises the following steps:
s01), inputting the resistance of the integrated array line resistor including the line resistor R on the bit lineblAnd line resistance R on the word linewl；
S02), inputting the number of rows and columns of the storage and calculation integrated array;
s03), obtaining hardware parameters of a correction framework, wherein the correction framework comprises a first additional circuit and a second additional circuit, the first additional circuit is connected to the input word line of the storage and calculation integrated array, the size of the first additional circuit is the same as the number of lines of the storage and calculation integrated array, the first additional circuit comprises m first compensation elements which are connected in series at the input position of each line of the storage and calculation integrated array, and m is the number of lines of the storage and calculation integrated array; the second additional circuit is connected to the output bit lines of the calculation integrated array, has the same size as the number of columns of the calculation integrated array, and comprises n second compensation elements which are connected in series at the output of each column of the calculation integrated array, wherein n is the number of columns of the calculation integrated frame; the first additional circuit and the second additional circuit are connected with the storage and calculation integrated array in series, so that the resistance value of the storage and calculation integrated array is corrected;
s04), adjusting the correction framework circuit, adjusting the resistance value of the first compensation element and the resistance value of the second compensation element according to the row number and the line resistance of the storage and calculation integrated array:
the first compensating element has a resistance of
RbiThe resistance of the first compensation element for the ith row, m is the number of rows in the storage body array, i is [1, m ]]，RblIs the line resistance on the bit line, RiIs the resistance of the memory cell corresponding to the word line in the ith row;
the second compensating element has a resistance of
RwjThe resistance of the second compensation element in the jth column, n is the number of rows in the integral array, j is equal to [1, n ]]，RwlIs the line resistance on the word line, RjIs the resistance of the memory cell corresponding to the jth column word line;
s05), judging whether the correction precision is achieved, if yes, carrying out array calculation, and if not, finely adjusting the first additional circuit and the second additional circuit by using software; when the array is calculated, the resistance value of the storage and calculation integrated array is serially added with the resistance value of the first additional circuit and the resistance value of the second additional circuit, and then the output current is obtained.
6. The method of improving computational accuracy of a storage-integrated array of claim 5, wherein: the process of utilizing software to fine tune the first additional circuit and the second additional circuit is as follows: and equivalently adding the difference resistance value by adjusting the input according to the calculated difference between the resistance value and the hardware resistance value.
7. The method of improving computational accuracy of a storage-integrated array of claim 5, wherein: the resistance value added by software does not exceed the step size of the resistance value change of the first additional circuit and the second additional circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110445555.7A CN113095496B (en) | 2021-04-25 | 2021-04-25 | Circuit and method for improving calculation precision of storage and calculation integrated array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110445555.7A CN113095496B (en) | 2021-04-25 | 2021-04-25 | Circuit and method for improving calculation precision of storage and calculation integrated array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113095496A CN113095496A (en) | 2021-07-09 |
| CN113095496B true CN113095496B (en) | 2022-07-15 |
Family
ID=76679862
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110445555.7A Active CN113095496B (en) | 2021-04-25 | 2021-04-25 | Circuit and method for improving calculation precision of storage and calculation integrated array |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113095496B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007135850A1 (en) * | 2006-05-24 | 2007-11-29 | The Ritsumeikan Trust | Infrared array sensor |
| CN211269960U (en) * | 2019-12-06 | 2020-08-18 | 珠海格力电器股份有限公司 | Cooking appliance with heating in different zones |
| CN112101539A (en) * | 2020-11-18 | 2020-12-18 | 南京优存科技有限公司 | Deposit and calculate integrative circuit and artificial intelligence chip |
| CN112382319A (en) * | 2020-10-10 | 2021-02-19 | 中国科学院微电子研究所 | Self-reference storage structure and storage and calculation integrated circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB0118678D0 (en) * | 2001-08-01 | 2001-09-19 | Qinetiq Ltd | Random access decoder |
| CN112558917B (en) * | 2019-09-10 | 2021-07-27 | 珠海博雅科技有限公司 | Integrated storage and calculation circuit and data calculation method based on integrated storage and calculation circuit |
| CN112036562B (en) * | 2020-11-05 | 2021-02-26 | 中科院微电子研究所南京智能技术研究院 | Bit cell applied to memory computation and memory computation array device |
-
2021
- 2021-04-25 CN CN202110445555.7A patent/CN113095496B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007135850A1 (en) * | 2006-05-24 | 2007-11-29 | The Ritsumeikan Trust | Infrared array sensor |
| CN211269960U (en) * | 2019-12-06 | 2020-08-18 | 珠海格力电器股份有限公司 | Cooking appliance with heating in different zones |
| CN112382319A (en) * | 2020-10-10 | 2021-02-19 | 中国科学院微电子研究所 | Self-reference storage structure and storage and calculation integrated circuit |
| CN112101539A (en) * | 2020-11-18 | 2020-12-18 | 南京优存科技有限公司 | Deposit and calculate integrative circuit and artificial intelligence chip |
Non-Patent Citations (2)
| Title |
|---|
| Crosspoint Memory Arrays: Principle, Strengths and Challenges;G. Molas，et al;《2020 IEEE International Memory Workshop (IMW)》;20200604;全文 * |
| 存算一体化的发展现状挑战与对策建议;李雅琪 等;《互联网经济》;20200425;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113095496A (en) | 2021-07-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Jaiswal et al. | 8T SRAM cell as a multibit dot-product engine for beyond von Neumann computing | |
| US10643705B2 (en) | Configurable precision neural network with differential binary non-volatile memory cell structure | |
| US9934463B2 (en) | Neuromorphic computational system(s) using resistive synaptic devices | |
| CN111433792B (en) | Counter-based resistance processing unit of programmable resettable artificial neural network | |
| Kim et al. | Input voltage mapping optimized for resistive memory-based deep neural network hardware | |
| Mohanty et al. | Random sparse adaptation for accurate inference with inaccurate multi-level RRAM arrays | |
| Liu et al. | Fault tolerance in neuromorphic computing systems | |
| US11138497B2 (en) | In-memory computing devices for neural networks | |
| US10468098B2 (en) | In-cell differential read-out circuitry for reading signed weight values in resistive processing unit architecture | |
| Agrawal et al. | X-CHANGR: Changing memristive crossbar mapping for mitigating line-resistance induced accuracy degradation in deep neural networks | |
| US20200234762A1 (en) | Differential memristive circuit | |
| Lepri et al. | Modeling and compensation of IR drop in crosspoint accelerators of neural networks | |
| Ali et al. | RAMANN: in-SRAM differentiable memory computations for memory-augmented neural networks | |
| Lee et al. | Novel method enabling forward and backward propagations in NAND flash memory for on-chip learning | |
| CN113095496B (en) | Circuit and method for improving calculation precision of storage and calculation integrated array | |
| Kim et al. | VCAM: Variation compensation through activation matching for analog binarized neural networks | |
| US20230297235A1 (en) | Sram-based cell for in-memory computing and hybrid computations/storage memory architecture | |
| Gi et al. | Fundamental issues of implementing hardware neural networks using memristor | |
| Serrano-Gotarrdeona et al. | An ART1 microchip and its use in multi-ART1 systems | |
| Doevenspeck et al. | Noise tolerant ternary weight deep neural networks for analog in-memory inference | |
| DE102021117736A1 (en) | IN-ROW TRACKING OF REFERENCE GENERATION FOR STORAGE DEVICES | |
| Sun et al. | Reliability-Aware Training and Performance Modeling for Processing-In-Memory Systems | |
| US11955168B2 (en) | Memory device and computing method using the same | |
| Qiu et al. | Mnsim-time: Performance modeling framework for training-in-memory architectures | |
| CN111191776A (en) | Storage calculation array, storage calculation module and data calculation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |