CN113094324A - Guidance information inter-core interaction method and system based on shared memory - Google Patents
Guidance information inter-core interaction method and system based on shared memory Download PDFInfo
- Publication number
- CN113094324A CN113094324A CN202110342595.9A CN202110342595A CN113094324A CN 113094324 A CN113094324 A CN 113094324A CN 202110342595 A CN202110342595 A CN 202110342595A CN 113094324 A CN113094324 A CN 113094324A
- Authority
- CN
- China
- Prior art keywords
- core
- shared memory
- slave
- guidance information
- main
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 41
- 230000003993 interaction Effects 0.000 title claims abstract description 26
- 230000008569 process Effects 0.000 claims abstract description 20
- 238000012545 processing Methods 0.000 claims abstract description 16
- 238000004891 communication Methods 0.000 claims abstract description 15
- 238000001914 filtration Methods 0.000 claims abstract description 14
- 238000012546 transfer Methods 0.000 claims abstract description 12
- 238000000605 extraction Methods 0.000 claims abstract description 7
- 230000007958 sleep Effects 0.000 claims description 10
- 238000004364 calculation method Methods 0.000 claims description 8
- 238000001514 detection method Methods 0.000 claims description 3
- 230000008901 benefit Effects 0.000 description 4
- 239000000523 sample Substances 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000005059 dormancy Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000013507 mapping Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/177—Initialisation or configuration control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/544—Buffers; Shared memory; Pipes
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Train Traffic Observation, Control, And Security (AREA)
Abstract
The invention provides a guidance information inter-core interaction method and a guidance information inter-core interaction system based on a shared memory, which comprise the following steps: step 1: carrying out system configuration of a multi-core embedded processing platform, and setting a master core and a slave core and a shared memory area; step 2: starting a main core process and starting to receive external interface information; and step 3: finishing the first inter-core communication of the original guidance information through a shared memory: the original information transfer process from the master core to the slave core; and 4, step 4: finishing guidance information extraction in the secondary core through an extended Kalman filtering algorithm; and 5: and finishing the second inter-core communication of the original guidance information through a shared memory: the original information transfer process from the secondary core to the primary core; step 6: generating a guidance control instruction in the period according to the guidance information in the main core; and 7: and repeating the step 2 to the step 6 until the scheduling of the main core flow is finished. According to the invention, through the configuration of the software shared memory area, the inter-core communication of guidance information between the master core and the slave core is realized.
Description
Technical Field
The invention relates to the field of embedded software design, in particular to a guidance information inter-core interaction method and system based on a shared memory. In particular to an inter-core communication method for processing guidance information interaction on a missile-borne multi-core embedded platform.
Background
Guidance information such as the visual line angular rate, the relative speed, the distance and the like of the strapdown seeker is extracted and can be obtained through an extended Kalman filtering method, and the method relates to large-scale matrix calculation, in particular to the inversion operation of a high-order matrix.
For a missile-borne system adopting a multi-core embedded platform such as a DSP or an ARM, the dominant frequency of the missile-borne system is generally lower than that of a home PC, and the computing capability is limited. Besides guidance information extraction, the missile-borne system also needs to process related tasks such as external interface management, time sequence flow control, clock timing, sensor information filtering, navigation guidance and control, information transmission and storage and the like. If such many information operations are arranged on a single core and can only be processed serially, it is difficult to take advantage of the multi-core platform, and it is difficult to ensure the real-time performance of the operations due to the low dominant frequency of the embedded processor, and it also brings many problems to the memory management of the embedded system.
By adopting the missile-borne platform with the multi-core processor, the maximum advantage of parallel processing can be exerted by starting the slave cores, and numerical calculation is stripped from the master core, so that the master core is focused on processing external interface management and flow control.
Patent document CN108959149A (application number: CN201810683337.5) discloses a shared memory based multi-core processor interaction bus design method, which is suitable for a multi-core processor system with large capacity data real-time interaction. And in the initialization stage, analyzing the data interaction configuration of the multi-core processor, and acquiring the configuration information of the output and input data of each core processor. And initializing the shared memory according to the output configuration information, and sequentially distributing the memory segments of the output data area of each core processor. And establishing a linked list of input data of each core processor, and storing a mapping memory address corresponding to the input data. And adopting ping-pong type cycle read-write cache in the real-time interrupt task, reading the interactive data of the last interrupt task, updating the output data of the current interrupt task and writing the output data into the shared memory.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a guidance information inter-core interaction method and system based on a shared memory.
The guidance information inter-core interaction method based on the shared memory provided by the invention comprises the following steps:
step 1: carrying out system configuration of a multi-core embedded processing platform, and setting a master core and a slave core and a shared memory area;
step 2: starting a main core process and starting to receive external interface information;
and step 3: finishing the first inter-core communication of the original guidance information through a shared memory: the original information transfer process from the master core to the slave core;
and 4, step 4: finishing guidance information extraction in the secondary core through an extended Kalman filtering algorithm;
and 5: and finishing the second inter-core communication of the original guidance information through a shared memory: the original information transfer process from the secondary core to the primary core;
step 6: generating a guidance control instruction in the period according to the guidance information in the main core;
and 7: and repeating the step 2 to the step 6 until the scheduling of the main core flow is finished.
Preferably, the step 1 comprises:
step 1.1: configuring a multi-core embedded processing platform, enabling a core0 and a core1 to be in an activatable state, configuring the core0 as a master core and configuring the core1 as a slave core;
step 1.2: configuring the size of a shared memory area in the memory of the embedded platform, and authorizing a read lock and a write lock of the shared memory of the master core0 and the slave core 1;
step 1.3: the main core0 starts operation, the slave core1 is set to a sleep state, and the operation is started after the main core0 wakes up the slave core 1.
Preferably, the primary core0 receives the original probe information from the external interface according to a preset cycle: line of sight, and wake-up slave core 1;
and generating guidance information comprising the angular velocity, the relative speed and the relative distance of the line of sight in the period by using extended Kalman filtering according to the original line of sight information in the shared memory in the secondary core 1.
Preferably, the step 3 comprises:
step 3.1: opening a shared memory write lock of the main core0, placing original line-of-sight angle information received by the main core0 from an external interface into a shared memory, and closing the shared memory write lock of the main core 0;
step 3.2: the shared memory read lock of the slave core1 is opened, the view angle information in the shared memory is read into the memory area managed by the slave core1, and the shared memory read lock of the slave core1 is closed.
Preferably, the step 5 comprises:
step 5.1: opening a write lock of the shared memory of the slave core1, placing guidance information obtained by calculation of the slave core1 into the shared memory, and closing the write lock of the shared memory of the slave core 1;
step 5.2: go to sleep from core 1;
step 5.3: and opening a read lock of the shared memory of the main core0, and reading guidance information including the line-of-sight angular velocity, the relative speed and the relative distance information in the shared memory into the main core.
The guidance information inter-core interaction system based on the shared memory comprises the following modules:
module M1: carrying out system configuration of a multi-core embedded processing platform, and setting a master core and a slave core and a shared memory area;
module M2: starting a main core process and starting to receive external interface information;
module M3: finishing the first inter-core communication of the original guidance information through a shared memory: the original information transfer process from the master core to the slave core;
module M4: finishing guidance information extraction in the secondary core through an extended Kalman filtering algorithm;
module M5: and finishing the second inter-core communication of the original guidance information through a shared memory: the original information transfer process from the secondary core to the primary core;
module M6: generating a guidance control instruction in the period according to the guidance information in the main core;
module M7: and repeatedly calling the module M2 to the module M6 until the master core flow scheduling is finished.
Preferably, the module M1 includes:
module M1.1: configuring a multi-core embedded processing platform, enabling a core0 and a core1 to be in an activatable state, configuring the core0 as a master core and configuring the core1 as a slave core;
module M1.2: configuring the size of a shared memory area in the memory of the embedded platform, and authorizing a read lock and a write lock of the shared memory of the master core0 and the slave core 1;
module M1.3: the main core0 starts operation, the slave core1 is set to a sleep state, and the operation is started after the main core0 wakes up the slave core 1.
Preferably, the primary core0 receives the original probe information from the external interface according to a preset cycle: line of sight, and wake-up slave core 1;
and generating guidance information comprising the angular velocity, the relative speed and the relative distance of the line of sight in the period by using extended Kalman filtering according to the original line of sight information in the shared memory in the secondary core 1.
Preferably, the module M3 includes:
module M3.1: opening a shared memory write lock of the main core0, placing original line-of-sight angle information received by the main core0 from an external interface into a shared memory, and closing the shared memory write lock of the main core 0;
module M3.2: the shared memory read lock of the slave core1 is opened, the view angle information in the shared memory is read into the memory area managed by the slave core1, and the shared memory read lock of the slave core1 is closed.
Preferably, the module M5 includes:
module M5.1: opening a write lock of the shared memory of the slave core1, placing guidance information obtained by calculation of the slave core1 into the shared memory, and closing the write lock of the shared memory of the slave core 1;
module M5.2: go to sleep from core 1;
module M5.3: and opening a read lock of the shared memory of the main core0, and reading guidance information including the line-of-sight angular velocity, the relative speed and the relative distance information in the shared memory into the main core.
Compared with the prior art, the invention has the following beneficial effects:
(1) the invention effectively exerts the advantage of multi-core parallel processing of the embedded platform through the mutual matching and interaction of the master core and the slave core;
(2) according to the method, the inter-core communication of the guidance information between the master core and the slave core is realized through the configuration of the shared memory area of the software;
(3) the invention ensures the lossless transmission of guidance information in the interaction process through the read-write lock.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a flow chart of the method of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
Example (b):
as shown in fig. 1, the present invention provides a guidance information inter-core interaction method based on a shared memory, which includes the steps of:
step one, configuring a multi-core embedded processing platform, enabling a core0 and a core1 to be in an activatable state, configuring a core0 as a master core, and configuring a core1 as a slave core;
step two, configuring the size of a shared memory area in the memory of the embedded platform, and authorizing the read lock and the write lock of the shared memory of the master core0 and the slave core 1;
thirdly, the main core0 starts to operate, the auxiliary core1 is set to be in a dormant state, and the operation is started after the main core0 wakes up the auxiliary core 1;
step four, the main core0 starts to receive original detection information, namely a line-of-sight angle, from an external interface according to a timing cycle, and wakes up the auxiliary core 1;
step five, opening a write lock of the shared memory of the main core0, placing the original line-of-sight angle information received by the main core0 from the external interface into the shared memory, and closing the write lock of the shared memory of the main core 0;
step six, opening a shared memory read lock of the slave core1, reading the view angle information in the shared memory into a memory area managed by the slave core1, and closing the shared memory read lock of the slave core 1;
seventhly, generating guidance information such as the line-of-sight angular speed, the relative distance and the like in the period by using extended Kalman filtering according to the original line-of-sight angular information in the shared memory in the secondary core 1;
step eight, opening a write lock of the shared memory of the slave core1, placing guidance information obtained by calculation of the slave core1, including the line-of-sight angular rate, the relative speed and the relative distance information, into the shared memory, and closing the write lock of the shared memory of the slave core 1;
step nine, the slave core1 enters dormancy;
step ten, opening a main core0 shared memory reading lock, and reading guidance information such as the line-of-sight angular rate, the relative speed, the relative distance information and the like in the shared memory into the main core;
eleven, generating a guidance control instruction in the period in the main core0 according to guidance information such as the line-of-sight angular rate, the relative speed and the relative distance information;
and step twelve, repeating the step four to the step eleven until the flow scheduling of the main core0 is finished.
The guidance information inter-core interaction system based on the shared memory comprises the following modules: module M1: carrying out system configuration of a multi-core embedded processing platform, and setting a master core and a slave core and a shared memory area; module M2: starting a main core process and starting to receive external interface information; module M3: finishing the first inter-core communication of the original guidance information through a shared memory: the original information transfer process from the master core to the slave core; module M4: finishing guidance information extraction in the secondary core through an extended Kalman filtering algorithm; module M5: and finishing the second inter-core communication of the original guidance information through a shared memory: the original information transfer process from the secondary core to the primary core; module M6: generating a guidance control instruction in the period according to the guidance information in the main core; module M7: and repeatedly calling the module M2 to the module M6 until the master core flow scheduling is finished.
The module M1 includes: module M1.1: configuring a multi-core embedded processing platform, enabling a core0 and a core1 to be in an activatable state, configuring the core0 as a master core and configuring the core1 as a slave core; module M1.2: configuring the size of a shared memory area in the memory of the embedded platform, and authorizing a read lock and a write lock of the shared memory of the master core0 and the slave core 1; module M1.3: the main core0 starts operation, the slave core1 is set to a sleep state, and the operation is started after the main core0 wakes up the slave core 1. The primary core0 receives original probe information from the external interface according to a preset cycle: line of sight, and wake-up slave core 1; and generating guidance information comprising the angular velocity, the relative speed and the relative distance of the line of sight in the period by using extended Kalman filtering according to the original line of sight information in the shared memory in the secondary core 1.
The module M3 includes: module M3.1: opening a shared memory write lock of the main core0, placing original line-of-sight angle information received by the main core0 from an external interface into a shared memory, and closing the shared memory write lock of the main core 0; module M3.2: the shared memory read lock of the slave core1 is opened, the view angle information in the shared memory is read into the memory area managed by the slave core1, and the shared memory read lock of the slave core1 is closed.
The module M5 includes: module M5.1: opening a write lock of the shared memory of the slave core1, placing guidance information obtained by calculation of the slave core1 into the shared memory, and closing the write lock of the shared memory of the slave core 1; module M5.2: go to sleep from core 1; module M5.3: and opening a read lock of the shared memory of the main core0, and reading guidance information including the line-of-sight angular velocity, the relative speed and the relative distance information in the shared memory into the main core.
Those skilled in the art will appreciate that, in addition to implementing the systems, apparatus, and various modules thereof provided by the present invention in purely computer readable program code, the same procedures can be implemented entirely by logically programming method steps such that the systems, apparatus, and various modules thereof are provided in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system, the device and the modules thereof provided by the present invention can be considered as a hardware component, and the modules included in the system, the device and the modules thereof for implementing various programs can also be considered as structures in the hardware component; modules for performing various functions may also be considered to be both software programs for performing the methods and structures within hardware components.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (10)
1. A guidance information inter-core interaction method based on a shared memory is characterized by comprising the following steps:
step 1: carrying out system configuration of a multi-core embedded processing platform, and setting a master core and a slave core and a shared memory area;
step 2: starting a main core process and starting to receive external interface information;
and step 3: finishing the first inter-core communication of the original guidance information through a shared memory: the original information transfer process from the master core to the slave core;
and 4, step 4: finishing guidance information extraction in the secondary core through an extended Kalman filtering algorithm;
and 5: and finishing the second inter-core communication of the original guidance information through a shared memory: the original information transfer process from the secondary core to the primary core;
step 6: generating a guidance control instruction in the period according to the guidance information in the main core;
and 7: and repeating the step 2 to the step 6 until the scheduling of the main core flow is finished.
2. The guidance information inter-core interaction method based on the shared memory according to claim 1, wherein the step 1 comprises:
step 1.1: configuring a multi-core embedded processing platform, enabling a core0 and a core1 to be in an activatable state, configuring the core0 as a master core and configuring the core1 as a slave core;
step 1.2: configuring the size of a shared memory area in the memory of the embedded platform, and authorizing a read lock and a write lock of the shared memory of the master core0 and the slave core 1;
step 1.3: the main core0 starts operation, the slave core1 is set to a sleep state, and the operation is started after the main core0 wakes up the slave core 1.
3. The guidance information inter-core interaction method based on the shared memory as claimed in claim 2, wherein the main core0 receives original detection information from an external interface according to a preset cycle: line of sight, and wake-up slave core 1;
and generating guidance information comprising the angular velocity, the relative speed and the relative distance of the line of sight in the period by using extended Kalman filtering according to the original line of sight information in the shared memory in the secondary core 1.
4. The guidance information inter-core interaction method based on the shared memory according to claim 3, wherein the step 3 comprises:
step 3.1: opening a shared memory write lock of the main core0, placing original line-of-sight angle information received by the main core0 from an external interface into a shared memory, and closing the shared memory write lock of the main core 0;
step 3.2: the shared memory read lock of the slave core1 is opened, the view angle information in the shared memory is read into the memory area managed by the slave core1, and the shared memory read lock of the slave core1 is closed.
5. The shared-memory-based guidance information inter-core interaction method according to claim 4, wherein the step 5 comprises:
step 5.1: opening a write lock of the shared memory of the slave core1, placing guidance information obtained by calculation of the slave core1 into the shared memory, and closing the write lock of the shared memory of the slave core 1;
step 5.2: go to sleep from core 1;
step 5.3: and opening a read lock of the shared memory of the main core0, and reading guidance information including the line-of-sight angular velocity, the relative speed and the relative distance information in the shared memory into the main core.
6. A guidance information inter-core interaction system based on a shared memory is characterized by comprising the following modules:
module M1: carrying out system configuration of a multi-core embedded processing platform, and setting a master core and a slave core and a shared memory area;
module M2: starting a main core process and starting to receive external interface information;
module M3: finishing the first inter-core communication of the original guidance information through a shared memory: the original information transfer process from the master core to the slave core;
module M4: finishing guidance information extraction in the secondary core through an extended Kalman filtering algorithm;
module M5: and finishing the second inter-core communication of the original guidance information through a shared memory: the original information transfer process from the secondary core to the primary core;
module M6: generating a guidance control instruction in the period according to the guidance information in the main core;
module M7: and repeatedly calling the module M2 to the module M6 until the master core flow scheduling is finished.
7. The shared-memory-based guidance information inter-core interaction system of claim 6, wherein the module M1 comprises:
module M1.1: configuring a multi-core embedded processing platform, enabling a core0 and a core1 to be in an activatable state, configuring the core0 as a master core and configuring the core1 as a slave core;
module M1.2: configuring the size of a shared memory area in the memory of the embedded platform, and authorizing a read lock and a write lock of the shared memory of the master core0 and the slave core 1;
module M1.3: the main core0 starts operation, the slave core1 is set to a sleep state, and the operation is started after the main core0 wakes up the slave core 1.
8. The guidance information inter-core interaction system based on the shared memory as claimed in claim 7, wherein the main core0 receives the original detection information from the external interface according to a preset cycle: line of sight, and wake-up slave core 1;
and generating guidance information comprising the angular velocity, the relative speed and the relative distance of the line of sight in the period by using extended Kalman filtering according to the original line of sight information in the shared memory in the secondary core 1.
9. The shared-memory-based guidance information inter-core interaction system of claim 8, wherein the module M3 comprises:
module M3.1: opening a shared memory write lock of the main core0, placing original line-of-sight angle information received by the main core0 from an external interface into a shared memory, and closing the shared memory write lock of the main core 0;
module M3.2: the shared memory read lock of the slave core1 is opened, the view angle information in the shared memory is read into the memory area managed by the slave core1, and the shared memory read lock of the slave core1 is closed.
10. The shared-memory-based guidance information inter-core interaction system of claim 9, wherein the module M5 comprises:
module M5.1: opening a write lock of the shared memory of the slave core1, placing guidance information obtained by calculation of the slave core1 into the shared memory, and closing the write lock of the shared memory of the slave core 1;
module M5.2: go to sleep from core 1;
module M5.3: and opening a read lock of the shared memory of the main core0, and reading guidance information including the line-of-sight angular velocity, the relative speed and the relative distance information in the shared memory into the main core.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110342595.9A CN113094324A (en) | 2021-03-30 | 2021-03-30 | Guidance information inter-core interaction method and system based on shared memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110342595.9A CN113094324A (en) | 2021-03-30 | 2021-03-30 | Guidance information inter-core interaction method and system based on shared memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113094324A true CN113094324A (en) | 2021-07-09 |
Family
ID=76671273
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110342595.9A Pending CN113094324A (en) | 2021-03-30 | 2021-03-30 | Guidance information inter-core interaction method and system based on shared memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113094324A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101025697A (en) * | 2007-04-05 | 2007-08-29 | 杭州华为三康技术有限公司 | Method, system and master core and slave core for realizing user configuration |
| CN110825687A (en) * | 2019-10-25 | 2020-02-21 | 天津津航技术物理研究所 | Dual-mode tracking method based on DSP (digital Signal processor) multi-core architecture |
| CN110941285A (en) * | 2019-11-29 | 2020-03-31 | 云南大学 | Unmanned aerial vehicle flight control system based on two IP cores |
-
2021
- 2021-03-30 CN CN202110342595.9A patent/CN113094324A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101025697A (en) * | 2007-04-05 | 2007-08-29 | 杭州华为三康技术有限公司 | Method, system and master core and slave core for realizing user configuration |
| CN110825687A (en) * | 2019-10-25 | 2020-02-21 | 天津津航技术物理研究所 | Dual-mode tracking method based on DSP (digital Signal processor) multi-core architecture |
| CN110941285A (en) * | 2019-11-29 | 2020-03-31 | 云南大学 | Unmanned aerial vehicle flight control system based on two IP cores |
Non-Patent Citations (3)
| Title |
|---|
| 徐松等: "TMS320C6678多核DSP导航制导软件框架设计", 《工业控制计算机》 * |
| 李剑阳等: "基于Microblaze多核***的设计及在FPGA上的实现", 《微电子学与计算机》 * |
| 田立等: "互相关跟踪算法的多核DSP快速实现", 《高技术通讯》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6212625B1 (en) | General purpose dynamically programmable state engine for executing finite state machines | |
| CN112381220B (en) | Neural network tensor processor | |
| US10657039B2 (en) | Control device for a motor vehicle | |
| JP7216781B2 (en) | Data storage method, data storage device, data reading method and data reading device | |
| CN103207797A (en) | Capsule type customized updating method based on universal extensible firmware interface firmware system | |
| CN103336672B (en) | Method for reading data, device and computing device | |
| CN107885517B (en) | Program loading circuit of embedded system processor | |
| CN112580792B (en) | Neural network multi-core tensor processor | |
| US11188498B2 (en) | Method and system for processing engineering objects in an industrial automation environment | |
| Li et al. | An improved algorithm for deep learning YOLO network based on Xilinx ZYNQ FPGA | |
| CN103838626A (en) | Data processing device and method for processing serial tasks | |
| CN105446920A (en) | Loongson-based FPGA embedded computer and configuration method thereof | |
| CN106648758A (en) | Multi-core processor BOOT starting system and method | |
| CN112347721A (en) | System for realizing data processing acceleration based on FPGA and acceleration method thereof | |
| CN104298645A (en) | Flexibly configured programmable system-on-chip chip and starting configuration method thereof | |
| US8397005B2 (en) | Masked register write method and apparatus | |
| CN101702119B (en) | Device oriented programming technology and method | |
| CN105830160A (en) | Apparatuses and methods for writing masked data to buffer | |
| CN112667593B (en) | Method and device for ETL (extract transform and load) process to execute hbase fast loading | |
| Kim et al. | The implementation of a power efficient bcnn-based object detection acceleration on a xilinx FPGA-SOC | |
| US20160042097A1 (en) | System and method for concurrent multi-user analysis of design models | |
| CN103218250B (en) | A kind of processor analogy method | |
| CN113094324A (en) | Guidance information inter-core interaction method and system based on shared memory | |
| CN103345413A (en) | Method and device for updating codes and electronic equipment | |
| CN112052040A (en) | Processing method, processing device, computer equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210709 |