CN113078991B - Frequency calibration system, method and transponder - Google Patents

Frequency calibration system, method and transponder Download PDF

Info

Publication number
CN113078991B
CN113078991B CN202110237217.4A CN202110237217A CN113078991B CN 113078991 B CN113078991 B CN 113078991B CN 202110237217 A CN202110237217 A CN 202110237217A CN 113078991 B CN113078991 B CN 113078991B
Authority
CN
China
Prior art keywords
frequency
clock signal
phase
target
preset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110237217.4A
Other languages
Chinese (zh)
Other versions
CN113078991A (en
Inventor
黄金煌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Unigroup Tsingteng Microsystems Co Ltd
Original Assignee
Beijing Unigroup Tsingteng Microsystems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Unigroup Tsingteng Microsystems Co Ltd filed Critical Beijing Unigroup Tsingteng Microsystems Co Ltd
Priority to CN202110237217.4A priority Critical patent/CN113078991B/en
Publication of CN113078991A publication Critical patent/CN113078991A/en
Application granted granted Critical
Publication of CN113078991B publication Critical patent/CN113078991B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/59—Responders; Transponders
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0091—Transmitter details

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The present disclosure provides a frequency calibration system, method and transponder, wherein the system comprises: the phase-locked loop is used for operating on the basis of the reference clock signal, the preset frequency division ratio and the first preset clock signal so as to output a second preset clock signal; the second input end of the time-to-digital conversion unit is used for inputting a first target clock signal and determining a target frequency dividing ratio of the phase-locked loop according to a second preset frequency of a second preset clock signal and a first target frequency of the first target clock signal; the phase-locked loop is also configured to operate based on the target division ratio to output a second target clock signal. The system can determine the frequency dividing ratio of the phase-locked loop through the time-to-digital conversion unit, and then the phase-locked loop outputs the clock signal meeting the frequency requirement when running according to the determined frequency dividing ratio, so that the frequency is calibrated, the accuracy of frequency calibration can be improved, and the signal transmission quality is favorably improved.

Description

Frequency calibration system, method and transponder
Technical Field
The present disclosure relates to the field of near field communication technologies, and in particular, to a frequency calibration system, a frequency calibration method, and a transponder.
Background
At present, the short-distance wireless communication technology is widely applied to smart phones and mobile devices, brings great convenience to the fields of traffic, payment, entrance guard and the like, but simultaneously puts high requirements on an entrance coupling system of the smart phones and the mobile devices, and as antenna coils in the smart phones and the mobile devices become smaller and more serious, an Active transponder replaces passive Load Modulation by Active Load Modulation (ALM), and simultaneously brings the problem that a clock required by data transmission of the Active transponder is in the same frequency and phase as a 13.56MHZ +/-7 KHZ carrier clock transmitted by a card reader. Therefore, in order to ensure that the card reader can effectively receive the data transmitted by the transponder, the design and research of the frequency calibration circuit of the active transponder have great significance.
In the related art, in the process of transmitting signals, an active transponder needs to transmit signals by relying on a clock recovered by a carrier clock, so that the accuracy of the clock when the active transponder actively transmits the signals is influenced, and the reliability of signal transmission is low.
Disclosure of Invention
The present disclosure is directed to solving, at least to some extent, one of the technical problems in the related art.
The main technical scheme of the disclosure is as follows.
An embodiment of a first aspect of the present disclosure provides a frequency calibration system, including: the phase-locked loop comprises a phase-locked loop, a first input end of the phase-locked loop is used for inputting a reference clock signal, and the phase-locked loop is used for operating based on the reference clock signal, a preset frequency division ratio and a first preset clock signal so as to output a second preset clock signal, wherein the second preset frequency of the second preset clock signal is equal to a first positive integer multiple of a first target frequency of a first target clock signal; a first input end of the time-to-digital conversion unit is connected with an output end of the phase-locked loop, a second input end of the time-to-digital conversion unit is used for inputting a first target clock signal, and an output end of the time-to-digital conversion unit is connected with a second input end of the phase-locked loop; the time-to-digital conversion unit is configured to determine a target frequency division ratio of the phase-locked loop according to a second preset frequency of the second preset clock signal and a first target frequency of a first target clock signal; the phase-locked loop is further configured to operate based on the target frequency division ratio to output a second target clock signal, where a second target frequency of the second target clock signal is a second positive integer multiple of the first target frequency.
In addition, the frequency calibration system proposed according to the above embodiment of the present disclosure may also have the following additional technical features.
According to an embodiment of the present disclosure, the time-to-digital conversion unit includes: the phase inverter delay chain comprises a plurality of phase inverters which are sequentially connected end to end, wherein the input end of the first phase inverter is connected with the output end of the phase-locked loop; the sampling circuit comprises a plurality of D flip-flops, the D flip-flops correspond to the inverters one by one, the D input end of each D flip-flop is connected with the output end of the corresponding inverter, and the CK input end of each D flip-flop is used for inputting the first target clock signal; the input end of the frequency division ratio recombination circuit is connected with the output end of each D trigger, and the output end of the frequency division ratio recombination circuit is connected with the second input end of the phase-locked loop; the sampling circuit samples the second preset clock signal through the rising edge of the first target clock signal to obtain a sampling signal, and the frequency division ratio recombination circuit is used for determining the target frequency division ratio according to the sampling signal.
According to an embodiment of the present disclosure, the frequency division ratio recombining circuit is specifically configured to: acquiring a first average number of the delay times respectively contained in a plurality of second preset periods of the second preset clock signal and a second average number of the delay times respectively contained in a plurality of first target periods of the first target clock signal; and determining the target frequency dividing ratio according to the first average number, the second average number and the preset frequency dividing ratio.
According to an embodiment of the present disclosure, the phase-locked loop includes: the device comprises a phase frequency detector, a charge pump, a passive filter, a voltage-controlled oscillator and a frequency divider; the input end of the phase frequency detector is used as the input end of the phase-locked loop, the first input end of the phase frequency detector is used for inputting a reference clock signal, and the second input end of the phase frequency detector is connected with the output end of the frequency divider; the input end of the charge pump is connected with the output end of the phase frequency detector, the output end of the charge pump is connected with the input end of the passive filter, and the output end of the passive filter is connected with the input end of the voltage-controlled oscillator; and the output end of the voltage-controlled oscillator is used as the output end of the phase-locked loop, and the output end of the voltage-controlled oscillator is respectively connected with the first input end of the time-to-digital conversion unit and the input end of the frequency divider.
According to an embodiment of the present disclosure, the frequency calibration system further includes: the frequency division ratio presetting unit is used for storing a preset frequency division ratio; the input end of the multiplexer is respectively connected with the output end of the frequency dividing ratio presetting unit and the output end of the time-to-digital conversion unit, the output end of the multiplexer is connected with the frequency divider, and the input end of the multiplexer is used for transmitting the preset frequency dividing ratio or the target frequency dividing ratio to the frequency divider; when the input end of the multiplexer is used for inputting a preset frequency dividing ratio, the phase-locked loop operates based on the preset frequency dividing ratio to output a second preset clock signal; when the input end of the multiplexer is used for inputting a target frequency dividing ratio, the phase-locked loop operates based on the target frequency dividing ratio to output a second target clock signal.
According to an embodiment of the present disclosure, the frequency divider includes: integer frequency dividers, fractional frequency dividers and sigma-delta modulators; the input end of the integer frequency divider and the input end of the sigma-delta modulator are connected with the output end of the multi-path selector, the input end of the integer frequency divider is connected with the output end of the phase-locked loop, the output end of the sigma-delta modulator is connected with the input end of the fractional frequency divider, and the output end of the integer frequency divider and the output end of the fractional frequency divider are connected with the input end of the phase-locked loop.
According to an embodiment of the present disclosure, the frequency calibration system further includes: a first input end of the phase calibration unit is connected with an output end of the phase-locked loop and is used for carrying out frequency adjustment on a second target clock signal output by the phase-locked loop so as to output a first target clock signal; the input end of the transmitting unit is connected with the output end of the phase calibration unit; the magnetic induction coupling unit comprises a first antenna and a second antenna which are mutually and magnetically coupled, and two ends of the first antenna are connected with the output end of the transmitting unit; the input end of the carrier clock recovery circuit is connected with one end of the first antenna, and the output end of the carrier clock recovery circuit is respectively connected with the second input end of the phase calibration unit and the second input end of the time-to-digital conversion unit; the carrier clock recovery circuit is used for determining a first target clock signal according to a signal carried by the first antenna and respectively sending the first target clock signal to the phase calibration unit and the time-to-digital conversion unit; the transmitting unit is used for superposing modulation signals on the basis that the first target clock is used as a carrier signal, and sending the superposed signals to the second antenna.
An embodiment of a second aspect of the present disclosure provides a frequency calibration method, including: controlling the phase-locked loop to operate based on the reference clock signal, the preset frequency division ratio and the first preset clock signal so as to output a second preset clock signal; wherein a second preset frequency of the second preset clock signal is equal to a first positive integer multiple of a first target frequency of a first target clock signal; the control time digital conversion unit determines a target frequency dividing ratio of the phase-locked loop according to a second preset frequency of the second preset clock signal and a first target frequency of a first target clock signal; and controlling the phase-locked loop to operate based on the target frequency dividing ratio to output a second target clock signal, wherein a second target frequency of the second target clock signal is a second positive integer multiple of the first target frequency.
In addition, the frequency calibration method according to the above-described embodiment of the present disclosure may also have the following additional technical features.
According to an embodiment of the present disclosure, the determining a target frequency division ratio of the phase-locked loop according to a second preset frequency of the second preset clock signal and a first target frequency of a first target clock signal includes: sampling the second preset clock signal through the rising edge of the first target clock signal to obtain a sampling signal; and determining the target frequency dividing ratio according to the sampling signal.
In an embodiment of a second aspect of the present disclosure, a transponder is provided, which includes the frequency calibration system provided in an embodiment of the first aspect of the present disclosure.
Through the technical scheme, the frequency dividing ratio of the phase-locked loop can be determined through the time-to-digital conversion unit, and then when the phase-locked loop operates according to the determined frequency dividing ratio, the clock signal meeting the frequency requirement is output, the frequency is calibrated, the accuracy of frequency calibration can be improved, and the signal transmission quality is favorably improved.
Additional aspects and advantages of the disclosure will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosure.
Drawings
The above and/or additional aspects and advantages of the present disclosure will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic structural diagram of a frequency calibration system according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a time-to-digital conversion unit according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a frequency calibration system according to one embodiment of the present disclosure;
FIG. 4 is a schematic block diagram of a frequency calibration system according to one example of the present disclosure;
FIG. 5A is a timing diagram illustrating the operation of the time-to-digital conversion unit according to one embodiment of the present disclosure;
FIG. 5B is a timing diagram illustrating the operation of the time-to-digital conversion unit according to another embodiment of the present disclosure;
FIG. 6 is a flow chart of a method of frequency calibration according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a transponder according to an embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and intended to be illustrative of the present disclosure, and should not be construed as limiting the present disclosure.
Fig. 1 is a schematic structural diagram of a frequency calibration system according to an embodiment of the present disclosure.
As shown in fig. 1, the frequency calibration system 100 includes: a phase locked loop 10 and a time to digital conversion unit 20.
A first input end of the phase-locked loop 10 is configured to input a reference clock signal, and the phase-locked loop 10 is configured to operate based on the reference clock signal, a preset frequency division ratio and a first preset clock signal to output a second preset clock signal, where a second preset frequency of the second preset clock signal is equal to a first positive integer multiple of a first target frequency of a first target clock signal; a first input terminal of the time-to-digital conversion unit 20 is connected to the output terminal of the phase-locked loop 10, a second input terminal of the time-to-digital conversion unit 20 is used for inputting the first target clock signal, and an output terminal of the time-to-digital conversion unit 20 is connected to the second input terminal of the phase-locked loop 10.
The time-to-digital conversion unit 20 is configured to determine a target frequency division ratio of the phase-locked loop 10 according to a second preset frequency of the second preset clock signal and a first target frequency of the first target clock signal; the phase locked loop 10 is further configured to operate based on the target frequency division ratio to output a second target clock signal, wherein a second target frequency of the second target clock signal is a second positive integer multiple of the first target frequency.
It should be noted that the second predetermined frequency of the second predetermined clock signal is approximately equal to the first positive integer multiple of the first target frequency of 13.56MHZ ± 7KHZ, that is, the second predetermined frequency may be N (13.56MHZ ± 100KHZ), where N is a positive integer. The first target clock signal may be a signal representing a target frequency or a target period (a frequency or a period to which the frequency calibration is to be performed) or may be understood as a transmission signal satisfying an actual transmission frequency, and the second target frequency of the second target clock signal is approximately equal to a second positive integer multiple of the first target frequency, and the accuracy may reach 2 ppm.
In the embodiments of the present disclosure, a clock period of the first predetermined clock signal may be referred to as a first predetermined period, a clock period of the second predetermined clock signal may be referred to as a second predetermined period, a frequency of the first target clock signal may be referred to as a first target frequency, and a frequency of the second target clock signal may be referred to as a second target frequency.
It is understood that the pll 10 can be understood as a feedback circuit widely used in the wireless communication field, and during operation, when the output voltage and the input voltage keep a fixed phase difference, the loop is locked, and the ratio of the output frequency of the pll to the input reference frequency is equal to the preset frequency division ratio.
Specifically, when frequency calibration is required to support effective transmission of subsequent signals, the time-to-digital conversion unit 20 may be controlled to be turned off (i.e., in an inoperative state) and the phase-locked loop 10 may be controlled to be turned on (to start operating), a reference clock signal and a preset frequency division ratio may be preset for the phase-locked loop 10, an output signal of the phase-locked loop 10 may be preset as a first preset clock signal, and the phase-locked loop 10 operates based on the preset frequency division ratio, the reference clock signal and the first preset clock signal, that is, the first preset clock signal may be subjected to frequency division processing by the preset frequency division ratio and then input into the phase-locked loop 10 together with the reference clock signal, and a second preset clock signal is output when the phase-locked loop 10 operates and is locked. After the phase-locked loop 10 is locked, the time-to-digital conversion unit 20 may be controlled to be turned on, and then the time-to-digital conversion unit 20 receives a second preset clock signal and a first target clock signal, determines a target frequency division ratio of the phase-locked loop 10 according to a second preset frequency of the second preset clock signal and a first target frequency of the first target clock signal, and sends the target frequency division ratio to the phase-locked loop 10, so that the phase-locked loop 10 operates based on the reference clock signal, the target frequency division ratio, and the second preset clock signal to output a second target clock signal having a frequency that is an integral multiple of the first target frequency.
It should be noted that, when the reference clock signal, the preset frequency division ratio, and the first preset clock signal are preset, the preset frequency division ratio may be determined according to a first preset frequency of the first preset clock signal and a reference frequency of the reference clock signal, or the preset frequency division ratio may be determined according to a first preset period of the first preset clock signal and a reference period rate of the reference clock signal. The reference clock signal may be a signal generated by an external crystal oscillator.
For example, the reference period of the reference clock signal may be preset to T before the phase-locked loop 10 operatesRA first predetermined period T of a first predetermined clock signalVIs TR/72 (for T)RAnd 72) and may set the preset frequency division ratio to TR/TV. Then, the phase-locked loop 10 is turned on to start operating, after the phase-locked loop 10 is locked (at this time, the phase-locked loop outputs a second preset clock signal), the time-to-digital conversion unit 20 is turned on to start operating, and the time-to-digital conversion unit 20 starts operating according to a second preset frequency of the second preset clock signal and the first target clock signalThe first target frequency, determining a target frequency division ratio of the phase-locked loop 10, and sending the target frequency division ratio to the phase-locked loop 10, so that the phase-locked loop 10 operates based on the reference clock signal, the target frequency division ratio, and a second preset clock signal to output a second target clock signal having a frequency of 72 times the first target frequency.
The frequency calibration circuit of the embodiment of the disclosure may be applied to an active transponder (the active transponder receives information transmitted by a card reader and transmits the information to the card reader), in such a scenario, the first target clock signal is a signal transmitted by the card reader, and the frequency of the first target clock signal may be 13.56MHZ ± 7KHZ, and after the second target clock signal is obtained according to the phase locked loop 10 and the time-to-digital conversion unit 20, the second target clock signal may be calibrated correspondingly, for example, to be the first target clock signal, so that the active transponder transmits data to the card reader with 13.56MHZ ± 7KHZ as a carrier frequency.
The frequency calibration system of the embodiment of the disclosure can determine the frequency dividing ratio of the phase-locked loop through the time-to-digital conversion unit, and then the phase-locked loop outputs the clock signal meeting the frequency requirement when operating according to the determined frequency dividing ratio, so as to realize the calibration of the frequency, improve the accuracy of the frequency calibration, and be beneficial to improving the signal transmission quality.
In one embodiment of the present disclosure, as shown in fig. 2, the time-to-digital conversion unit 20 may include: an inverter delay chain 21, a sampling circuit 22, and a division ratio recombining circuit 23.
Referring to fig. 2, the inverter delay chain 21 may include a plurality of inverters (a first inverter INV1 to an nth inverter INVn) connected end to end, wherein an input end of the first inverter INV1 is connected to an output end of the phase locked loop 10, and an input end of the first inverter INV1 is used for inputting a second preset clock signal; the sampling circuit 22 includes a plurality of D flip-flops (a first D flip-flop D1 to an nth D flip-flop Dn) in one-to-one correspondence with a plurality of inverters, wherein a D input terminal of each D flip-flop is connected to an output terminal of the corresponding inverter, and a CK input terminal of each D flip-flop is used for inputting a first target clock signal; the input terminal of the division ratio recombining circuit 23 is connected to the output terminal of each D flip-flop, and the output terminal of the division ratio recombining circuit 23 is connected to the second input terminal of the phase locked loop 10.
The sampling circuit 22 samples the second preset clock signal through the rising edge of the first target clock signal to obtain a sampling signal, and the frequency division ratio recombination circuit 23 is configured to determine the target frequency division ratio according to the sampling signal.
Specifically, the first inverter INV1 of the time-to-digital conversion unit 20 receives the second preset clock signal, inverts the second preset clock signal, and outputs the inverted second preset clock signal to the second inverter INV2, meanwhile, the D input of the first D flip-flop D1 corresponding to the first inverter INV1 receives the inverted second preset clock signal FV2, the CK input of the first D flip-flop D1 receives the first target clock signal, when the first target clock signal is a rising edge, the first flip-flop D1 outputs the second preset clock signal, when each inverter and its corresponding D flip-flop are all operated, the sampling circuit 22 may sample the second preset clock signal to obtain a sampling signal, and may transmit the sampling signal to the frequency division ratio recombination circuit 23, and the frequency division ratio recombination circuit 23 determines the target frequency division ratio according to the sampling signal, and may transmit the target frequency division ratio to the phase-locked loop 10, so that the phase-locked loop 10 outputs a clock signal satisfying the requirement after operating.
Further, the frequency division ratio recombining circuit 23 may be specifically configured to: acquiring a first average number of delay times respectively contained in a plurality of second preset periods of a second preset clock signal and a second average number of delay times respectively contained in a plurality of first target periods of a first target clock signal; and determining a target frequency dividing ratio according to the first average number, the second average number and a preset frequency dividing ratio.
It should be noted that, in the embodiments of the present disclosure, a period of the first target clock signal may be referred to as a first target period, and a period of the second preset signal may be referred to as a second preset period. The first average number may be an average value of the numbers of the delay times included in the plurality of second preset periods, and the second average number may be an average value of the numbers of the delay times included in the plurality of first target periods.
Specifically, the frequency division ratio recombining circuit 23 may first obtain a first average number of delay times included in a plurality of second preset periods of the second preset clock signal and a second average number of delay times included in a plurality of first target periods of the first target clock signal, and then determine the target frequency division ratio according to the first average number, the second average number, and the preset frequency division ratio, for example, may first determine a product value between the first average number and the preset frequency division ratio, then may determine a ratio between the product value and the second average number, and use the ratio as the target frequency division ratio.
It should be noted that, in order to improve the accuracy of the inverter delay chain 21, the final purpose of the frequency calibration is to make the output frequency of the phase-locked loop 10 (i.e. the second target frequency) be an integer multiple, for example 72 times, of the first target frequency, so as to improve the accuracy of the inverter delay chain.
In one embodiment of the present disclosure, as shown in fig. 3, the phase locked loop 10 may include: a Phase Frequency Detector (PFD) 11, a Charge Pump (CP) 12, a Passive Filter (PF) 13, a Voltage Controlled Oscillator (VCO) 14, and a Frequency divider 15.
An input end of the phase frequency detector 11 serves as an input end of the phase-locked loop 10, a first input end of the phase frequency detector 11 is used for inputting a reference clock signal FR, and a second input end of the phase frequency detector 11 is connected with an output end of the frequency divider 15; the input end of the charge pump 12 is connected with the output end of the phase frequency detector 11, the output end of the charge pump 12 is connected with the input end of the passive filter 13, and the output end of the passive filter 13 is connected with the input end of the voltage-controlled oscillator 14; an output terminal of the voltage-controlled oscillator 14 serves as an output terminal of the phase-locked loop 10, and the output terminal of the voltage-controlled oscillator 14 is connected to a first input terminal of the time-to-digital conversion unit 20 and an input terminal of the frequency divider 15, respectively.
Specifically, after comparing the phase difference between the reference clock signal and the feedback signal of the frequency divider 15 (the signal fed back to the phase frequency detector by the frequency divider 15), the phase frequency detector 11 provides the output voltage value to the charge pump 12 according to the phase difference, and then the charge pump 12 converts the voltage value into the current amount and outputs the current amount to the passive filter 13, the passive filter 13 filters out the ac component of the current amount to generate the dc control voltage, the dc control voltage controls the frequency of the output signal of the voltage controlled oscillator 14, the output signal of the voltage controlled oscillator 14 is used as the output signal of the phase locked loop 10, and the output signal of the phase locked loop 10 is further frequency-divided by the frequency divider 15 and then fed back to the input terminal of the phase frequency detector 11. The loop is repeated until the phase-locked loop 10 is locked, and the voltage-controlled oscillator 14 outputs a signal with an integral multiple of the input frequency (the frequency of the reference clock signal).
Further, referring to fig. 3, the frequency calibration system 100 may further include: a frequency division ratio presetting unit 30 and a Multiplexer (MUX) 40.
The frequency division ratio presetting unit 30 is configured to store a preset frequency division ratio; the input end of the multiplexer 40 is connected to the output end of the frequency division ratio presetting unit 30 and the output end of the time-to-digital conversion unit 20, the output end of the multiplexer 40 is connected to the frequency divider 15, and the input end of the multiplexer 40 is used for transmitting the preset frequency division ratio or the target frequency division ratio to the frequency divider 15.
When the input terminal of the multiplexer 40 is used to input the preset frequency division ratio, the phase-locked loop 10 operates based on the preset frequency division ratio to output a second preset clock signal; when the input terminal of the multiplexer 40 is used to input the target frequency division ratio, the phase locked loop 10 operates based on the target frequency division ratio to output the second target clock signal.
Specifically, before signal transmission, in order to calibrate the frequency to a frequency satisfying a requirement to support signal transmission, a reference clock signal input to a first input terminal of the phase frequency detector 11 may be set in advance, a first preset clock signal output by the voltage controlled oscillator 14 may be set, a frequency division ratio of the frequency divider 15 may be set in advance as a preset frequency division ratio, the preset frequency division ratio may be stored in the frequency division ratio presetting unit 30, the multiplexer 40 is controlled to select the preset frequency division ratio output by the frequency division ratio presetting unit 30 to be transmitted to the frequency divider 15, so that the first preset clock signal is subjected to frequency division processing by the frequency divider 15 having the preset frequency division ratio, the frequency divider 15 feeds back the first preset clock signal after frequency division processing to a second input terminal of the phase frequency detector 11, and the phase difference between the reference clock signal and a feedback signal of the frequency divider 15 (a signal fed back to the phase detector by the frequency detector 15) may be compared by the phase frequency detector 11, the output voltage value according to the phase difference is sent to the charge pump 12, and then the charge pump 12 converts the voltage value into a current amount and outputs the current amount to the passive filter 13, the loop filter 13 filters an alternating current component of the current amount to generate a direct current control voltage, the direct current controls the frequency of an output signal of the voltage-controlled oscillator 14, the output signal of the voltage-controlled oscillator 14 is used as an output signal of the phase-locked loop 10, and the output signal of the phase-locked loop 10 is further frequency-divided by the frequency divider 15 and then fed back to the input end of the phase frequency detector 11. The above-mentioned cycle is repeated until the phase locked loop 10 is locked, and the voltage controlled oscillator 14 outputs the second preset clock signal.
After the phase locked loop 10 is locked, the time-to-digital conversion unit 20 may be controlled to be turned on, and then the first inverter INV1 of the time-to-digital conversion unit 20 receives the second preset clock signal, the sampling unit 22 of the time-to-digital conversion unit 20 receives the first target clock signal, and when the first target clock signal is a rising edge, the sampling unit 22 samples the second preset clock signal to obtain a sampled signal, and then the division ratio recombination circuit 23 determines a target division ratio according to the sampled signal and may transmit the target division ratio to the multiplexer 40, and at the same time, the multiplexer 40 may be controlled to transmit the target division ratio output by the division ratio recombination circuit 23 to the frequency divider 15, so that the second preset clock signal is subjected to frequency division processing by the frequency divider 15 whose division ratio is the target division ratio, and the frequency divider 15 feeds back the second preset clock signal after frequency division processing to the second input end of the phase frequency discriminator 11, then, after comparing the phase difference between the reference clock signal and the feedback signal of the frequency divider 15 (the signal fed back to the phase frequency detector by the frequency divider 15), the phase frequency detector 11 provides the output voltage value to the charge pump 12 according to the phase difference, and then the charge pump 12 converts the voltage value into the current amount and outputs the current amount to the passive filter 13, the loop filter 13 filters out the alternating current component of the current amount to generate the direct current control voltage, the direct current controls the frequency of the output signal of the voltage controlled oscillator 14, the output signal of the voltage controlled oscillator 14 is used as the output signal of the phase locked loop 10, and the output signal of the phase locked loop 10 is further frequency-divided by the frequency divider 15 and then fed back to the input terminal of the phase frequency detector 11. The above cycle is repeated, until the phase locked loop 10 is locked, the voltage controlled oscillator 14 outputs the second target clock signal (the frequency is an integral multiple of the frequency of the first target clock signal), so that the clock signal meeting the requirement can be obtained, and the precise calibration of the frequency is realized.
In one example of the present disclosure, as shown in fig. 4, the frequency divider 15 may include: an integer divider 152, a fractional divider 151, and a Sigma-Delta Modulator (SDM)153 (also referred to as a Sigma Delta Modulator).
The input end of the integer frequency divider 152 and the input end of the sigma-delta modulator 153 are connected to the output end of the multiplexer 40, the input end of the integer frequency divider 152 is connected to the output end of the phase-locked loop 10, the output end of the sigma-delta modulator 153 is connected to the input end of the fractional frequency divider 151, and the output end of the integer frequency divider 152 and the output end of the fractional frequency divider 151 are connected to the input end of the phase-locked loop 10.
Referring to fig. 3 and 4, the frequency calibration circuit may further include: phase calibration unit 50, transmitting unit 60, magnetic induction coupling unit 70 and carrier clock recovery circuit 80.
A first input end of the phase calibration unit 50 is connected to an output end of the phase-locked loop 10 (i.e., an output end of the voltage-controlled oscillator 11), and is configured to perform frequency adjustment on a second target clock signal output by the phase-locked loop 10 to output a first target clock signal; the input end of the transmitting unit 60 is connected with the output end of the phase calibration unit 50; the magnetic induction coupling unit 70 comprises a first antenna 71 and a second antenna 72 which are mutually and magnetically coupled, and two ends of the first antenna 71 are connected with the output end of the transmitting unit 60; an input end of the carrier clock recovery circuit 80 is connected to one end of the first antenna 71, and an output end of the carrier clock recovery circuit 80 is connected to a second input end of the phase calibration unit 50 and a second input end of the time-to-digital conversion unit 20, respectively.
The carrier clock recovery circuit 80 is configured to determine a first target clock signal according to a signal carried by the first antenna 71, and send the first target clock signal to the phase calibration unit 50 and the time-to-digital conversion unit 20, respectively; the transmitting unit 60 may be configured to superimpose the modulated signal on the basis of the first target clock signal as a carrier signal and send the superimposed signal to the second antenna 72.
It will be appreciated that the first antenna 71 may be an antenna of an active transponder and the second antenna 72 may be an antenna of a reader corresponding to the transponder.
The operation of applying the frequency calibration system 100 to an active transponder is described below by way of a specific example.
Before the system is operated, the phase-locked loop 10 is operated according to the frequency (preset T) of the reference clock signal FTAL input from the outsideR≈TCR) And the output signal of the voltage controlled oscillator 14 (e.g. with a period T)CR/72), the preset frequency division ratio of the phase locked loop 10 can be calculated according to the formula (1):
Figure GDA0003694141020000091
wherein, TRFor the period of an externally input clock FTAL (reference clock signal), TVFor the period of the output clock of the voltage controlled oscillator 14, TCRPeriod of output clock, N, for carrier recovery clock circuit 801For a preset integer division ratio, F1Is a fractional division ratio.
N is to be1、F1Written in advance in a register of the division ratio presetting unit 30, controls the output of the output division ratio presetting unit 30 circuit of the multiplexer MUX40 as inputs of the integer divider 152 and the sigma-delta modulator (SDM)153, i.e., controls the division ratio presetting unit 30 to divide the integer division ratio N1Inputting integer frequency divider 152, dividing the decimal frequency by F1Input to a sigma-delta modulator (SDM) 153.
After the preset operation is completed, the time-to-digital conversion unit TDC20 is turned off, the phase-locked loop 10 is turned on to enable the loop to work, after the mode-locked loop is locked, the TDC20 is turned on to enable the loop to work, and then the output of the MUX40 can be controlled to select the target frequency dividing ratio N of the output of the TDC202And F2I.e. the target frequency dividing ratio N2And F2As inputs to an integer divider 152 and sigma-delta modulator (SDM)153, respectively.
The working principle of the time-to-digital conversion unit 20 is as follows:
FIGS. 5A and 5B are timing diagrams of the operation of the time-to-digital conversion unit, (where FCR may be used to represent a first target clock signal and FV may be used to represent a second predetermined clock signal), the VCO14 output clock (i.e., the second predetermined clock signal) is sampled by the rising edge of the output clock (i.e., the first target clock signal) of the carrier recovery clock circuit 80, and the average clock period output by the VCO14 is calculated every M output clock periods of the carrier recovery clock circuit 80
Figure GDA0003694141020000101
And average clock period of the output of the carrier recovery clock circuit 80
Figure GDA0003694141020000102
Figure GDA0003694141020000103
Figure GDA0003694141020000104
Wherein N is a TCRNumber of whole clocks, T, output by VCO14 during cycle timeLSBFor the delay time of each stage of the inverter of the time-to-digital conversion unit 20, Δ T1, Δ T2, Δ T3 may pass through TLSBSimilarly, the output clock period of the carrier recovery clock circuit 80 and the output clock period of the voltage controlled oscillator VCO14 may also pass through TLSBThe measurement is carried out by measuring the time of the measurement,
Figure GDA0003694141020000105
for each VCO14 output clock period TLSBThe average number of (a) and (b),
Figure GDA0003694141020000106
recovering the clock CR80 output clock cycle T for each carrierLSBThe reduction of T required to reduce the TDC20 quantization errorLSBSo that it can improve
Figure GDA0003694141020000107
And
Figure GDA0003694141020000108
until will
Figure GDA0003694141020000109
And
Figure GDA00036941410200001010
the sampling precision of (2) is improved to N x FV(FVOutput clock frequency for VCO 14), assume FV＝1GHZ，N＝40，
Figure GDA00036941410200001011
And
Figure GDA00036941410200001012
the sampling frequency of (2) can reach 40 GHz.
The VCO14 output clock period in the phase locked loop 10 is ultimately calibrated to be accurate
Figure GDA0003694141020000111
Thereby obtaining a target frequency dividing ratio (fractional frequency dividing ratio F)2And integer division ratio N2)：
Figure GDA0003694141020000112
The following can be derived from equations (1) and (2):
Figure GDA0003694141020000113
the following equations (4), (3) and (5) can be derived:
Figure GDA0003694141020000114
then, respectively adding N2And F2The signals are input into an integer divider 152 and a sigma-delta modulator (SDM)153 through a MUX40, the phase-locked loop 10 operates based on a target division ratio, and after a period of time, the phase-locked loop 10 is locked again, and at the moment, the output clock period of the voltage-controlled oscillator VCO14 is high-precision
Figure GDA0003694141020000115
And the frequency calibration process is carried out in real time when the active transponder is not actively transmitting (ALM), so that the accuracy of the clock frequency when the active transponder is actively transmitting (ALM) is ensured. After the phase-locked loop 10 is locked again, the output frequency of the voltage-controlled oscillator VCO14 is 72 times that of the output clock of the carrier clock recovery circuit CR80, so that the accuracy of the inverter delay chain can be improved.
The voltage controlled oscillator VCO14 with the frequency calibrated outputs the output clock (i.e. the second target clock signal) to the phase calibration unit 50, outputs a 13.56MHZ ± 7KHZ clock with the same frequency and phase as the output clock voltage of the carrier recovery clock CR80 after the phase calibration, and the 13.56MHZ ± 7KHZ clock output by the phase calibration unit 50 drives the transmission circuit TX60 to transmit the digital modulation signal, and then transmits the digital modulation signal to the card reader antenna L2 through the active transponder antenna L1, thereby completing the active transmission of the active transponder.
It should be noted that, the clock used for active load modulation of the active transponder comes from the 13.56MHZ ± 7KHZ carrier wave transmitted by the reader, and in order for the reader to reliably receive the data transmitted by the transponder, the transponder must have a reliable frequency calibration and phase calibration circuit so that the data transmission clock of the active transponder is in the same frequency and phase as the 13.56MHZ ± 7KHZ carrier wave transmitted by the reader. Through the frequency calibration system provided by the embodiment of the disclosure, the frequency calibration can be performed when the active transponder does not actively transmit the ALM, so that the clock recovered by the carrier clock is not relied on when the ALM is actively transmitted, and the transmission efficiency is improved.
In summary, the frequency calibration system according to the embodiment of the present disclosure introduces the time-to-digital conversion unit, and can improve the frequency calibration accuracy by reducing the delay time of the delay chain; the Active transponder carries out frequency calibration when the Active Load Modulation (ALM) is not actively transmitted, and the Active transponder does not depend on a clock recovered by a carrier clock when the ALM is transmitted, so that the transmission quality is improved; the method can calibrate the frequency in real time when the active transponder does not actively transmit the ALM, ensures the accuracy of the clock frequency when the active transponder actively transmits the ALM, and has the advantages of simple structure and easy integration.
It should be noted that the above embodiments are merely illustrative of the basic idea of the present disclosure, and the constituent circuits related to the present disclosure are not drawn in terms of the number, shape, arrangement of devices, and connection manner of the constituent circuits in actual implementation. The actual implementation of the method can be changed freely according to the type, number, connection mode, device arrangement mode and device parameters of each circuit.
The embodiment of the disclosure also provides a frequency calibration method. Fig. 6 is a flowchart of a frequency calibration method according to an embodiment of the disclosure.
As shown in fig. 6, the method comprises the steps of:
s601, controlling the phase-locked loop to operate based on the reference clock signal, the preset frequency division ratio and the first preset clock signal to output a second preset clock signal, wherein a second preset frequency of the second preset clock signal is equal to a first positive integer multiple of a first target frequency of the first target clock signal.
And S602, controlling the time-to-digital conversion unit to determine a target frequency dividing ratio of the phase-locked loop according to a second preset frequency of the second preset clock signal and a first target frequency of the first target clock signal.
And S603, controlling the phase-locked loop to operate based on the target frequency dividing ratio to output a second target clock signal, wherein a second target frequency of the second target clock signal is a second positive integer multiple of the first target frequency.
In an embodiment of the present disclosure, the determining the target frequency division ratio of the phase-locked loop according to the second preset frequency of the second preset clock signal and the first target frequency of the first target clock signal in step S602 may include: sampling a second preset clock signal through the rising edge of the first target clock signal to obtain a sampling signal; and determining a target frequency dividing ratio according to the sampling signal.
It should be noted that, for the specific implementation of the frequency calibration method in the embodiment of the present disclosure, reference may be made to the specific implementation of the frequency calibration system, and details are not described herein again to avoid redundancy.
According to the frequency calibration method, the frequency division ratio of the phase-locked loop can be determined through the time-to-digital conversion unit, and then when the phase-locked loop operates according to the determined frequency division ratio, the clock signal meeting the frequency requirement is output, so that the frequency calibration is realized, the accuracy of the frequency calibration can be improved, and the signal transmission quality is favorably improved.
The embodiment of the disclosure also provides a transponder. Fig. 7 is a schematic structural diagram of a transponder according to an embodiment of the present disclosure.
As shown in fig. 7, the transponder 1000 includes the frequency calibration system 100 proposed in the above embodiment.
The transponder 1000 is an active transponder.
The transponder of the embodiment of the present disclosure, through its frequency calibration system, can determine the frequency dividing ratio of the phase-locked loop through the time-to-digital conversion unit, and then when the phase-locked loop operates according to the determined frequency dividing ratio, output the clock signal satisfying the frequency requirement, realize the calibration of the frequency, can improve the accuracy of the frequency calibration, and is favorable to improving the signal transmission quality.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In the description of the present disclosure, "plurality" means at least two, e.g., two, three, etc., unless explicitly defined otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present disclosure in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present disclosure.
The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present disclosure may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present disclosure may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure, and that changes, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present disclosure.

Claims (8)

1. A frequency calibration system, comprising:
the phase-locked loop comprises a phase-locked loop, a first input end of the phase-locked loop is used for inputting a reference clock signal, and the phase-locked loop is used for operating based on the reference clock signal, a preset frequency division ratio and a first preset clock signal so as to output a second preset clock signal, wherein the second preset frequency of the second preset clock signal is equal to a first positive integer multiple of a first target frequency of a first target clock signal;
a first input end of the time-to-digital conversion unit is connected with an output end of the phase-locked loop, a second input end of the time-to-digital conversion unit is used for inputting a first target clock signal, and an output end of the time-to-digital conversion unit is connected with a second input end of the phase-locked loop;
the time-to-digital conversion unit is configured to determine a target frequency division ratio of the phase-locked loop according to a second preset frequency of the second preset clock signal and a first target frequency of a first target clock signal; the phase-locked loop is further configured to operate based on the target frequency division ratio to output a second target clock signal, wherein a second target frequency of the second target clock signal is equal to a second positive integer multiple of the first target frequency;
the time-to-digital conversion unit includes:
the phase inverter delay chain comprises a plurality of phase inverters which are sequentially connected end to end, wherein the input end of the first phase inverter is connected with the output end of the phase-locked loop;
the sampling circuit comprises a plurality of D triggers, the D triggers correspond to the inverters one by one, the D input end of each D trigger is connected with the output end of the corresponding inverter, and the CK input end of each D trigger is used for inputting the first target clock signal;
the input end of the frequency division ratio recombination circuit is connected with the output end of each D trigger, and the output end of the frequency division ratio recombination circuit is connected with the second input end of the phase-locked loop;
the sampling circuit samples the second preset clock signal through the rising edge of the first target clock signal to obtain a sampling signal, and the frequency division ratio recombination circuit is used for determining the target frequency division ratio according to the sampling signal;
the frequency dividing ratio recombining circuit is specifically configured to obtain a first average number of delay times included in a plurality of second preset periods of the second preset clock signal and a second average number of the delay times included in a plurality of first target periods of the first target clock signal, and determine the target frequency dividing ratio according to the first average number, the second average number, and the preset frequency dividing ratio.
2. The system of claim 1, wherein the phase-locked loop comprises:
the device comprises a phase frequency detector, a charge pump, a passive filter, a voltage-controlled oscillator and a frequency divider; wherein, the first and the second end of the pipe are connected with each other,
the output end of the phase frequency detector is used as the input end of the phase-locked loop, the first input end of the phase frequency detector is used for inputting a reference clock signal, and the second input end of the phase frequency detector is connected with the output end of the frequency divider;
the input end of the charge pump is connected with the output end of the phase frequency detector, the output end of the charge pump is connected with the input end of the passive filter, and the output end of the passive filter is connected with the input end of the voltage-controlled oscillator;
and the output end of the voltage-controlled oscillator is used as the output end of the phase-locked loop, and the output end of the voltage-controlled oscillator is respectively connected with the first input end of the time-to-digital conversion unit and the input end of the frequency divider.
3. The system of claim 2, further comprising:
the frequency division ratio presetting unit is used for storing a preset frequency division ratio;
the input end of the multiplexer is respectively connected with the output end of the frequency dividing ratio presetting unit and the output end of the time-to-digital conversion unit, the output end of the multiplexer is connected with the frequency divider, and the input end of the multiplexer is used for transmitting the preset frequency dividing ratio or the target frequency dividing ratio to the frequency divider;
when the input end of the multiplexer is used for inputting a preset frequency dividing ratio, the phase-locked loop operates based on the preset frequency dividing ratio to output a second preset clock signal;
when the input end of the multiplexer is used for inputting a target frequency dividing ratio, the phase-locked loop operates based on the target frequency dividing ratio to output a second target clock signal.
4. The system of claim 3, wherein the frequency divider comprises:
integer frequency dividers, fractional frequency dividers and sigma-delta modulators;
the input end of the integer frequency divider and the input end of the sigma-delta modulator are connected with the output end of the multi-path selector, the input end of the integer frequency divider is connected with the output end of the phase-locked loop, the output end of the sigma-delta modulator is connected with the input end of the fractional frequency divider, and the output end of the integer frequency divider and the output end of the fractional frequency divider are connected with the input end of the phase-locked loop.
5. The system of claim 1, further comprising:
a first input end of the phase calibration unit is connected with an output end of the phase-locked loop and is used for carrying out frequency adjustment on a second target clock signal output by the phase-locked loop so as to output a first target clock signal;
the input end of the transmitting unit is connected with the output end of the phase calibration unit;
the magnetic induction coupling unit comprises a first antenna and a second antenna which are mutually magnetically coupled, and two ends of the first antenna are connected with the output end of the transmitting unit;
the input end of the carrier clock recovery circuit is connected with one end of the first antenna, and the output end of the carrier clock recovery circuit is respectively connected with the second input end of the phase calibration unit and the second input end of the time-to-digital conversion unit;
the carrier clock recovery circuit is used for determining a first target clock signal according to a signal carried by the first antenna and respectively sending the first target clock signal to the phase calibration unit and the time-to-digital conversion unit; the transmitting unit is used for superposing a modulation signal on the basis of taking the first target clock signal as a carrier signal and sending the superposed signal to the second antenna.
6. A frequency calibration method based on the frequency calibration system according to any one of claims 1 to 5, comprising:
controlling a phase-locked loop to operate based on a reference clock signal, a preset frequency division ratio and a first preset clock signal so as to output a second preset clock signal, wherein a second preset frequency of the second preset clock signal is equal to a first positive integer multiple of a first target frequency of a first target clock signal;
the control time digital conversion unit determines a target frequency dividing ratio of the phase-locked loop according to a second preset frequency of the second preset clock signal and a first target frequency of a first target clock signal;
and controlling the phase-locked loop to operate based on the target frequency dividing ratio to output a second target clock signal, wherein a second target frequency of the second target clock signal is a second positive integer multiple of the first target frequency.
7. The method of claim 6, wherein determining the target frequency division ratio of the phase-locked loop according to the second preset frequency of the second preset clock signal and the first target frequency of the first target clock signal comprises:
sampling the second preset clock signal through the rising edge of the first target clock signal to obtain a sampling signal;
and determining the target frequency dividing ratio according to the sampling signal.
8. A transponder, characterized in that it comprises a frequency calibration system according to any one of claims 1-5.
CN202110237217.4A 2021-03-03 2021-03-03 Frequency calibration system, method and transponder Active CN113078991B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110237217.4A CN113078991B (en) 2021-03-03 2021-03-03 Frequency calibration system, method and transponder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110237217.4A CN113078991B (en) 2021-03-03 2021-03-03 Frequency calibration system, method and transponder

Publications (2)

Publication Number Publication Date
CN113078991A CN113078991A (en) 2021-07-06
CN113078991B true CN113078991B (en) 2022-07-22

Family

ID=76609805

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110237217.4A Active CN113078991B (en) 2021-03-03 2021-03-03 Frequency calibration system, method and transponder

Country Status (1)

Country Link
CN (1) CN113078991B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113484565B (en) * 2021-07-14 2024-02-13 国网新疆电力有限公司电力科学研究院 DC signal generating device for calibrating low-frequency AC signal and calibration method
CN114421967B (en) * 2022-01-24 2024-05-31 高澈科技(上海)有限公司 Phase interpolation circuit, phase-locked loop, chip and electronic equipment
CN116015285B (en) * 2022-12-31 2024-03-12 成都电科星拓科技有限公司 Method and device for correcting TDC delay stepping based on stepping LDO
CN116094513B (en) * 2023-04-04 2023-06-23 苏州萨沙迈半导体有限公司 Decimal frequency dividing system, decimal frequency dividing method and decimal frequency dividing chip
CN117608868B (en) * 2024-01-24 2024-04-09 苏州元脑智能科技有限公司 A clock generator a parameter adjusting method a system(s) device and medium

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7436227B2 (en) * 2003-05-02 2008-10-14 Silicon Laboratories Inc. Dual loop architecture useful for a programmable clock source and clock multiplier applications
US8041310B2 (en) * 2007-10-01 2011-10-18 Telefonaktiebolaget Lm Ericsson (Publ) Apparatus and methods for frequency control in a multi-output frequency synthesizer
KR101544994B1 (en) * 2008-09-16 2015-08-17 삼성전자주식회사 2 Two-point phase modulator and conversion gain calibration method thereof
US8384452B1 (en) * 2011-09-13 2013-02-26 Cortina Systems, Inc. Integrated jitter compliant low bandwidth phase locked loops
US8791763B2 (en) * 2012-08-09 2014-07-29 Qualcomm Incorporated Tunable injection locked dividers with enhanced locking range
CN103346790B (en) * 2013-07-19 2016-01-13 苏州磐启微电子有限公司 A kind of frequency synthesizer of quick lock in
CN111900977B (en) * 2020-07-20 2022-05-06 清华大学 Circuit for carrying out fast gain calibration on digital time converter of phase-locked loop

Also Published As

Publication number Publication date
CN113078991A (en) 2021-07-06

Similar Documents

Publication Publication Date Title
CN113078991B (en) Frequency calibration system, method and transponder
US9851696B2 (en) Circuit, a time-to-digital converter, an integrated circuit, a transmitter, a receiver and a transceiver
JP4386725B2 (en) Improved frequency divider with reduced jitter and transmitter based thereon
US20110064150A1 (en) Pll circuit with improved phase difference detection
JP5347534B2 (en) Phase comparator, PLL circuit, and phase comparator control method
US10911037B2 (en) Systems and methods for phase synchronization of local oscillator paths in oscillator-operated circuits
EP1249936A2 (en) Lock detection circuit
KR101787720B1 (en) Digital phase-locked loop using frequency shift keying and the method
EP2622741B1 (en) Reference clock sampling digital pll / fll
US11804847B2 (en) Fractional frequency synthesis by sigma-delta modulating frequency of a reference clock
US8248104B2 (en) Phase comparator and phase-locked loop
US8008979B2 (en) Frequency synthesizer and radio transmitting apparatus
EP1371167B1 (en) Fractional-n frequency synthesizer with fractional compensation method
US20090201094A1 (en) Phase comparison circuit and pll synthesizer using the same
US7298790B2 (en) Low frequency self-calibration of a PLL with multiphase clocks
US9602115B1 (en) Method and apparatus for multi-rate clock generation
CN111771332B (en) Phase-locked loop circuit
EP1297619B1 (en) Linear dead-band-free digital phase detection
US8451965B2 (en) Semiconductor integrated circuit, radio communication device and time to digital converter
EP1422826A1 (en) Exact self-calibration of a pll with multiphase clocks
US8040996B2 (en) Method and system for RF signal generation utilizing a synchronous multi-modulus divider
US20050036580A1 (en) Programmable phase-locked loop fractional-N frequency synthesizer
US20230318658A1 (en) Device comprising a synchronization circuit for performing near field communication
EP1638207B1 (en) Method of calibrating the frequency of an oscillator in a phase locked loop circuit
CN116743335A (en) Apparatus comprising a synchronization circuit for performing near field communication

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant