CN113077752A - Pixel driving circuit - Google Patents

Pixel driving circuit Download PDF

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Publication number
CN113077752A
CN113077752A CN202110386028.3A CN202110386028A CN113077752A CN 113077752 A CN113077752 A CN 113077752A CN 202110386028 A CN202110386028 A CN 202110386028A CN 113077752 A CN113077752 A CN 113077752A
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switch
control
control signal
period
voltage
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CN113077752B (en
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林志隆
林捷安
吴佳恩
蔡佳凌
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AU Optronics Corp
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AU Optronics Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention provides a pixel driving circuit, which comprises a light-emitting unit, ten switches and two capacitors. The driving current of the light emitting unit only flows through one of the switches, thereby saving power consumption. In addition, the pixel driving circuit can compensate the critical voltage and the operating voltage, so that the light-emitting unit can provide consistent brightness.

Description

Pixel driving circuit
Technical Field
The present disclosure relates to a pixel driving circuit of a light emitting diode.
Background
Light emitting diodes are widely used in various types of displays. The brightness of the light emitting diode during light emission is related to the magnitude of the driving current thereof, and the magnitude of the driving current is controlled by the driving transistor. However, the threshold voltage (Vth) of the driving transistor of each pixel in the display is different due to process variation, so that the leds in different pixels have different driving currents and the brightness of each led is different, thereby causing the display to have a non-uniform brightness when displaying images. In addition, the driving current is provided by the operating voltage, and the operating voltage is likely to generate a voltage drop due to the line resistance in the transmission path, so that the operating voltage of each pixel is different, and the driving current generates an error.
Therefore, it is an objective of research by those skilled in the art to compensate for the threshold voltage of the driving transistor of a pixel of a display and also compensate for the operating voltage.
Disclosure of Invention
An embodiment of the present invention provides a pixel driving circuit, which includes the following components. The light emitting unit has a first end and a second end, and the first end of the light emitting unit is connected to a first operating voltage. The first switch has a first end, a second end and a control end, the first end of the first switch is connected with the second end of the light-emitting unit, and the second end of the first switch is connected to the second operating voltage. The second switch has a first end, a second end and a control end, the first end of the second switch is connected to the control end of the first switch, and the second end of the second switch is connected to the reference voltage. The first capacitor has a first end and a second end, and the first end of the first capacitor is connected to the control end of the first switch and the first end of the second switch. The third switch has a first end, a second end and a control end, the first end of the third switch is connected to the second operation voltage, and the control end of the third switch is connected to the control end of the second switch. The fourth switch has a first end, a second end and a control end, the first end of the fourth switch is connected to the second end of the first capacitor and the second end of the third switch, the second end of the fourth switch is connected to the first control signal, and the control end of the fourth switch is connected to the first voltage. The fifth switch has a first end, a second end and a control end, the first end of the fifth switch is connected to the second voltage, the second end of the fifth switch is connected to the control end of the second switch and the control end of the third switch, and the control end of the fifth switch is connected to the second control signal. The sixth switch has a first end, a second end and a control end, the first end of the sixth switch is connected to the control end of the second switch, the control end of the third switch and the second end of the fifth switch, and the control end of the sixth switch is connected to the third control signal. The seventh switch has a first end, a second end and a control end, the first end of the seventh switch is connected to the second end of the sixth switch, and the control end of the seventh switch is connected to the fourth control signal. The eighth switch has a first end, a second end and a control end, the first end of the eighth switch is connected to the second end of the seventh switch, the second end of the eighth switch is connected to the first control signal, and the control end of the eighth switch is connected to the reference voltage. The second capacitor has a first end and a second end, and the first end of the second capacitor is connected to the second end of the sixth switch and the first end of the seventh switch. And the ninth switch is provided with a first end, a second end and a control end, wherein the first end of the ninth switch is connected to the second end of the second capacitor, the second end of the ninth switch is connected to a data voltage, and the control end of the ninth switch is connected to the fourth control signal. The tenth switch has a first end, a second end and a control end, the first end of the tenth switch is connected to the second end of the second capacitor and the first end of the ninth switch, the second end of the tenth switch is connected to the first voltage, and the control end of the tenth switch is connected to the second control signal.
In some embodiments, the pixel driving circuit operates in a first period, a second period, a third period, and a fourth period in sequence. In the first period, the first switch, the third switch, the sixth switch, and the tenth switch are in an off state, and the second switch, the fourth switch, the fifth switch, the seventh switch, the eighth switch, and the ninth switch are in an on state. In the second period, the first switch, the third switch, the sixth switch, and the tenth switch are turned off, and the second switch, the fourth switch, the fifth switch, the seventh switch, the eighth switch, and the ninth switch are turned on. In the first sub-period of the third period, the first switch, the third switch, the fifth switch, the sixth switch, the seventh switch, and the ninth switch are in an off state, and the second switch, the fourth switch, the eighth switch, and the tenth switch are in an on state. In a second sub-period of the third period, the second switch, the fourth switch, the fifth switch, the seventh switch, and the ninth switch are turned off, and the first switch, the third switch, the sixth switch, the eighth switch, and the tenth switch are turned on. In the fourth period, the first switch, the third switch, the fourth switch, the sixth switch, the seventh switch, the ninth switch, and the tenth switch are in an off state, and the second switch, the fifth switch, and the eighth switch are in an on state.
In some embodiments, the third switch, the fifth switch, the seventh switch, and the ninth switch are P-type transistors, and the first switch, the second switch, the fourth switch, the sixth switch, the eighth switch, and the tenth switch are N-type transistors.
In some embodiments, the threshold voltage of the first switch is matched to the threshold voltage of the fourth switch, and the threshold voltage of the sixth switch is matched to the threshold voltage of the eighth switch.
In some embodiments, during the first period, the first control signal, the second control signal, and the fourth control signal are at a first low level, and the third control signal is at a second low level. In the second period, the first control signal is at a first high level, the second control signal and the fourth control signal are at a first low level, and the third control signal is at a second low level. In the third period, the first control signal, the second control signal and the fourth control signal are at the first high level, and the third control signal is gradually increased from the second low level to the second high level. In the fourth period, the first control signal and the fourth control signal are at the first high level, the second control signal is at the first low level, and the third control signal is at the second low level.
In some embodiments, the first operating voltage is greater than the second operating voltage, and the first voltage is less than the second voltage.
In some embodiments, the light emitting unit is a light emitting diode.
In some embodiments, the size of the light emitting diode is sub-millimeter.
In some embodiments, the pixel driving circuit is disposed in the display panel.
In some embodiments, the pixel driving circuit is disposed in the backlight module.
In the pixel driving circuit, the threshold voltage and the operating voltage can be compensated, and the technical effect of saving power consumption is achieved.
Drawings
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a circuit architecture diagram illustrating a pixel driving circuit according to an embodiment.
Fig. 2 is a timing diagram illustrating various control signals in the pixel driving circuit according to one embodiment.
Fig. 3 is a switching schematic diagram illustrating a pixel driving circuit during a first period according to an embodiment.
Fig. 4 is a switching diagram illustrating a pixel driving circuit during a second period according to an embodiment.
Fig. 5 is a switching diagram illustrating a pixel driving circuit in a first sub-period during a third period according to an embodiment.
Fig. 6 is a switching diagram illustrating a pixel driving circuit during a second sub-period in a third period according to an embodiment.
FIG. 7 is a switching diagram illustrating a pixel drive circuit during a fourth period according to one embodiment.
Description of reference numerals:
100: pixel driving circuit
110: light emitting unit
C1: first capacitor
C2: second capacitor
T1-T10: switch with a switch body
ILED: electric current
110-1, C1-1, C2-1, T1-1, T2-1, T3-1, T4-1, T5-1, T6-1, T7-1, T8-1, T9-1, T10-1: first end
110-2, C1-2, C2-2, T1-2, T2-2, T3-2, T4-2, T5-2, T6-2, T7-2, T8-2, T9-2, T10-2: second end
T1-3, T2-3, T3-3, T4-3, T5-3, T6-3, T7-3, T8-3, T9-3, T10-3: control terminal
A, B, C, D, E: node point
VDD, VSS: operating voltage
S1,S2,S3,Vsweep: control signal
VH,VL: voltage of
VDATA: data voltage
Vref: reference voltage
210: the first period
220: the second period
230: the third period
230-1: the first sub-period
230-2: the second sub-period
240: the fourth period
VGH,Vsweep_H: high level
VGL,Vsweep_L: low level of electricity
Detailed Description
As used herein, the terms "first," "second," and the like, do not denote any particular order or order, but rather are used to distinguish one element from another or from another.
Fig. 1 is a circuit architecture diagram illustrating a pixel driving circuit according to an embodiment. The pixel driving circuit 100 may be disposed on a backlight module of a display device to provide a backlight source, or disposed in a display panel as a pixel, which is not limited in this disclosure. The pixel driving circuit 100 includes a light emitting unit 110, switches T1-T10, a first capacitor C1 and a second capacitor C2. The light emitting unit 110 is, for example, a light emitting diode, and the size of the light emitting diode may be on the sub-millimeter scale or other suitable size, which is not limited in this disclosure.
The light emitting unit 110 has a first end 110-1 and a second end 110-2The first terminal 110-1 of 110 is connected to the operating voltage VDD. The switch T1 has a first terminal T1-1, a second terminal T1-2 and a control terminal T1-3, wherein the first terminal T1-1 of the switch T1 is connected to the second terminal 110-2 of the light emitting unit 110, and the second terminal T1-2 of the switch T1 is connected to the operation voltage VSS. The switch T2 has a first terminal T2-1, a second terminal T2-2 and a control terminal T2-3, the first terminal T2-1 of the switch T2 is connected to the control terminal T1-3 of the switch T1, and the second terminal T2-2 of the switch T2 is connected to a reference voltage Vref. The first capacitor C1 has a first terminal C1-1 and a second terminal C1-2, and the first terminal C1-1 of the first capacitor C1 is connected to the control terminal T1-3 of the switch T1 and the first terminal T2-1 of the switch T2. The switch T3 has a first terminal T3-1, a second terminal T3-2 and a control terminal T3-3, the first terminal T3-1 of the switch T3 is connected to the operation voltage VSS, and the control terminal T3-3 of the switch T3 is connected to the control terminal T2-3 of the switch T2. The switch T4 has a first terminal T4-1, a second terminal T4-2 and a control terminal T4-3, the first terminal T4-1 of the switch T4 is connected to the second terminal C1-2 of the first capacitor C1 and the second terminal T3-2 of the switch T3, the second terminal T4-2 of the switch T4 is connected to the control signal S1, the control terminal T4-3 of the switch T4 is connected to the voltage V1L. The switch T5 has a first terminal T5-1, a second terminal T5-2 and a control terminal T5-3, wherein the first terminal T5-1 of the switch T5 is connected to a voltage VHThe second terminal T5-2 of the switch T5 is connected to the control terminal T2-3 of the switch T2 and the control terminal T3-3 of the switch T3, and the control terminal T5-3 of the switch T5 is connected to the control signal S2.
The switch T6 has a first terminal T6-1, a second terminal T6-2 and a control terminal T6-3, the first terminal T6-1 of the switch T6 is connected to the control terminal T2-3 of the switch T2, the control terminal T3-3 of the switch T3 and the second terminal T5-2 of the switch T5, the control terminal T6-3 of the switch T6 is connected to the control signal Vsweep. The switch T7 has a first terminal T7-1, a second terminal T7-2 and a control terminal T7-3, the first terminal T7-1 of the switch T7 is connected to the second terminal T6-2 of the switch T6, and the control terminal T7-3 of the switch T7 is connected to the control signal S3. The switch T8 has a first terminal T8-1, a second terminal T8-2 and a control terminal T8-3, the first terminal T8-1 of the switch T8 is connected to the second terminal T7-2 of the switch T7, the second terminal T8-2 of the switch T8 is connected to the control signal S1, the control terminal T3-3 of the switch T8 is connected to the reference voltage V3-3ref. The second capacitor C2 has a first terminal C2-1 and a second terminal C2-2, and the first terminal C2-1 of the second capacitor C2 is connected to the second terminal T6-2 of the switch T6 and to the switchThe first end of T7, T7-1. The switch T9 has a first terminal T9-1, a second terminal T9-2 and a control terminal T9-3, the first terminal T9-1 of the switch T9 is connected to the second terminal C2-2 of the second capacitor C2, and the second terminal T9-2 of the switch T9 is connected to the data voltage VDATAThe control terminal T9-3 of the switch T9 is connected to the control signal S3. The switch T10 has a first terminal T10-1, a second terminal T10-2 and a control terminal T10-3, the first terminal T10-1 of the switch T10 is connected to the second terminal C2-2 of the second capacitor C2 and the first terminal T9-1 of the switch T9, the second terminal T10-2 of the switch T10 is connected to a voltage VLThe control terminal T10-3 of the switch T10 is connected to the control signal S2.
In this embodiment, the switches T1 to T10 are, for example, thin film transistors (thin film transistors), wherein the switches T3, T5, T7 and T9 are P-type transistors, and the switches T1, T2, T4, T6, T8 and T10 are N-type transistors. In addition, the threshold voltage of the switch T1 is matched to the threshold voltage of the switch T4, and the threshold voltage of the switch T6 is matched to the threshold voltage of the switch T8, and the technical effect of threshold voltage matching will be described in detail below.
Fig. 2 is a timing diagram illustrating various control signals in the pixel driving circuit according to one embodiment. Referring to fig. 2, the pixel driving circuit operates in the first period 210, the second period 220, the third period 230 and the fourth period 240 in sequence, and returns to the first period 210 after the fourth period 240 is finished.
In this embodiment, the operating voltage VDD is greater than the operating voltage VSS, and the voltage V is greater than the operating voltage VDDLLess than voltage VHReference voltage VrefGreater than voltage VL. In addition, the voltage VLGreater than low level VGLAnd a high level VGHGreater than voltage VH。
Fig. 3 is a switching schematic diagram illustrating a pixel driving circuit during a first period according to an embodiment. Referring to fig. 2 and 3, the first period 210 is used to reset the pixel driving circuit 100. During the first period 210, the control signal S1, the control signal S2 and the control signal S3 are at a low level VGLControl signal VsweepAt a low level Vsweep_LWherein the low level VGLMay be the same or different from the low level Vsweep_LThe disclosure is not so limited. Thus, during the first period 210, the switches T1, T3, T6, T10 are in the off state, and the switches T2, T4, T5, T7, T8, T9 are in the on state. Specifically, the potential of the node A is the same as the reference voltage VrefBut with reference to a voltage VrefLess than the threshold voltage of switch T1. Voltage VLGreater than the threshold voltage of the switch T4, so that the switch T4 is in the conducting state and the node B is at the same level as the low level VGL. The potential of the node C is the same as the voltage VH. Reference voltage VrefIs greater than the threshold voltage of the switch T8, so that the switch T8 is in the conducting state and the potential of the node D is the same as the low level VGL. The potential of the node E is the same as the data voltage VDATA。
Fig. 4 is a switching diagram illustrating a pixel driving circuit during a second period according to an embodiment. Referring to fig. 2 and 4, the second period 220 is used for voltage compensation. During the second period 220, the control signal S1 is at the high level VGHThe control signals S2 and S3 are at a low level VGLControl signal VsweepAt a low level Vsweep_L. Therefore, in the second period 220, the switches T1, T3, T6, and T10 are in the off state, and the switches T2, T4, T5, T7, T8, and T9 are in the on state. Specifically, the potential of the node A is the same as the reference voltage Vref. The potential of the node B will continuously rise due to the charging of the first capacitor C1 until the potential of the node B is the same as VL-VTH_T4The time switch T4 will be switched to the off state, where VTH_T4Is the threshold voltage of switch T4. The potential of the node C is the same as the voltage VH. Similarly, the potential of the node D will continuously rise until the potential of the node D is the same as Vref-VTH_T8The time switch T8 will be switched to the off state, where VTH_T8Is the threshold voltage of switch T8. The potential of the node E is the same as the data voltage VDATA。
Fig. 5 is a switching diagram illustrating a pixel driving circuit in a first sub-period during a third period according to an embodiment. Referring to fig. 2 and 5, the third period 230 is divided into a first sub-period 230-1 and a second sub-period 230-2, the light emitting unit 110 is turned off in the first sub-period 230-1, and light is emitted in the second sub-period 230-2The cell 110 is on and emits light. The lengths of the first sub-period 230-1 and the second sub-period 230-2 are determined by the data voltage VDATAAnd (4) determining. In other words, in this embodiment, the light emitting unit 110 is driven by Pulse Width Modulation (PWM), so as to determine the brightness of the pixel. Specifically, in the third period 230, the control signal S1, the control signal S2, and the control signal S3 are at the high level VGHControl signal VsweepFrom low level Vsweep_LGradually increases to a high level Vsweep_HWherein the high level Vsweep_HCan be the same as or different from the high level VGHThe disclosure is not so limited.
In the first sub-period 230-1, the switches T1, T3, T5, T6, T7, and T9 are in the off state, and the switches T2, T4, T8, and T10 are in the on state. The potential of the node A is the same as the reference voltage Vref. The potential of the node B is the same as VL-VTH_T4. The potential of the node C is kept constant and maintained at the voltage VH. Specifically, the potential of the node E is changed from the data voltage V of the second period 220DATAChange to the voltage V of the third period 230LThe amount of change is represented as VL-VDATATherefore, the potential of the node D will be changed from V of the second period 220ref-VTH_T8Change to Vref-VTH_T8+VL-VDATA. At this time, the control signal VsweepIs less than the potential of the node D, the switch T6 is in the off state.
Due to the control signal VsweepThe potential of (b) is continuously increased, and when the following equation 1 is satisfied, the switch T6 is switched to the on state, and then the second sub-period 230-2 is entered.
[ mathematical formula 1]
Figure BDA0003013674890000081
Wherein VDIs the potential of node D, VTH_T6Is the threshold voltage of switch T6. Since the threshold voltage of the switch T6 is matched to the threshold voltage of the switch T8, two threshold voltages are shown in equation 1VTH_T6、VTH_T8The effect of the threshold voltage of the switch T6 is cancelled out, i.e. removed. When the data voltage VDATAThe larger the value, the earlier the equation 1 is established, and the earlier the second sub-period 230-2 is entered.
Fig. 6 is a switching diagram illustrating a pixel driving circuit during a second sub-period in a third period according to an embodiment. Referring to fig. 2 and 6, in the second sub-period 230-2, the switches T2, T4, T5, T7 and T9 are turned off, and the switches T1, T3, T6, T8 and T10 are turned on. Specifically, since the switch T6 is turned on, the potentials of the node D and the node C are the same as Vref-VTH_T8+VL-VDATAThis potential turns off switch T2 and turns on switch T3. The potential of the node B is V from the first sub-period 230-1L-VTH_T4Changed to the operating voltage VSS by the amount VSS-VL+VTH_T4Therefore, the potential of the node A is derived from the reference voltage V of the first sub-period 230-1refChange to Vref+VSS-VL+VTH_T4This potential turns on switch T1 to generate current ILEDThe current ILEDA current I flows through the light emitting unit 110 and the switch T1LEDThe size of (d) is shown in the following equation 2.
[ mathematical formula 2]
Figure BDA0003013674890000082
Wherein K is a constant, VAIs the potential of node A, VTH_T1Is the threshold voltage of switch T1. Notably, since the threshold voltage of the switch T1 is matched to the threshold voltage of the switch T4, the current ILEDIs not influenced by the critical voltage VTH_T1The influence of (c). In addition, since the operating voltage VSS is compensated in equation 2, the current ILEDIs also not affected by the operating voltage VSS. In the prior art, when the driving current passes through more than two switches, the voltage drop is generated when the current is larger, so that the switches can enter the linear region, and the problem can be solved by increasing the voltage across the operating voltages VDD and VSS,but increases power consumption. In contrast, the current ILEDOnly one switch T1 will flow, thus having the technical effect of reducing power consumption.
FIG. 7 is a switching diagram illustrating a pixel drive circuit during a fourth period according to one embodiment. Referring to fig. 2 and 7, the fourth period 240 is used to turn off the light emitting unit 110. During the fourth period 240, the control signals S1 and S3 are high VGHThe control signal S2 is at a low level VGLControl signal VsweepAt a low level Vsweep_L. Therefore, the switches T1, T3, T4, T6, T7, T9, and T10 are in the off state, and the switches T2, T5, and T8 are in the on state. The potential of the node A is a reference voltage VrefThereby turning off switch T1. The potential of the node C is a voltage VH。
In the above embodiments, "connected" may be a direct connection.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (10)

1. A pixel driving circuit comprising:
a light emitting unit having a first end and a second end, the first end of the light emitting unit being connected to a first operating voltage;
a first switch having a first end, a second end and a control end, wherein the first end of the first switch is connected to the second end of the light-emitting unit, and the second end of the first switch is connected to a second operating voltage;
a second switch having a first end, a second end and a control end, wherein the first end of the second switch is connected to the control end of the first switch, and the second end of the second switch is connected to a reference voltage;
a first capacitor having a first end and a second end, the first end of the first capacitor being connected to the control end of the first switch and the first end of the second switch;
a third switch having a first end, a second end and a control end, wherein the first end of the third switch is connected to the second operating voltage, and the control end of the third switch is connected to the control end of the second switch;
a fourth switch having a first end, a second end and a control end, wherein the first end of the fourth switch is connected to the second end of the first capacitor and the second end of the third switch, the second end of the fourth switch is connected to the first control signal, and the control end of the fourth switch is connected to a first voltage;
a fifth switch having a first end, a second end and a control end, the first end of the fifth switch being connected to the second voltage, the second end of the fifth switch being connected to the control end of the second switch and the control end of the third switch, the control end of the fifth switch being connected to a second control signal;
a sixth switch having a first end, a second end, and a control end, the first end of the sixth switch being connected to the control end of the second switch, the control end of the third switch, and the second end of the fifth switch, the control end of the sixth switch being connected to a third control signal;
a seventh switch having a first end, a second end and a control end, wherein the first end of the seventh switch is connected to the second end of the sixth switch, and the control end of the seventh switch is connected to a fourth control signal;
an eighth switch having a first end, a second end, and a control end, wherein the first end of the eighth switch is connected to the second end of the seventh switch, the second end of the eighth switch is connected to the first control signal, and the control end of the eighth switch is connected to the reference voltage;
a second capacitor having a first end and a second end, the first end of the second capacitor being connected to the second end of the sixth switch and the first end of the seventh switch;
a ninth switch having a first end, a second end and a control end, wherein the first end of the ninth switch is connected to the second end of the second capacitor, the second end of the ninth switch is connected to a data voltage, and the control end of the ninth switch is connected to the fourth control signal; and
a tenth switch having a first end, a second end and a control end, wherein the first end of the tenth switch is connected to the second end of the second capacitor and the first end of the ninth switch, the second end of the tenth switch is connected to the first voltage, and the control end of the tenth switch is connected to the second control signal.
2. The pixel driving circuit according to claim 1, wherein the pixel driving circuit operates in a first period, a second period, a third period and a fourth period sequentially,
wherein during the first period, the first switch, the third switch, the sixth switch and the tenth switch are in an off state, the second switch, the fourth switch, the fifth switch, the seventh switch, the eighth switch and the ninth switch are in an on state,
wherein in the second period, the first switch, the third switch, the sixth switch and the tenth switch are in the off state, the second switch, the fourth switch, the fifth switch, the seventh switch, the eighth switch and the ninth switch are in the on state,
wherein in a first sub-period of the third period, the first switch, the third switch, the fifth switch, the sixth switch, the seventh switch and the ninth switch are in the off state, the second switch, the fourth switch, the eighth switch and the tenth switch are in the on state,
wherein in a second sub-period of the third period, the second switch, the fourth switch, the fifth switch, the seventh switch and the ninth switch are in the off state, the first switch, the third switch, the sixth switch, the eighth switch and the tenth switch are in the on state,
during the fourth period, the first switch, the third switch, the fourth switch, the sixth switch, the seventh switch, the ninth switch and the tenth switch are in the off state, and the second switch, the fifth switch and the eighth switch are in the on state.
3. The pixel driving circuit as claimed in claim 2, wherein the third switch, the fifth switch, the seventh switch and the ninth switch are P-type transistors, and the first switch, the second switch, the fourth switch, the sixth switch, the eighth switch and the tenth switch are N-type transistors.
4. The pixel driving circuit according to claim 3, wherein the threshold voltage of the first switch is matched to the threshold voltage of the fourth switch, and the threshold voltage of the sixth switch is matched to the threshold voltage of the eighth switch.
5. The pixel driving circuit according to claim 3, wherein during the first period, the first control signal, the second control signal and the fourth control signal are at a first low level, the third control signal is at a second low level,
wherein during the second period, the first control signal is at a first high level, the second control signal and the fourth control signal are at a first low level, the third control signal is at a second low level,
wherein during the third period, the first control signal, the second control signal and the fourth control signal are at the first high level, the third control signal is gradually increased from the second low level to a second high level,
in the fourth period, the first control signal and the fourth control signal are at the first high level, the second control signal is at the first low level, and the third control signal is at the second low level.
6. A pixel driving circuit as claimed in claim 5, wherein the first operating voltage is greater than the second operating voltage, the first voltage being less than the second voltage.
7. The pixel driving circuit as claimed in claim 1, wherein the light emitting unit is a light emitting diode.
8. A pixel driving circuit as claimed in claim 7, wherein the size of the light emitting diode is sub-millimeter.
9. The pixel driving circuit according to claim 1, wherein the pixel driving circuit is disposed in a display panel.
10. The pixel driving circuit as claimed in claim 1, wherein the pixel driving circuit is disposed in a backlight module.
CN202110386028.3A 2020-06-10 2021-04-09 Pixel driving circuit Active CN113077752B (en)

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