CN113066862B - 一种集成mos自适应控制soi ligbt - Google Patents

一种集成mos自适应控制soi ligbt Download PDF

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CN113066862B
CN113066862B CN202110317574.1A CN202110317574A CN113066862B CN 113066862 B CN113066862 B CN 113066862B CN 202110317574 A CN202110317574 A CN 202110317574A CN 113066862 B CN113066862 B CN 113066862B
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罗小蓉
苏伟
马臻
张森
杨可萌
魏杰
樊雕
王晨霞
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University of Electronic Science and Technology of China
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    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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Abstract

本发明属于功率半导体技术领域，涉及一种集成MOS自适应控制SOI LIGBT。本发明的主要特征在于：在SOI LIGBT阴极侧集成3个MOS管，且通过氧化隔离槽互相隔离。MOS管通过电气连接可实现自适应控制SOI LIGBT。正向导通时，集成MOS自适应控制SOI LIGBT寄生二极管开启，增强电导调制效应，降低器件导通压降，增加器件饱和电流；关断过程中，集成MOS自适应辅助耗尽漂移区且提供额外的空穴抽取通道，有效降低关断损耗；短路状态下，集成MOS自适应控制SOI LIGBT寄生二极管截止，抑制闩锁效应，提高器件的抗短路能力。本发明的有益效果为，相对于传统SOI LIGBT结构，本发明具有更低的导通压降、更低的关断损耗、更高的饱和电流以及更长的短路耐受时间。

Description

一种集成MOS自适应控制SOI LIGBT
技术领域
本发明属于功率半导体技术领域，涉及一种集成MOS自适应控制SOI LIGBT(Lateral Insulated Gate Bipolar Transistor，横向绝缘栅双极型晶体管)。
背景技术
IGBT作为电子电力器件的典型代表，既有MOSFET的输入阻抗高、栅控能力好以及驱动电路简单的好处，同时又具有BJT的高电流密度、低导通压降以及强电流处理能力的优点，目前已被广泛应用于高铁，电网，智能家电以及新能源汽车等领域。SOI基LIGBT由于采用介质隔离，其具有泄漏电流小，寄生电容小，抗辐照能力强的优势。此外，横向IGBT(LIGBT)便于集成，促使SOI LIGBT成为单片功率集成芯片的核心元器件。
IGBT低导通压降得益于导通时漂移区内的电导调制效应。然而关断时，阳极区的电子势垒迫使存储在漂移区的载流子通过复合消失，导致其关断速度减慢，关断损耗增加，限制IGBT的高频应用。因此，导通压降和关断损耗的矛盾仍是IGBT的基本问题。缓解二者矛盾关系的典型技术有以下三种。其一，寿命控制技术可使漂移区内的载流子复合速度变快，减小器件关断损耗。然而，此种技术亦会使器件导通时漂移区内非平衡载流子浓度减小，导通压降上升。其二，在阴极端引入具有空穴阻挡作用的存储层，使靠近阴极端一侧的漂移区载流子浓度升高，减小导通压降，但其非平衡载流子仍需通过复合消失，关断速度依旧较慢。其三，短路阳极技术可加快载流子抽取，获得导通压降和关断损耗的良好折衷。但短路阳极结构带来的snapback效应会影响电流分布的均匀性，不利于器件并联应用。
此外，IGBT由于工作在饱和区的强电流能力，会在短路发生时的高压大电流状态下产生大的功耗，使其有发生闩锁、提前热击穿甚至失效的风险，因此IGBT的高饱和电流与短路时间的矛盾关系也是IGBT需要解决的问题。缓解二者的矛盾关系的典型技术有以下两种。其一，在阴极端引入高掺杂的P型埋层使与阴极寄生二极管并联的等效电阻值降低，抑制寄生二极管开启从而抑制闩锁。然而当IGBT电导调制效应较强时，该技术依然有发生闩锁的风险。其二，在阴极端引入空穴旁路，抽取阴极附近的空穴使电导调制效应被削弱，降低饱和电流，从而降低器件在发生短路时的功耗，提高短路能力。由于该技术削弱了器件导通时的电导调制效应，又会使器件的导通压降升高。
为此，本发明提出一种集成MOS自适应控制SOI LIGBT，实现低泄漏电流，低导通压降，高饱和电流以及长短路耐受时间。
发明内容
本发明针对上述问题提出一种集成MOS自适应控制SOI LIGBT。
本发明的技术方案是：
一种集成MOS自适应控制SOI LIGBT，包括自下而上依次层叠设置的P衬底1、埋氧层2和顶部半导体层；所述的顶部半导体层具有N型掺杂，沿器件横向方向，所述的顶部半导体层上层两端具有P阱区5和N型缓冲层4，在P阱区5和N型缓冲层4之间的N型半导体为N漂移区3；N型缓冲层4的上层具有P+阳极区6，所述P+阳极区6的引出端为阳极；在P阱区5上层靠近N型缓冲层4的方向依次具有集成MOS结构、并列设置的P+区8和N+区7、第四P+体接触区23，且集成MOS结构和P+区8之间通过第一介质隔离槽11隔离，P+区8与第一介质隔离槽11接触；在N+区7和第四P+体接触区23之间具有LIGBT槽栅结构9；所述槽栅结构9从表面沿器件垂直方向向下穿过P阱区5至N漂移区3中；所述槽栅结构9侧面靠近N型缓冲层4一侧与第四P+体接触区23、P阱区5和N漂移区3接触，另一侧与N+区7、P阱区5和N漂移区3接触；
其特征在于，所述集成MOS结构包括第一MOS、第二MOS和第三MOS；所述第一MOS与P+区8通过第一介质隔离槽11隔离，第一MOS和第二MOS通过第二介质隔离槽17隔离，第二MOS和第三MOS通过第三介质隔离槽24隔离，且第一介质隔离槽11、第二介质隔离槽17和第三介质隔离槽24从表面沿器件垂直方向向下贯穿P阱区5和N漂移区3后与埋氧层2接触；所述第一MOS/第二MOS/第三MOS并列位于P阱区5上层，包括第一N+漏区12/第二N+漏区18/第三N+漏区25、第一N+源区13/第二N+源区19/第三N+源区26、第一P+体接触区14/第二P+体接触区20/第三P+体接触区27、第一N+漏区12/第二N+漏区18/第三N+漏区25和第一N+源区13/第二N+源区19/第三N+源区26之间P阱区5上方的第一平面栅10/第二平面栅15/第三平面栅16；
所述第一N+漏区12和第一P+体接触区14位于第一介质隔离槽11和第二介质隔离槽17之间的P阱区5上层两端；所述第二N+漏区18和第二P+体接触区20位于第二介质隔离槽17和第三介质隔离槽24之间的P阱区5上层两端；所述第三N+漏区25和第三P+体接触区27位于第三介质隔离槽24远离第二介质隔离槽17一侧的P阱区5上层两端；所述第一N+漏区12/第二N+漏区18/第三N+漏区25与第一介质隔离槽11/第二介质隔离槽17/第三介质隔离槽24接触；所述第一N+源区13与第一P+体接触区14、第二N+源区19与第二P+体接触区20、第三N+源区26于第三P+体接触区27并列设置；
所述槽栅结构9和第三平面栅16的共同引出端为栅极；所述第一N+源区13、第二N+源区19、第二P+体接触区20、第三N+源区26、第三P+体接触区27的共同引出端为阴极；所述N+区7、第一P+体接触区14和第三N+漏区25的引出端用浮空欧姆接触连接；所述P+区8、第一N+漏区12和第一平面栅10的引出端用浮空欧姆接触连接；所述第四P+体接触区23、第二N+漏区18和第二平面栅15的引出端用浮空欧姆接触连接。
本发明的有益效果为，相比于传统的SOI LIGBT，本发明有效缓解了Von～Eoff矛盾关系，可实现更低的正向导通压降，更低的关断损耗，更高的正向饱和电流，更长的短路耐受时间，且能与功率集成电路的高低压器件工艺兼容，制备成本低。
附图说明
图1为本发明提出的实施例1元胞结构示意图；
具体实施方式
下面结合附图和实施例，详细描述本发明的技术方案：
实施例1
如图1所示，本例的结构包括一种集成MOS自适应控制SOI LIGBT，包括自下而上依次层叠设置的P衬底1、埋氧层2和顶部半导体层；所述的顶部半导体层具有N型掺杂，沿器件横向方向，所述的顶部半导体层上层两端具有P阱区5和N型缓冲层4，在P阱区5和N型缓冲层4之间的N型半导体为N漂移区3；N型缓冲层4的上层具有P+阳极区6，所述P+阳极区6的引出端为阳极；在P阱区5上层靠近N型缓冲层4的方向依次具有集成MOS结构、并列设置的P+区8和N+区7、第四P+体接触区23，且集成MOS结构和P+区8之间通过第一介质隔离槽11隔离，P+区8与第一介质隔离槽11接触；在N+区7和第四P+体接触区23之间具有LIGBT槽栅结构9；所述槽栅结构9从表面沿器件垂直方向向下穿过P阱区5至N漂移区3中；所述槽栅结构9侧面靠近N型缓冲层4一侧与第四P+体接触区23、P阱区5和N漂移区3接触，另一侧与N+区7、P阱区5和N漂移区3接触；
其特征在于，所述集成MOS结构包括第一MOS、第二MOS和第三MOS；所述第一MOS与P+区8通过第一介质隔离槽11隔离，第一MOS和第二MOS通过第二介质隔离槽17隔离，第二MOS和第三MOS通过第三介质隔离槽24隔离，且第一介质隔离槽11、第二介质隔离槽17和第三介质隔离槽24从表面沿器件垂直方向向下贯穿P阱区5和N漂移区3后与埋氧层2接触；所述第一MOS/第二MOS/第三MOS并列位于P阱区5上层，包括第一N+漏区12/第二N+漏区18/第三N+漏区25、第一N+源区13/第二N+源区19/第三N+源区26、第一P+体接触区14/第二P+体接触区20/第三P+体接触区27、第一N+漏区12/第二N+漏区18/第三N+漏区25和第一N+源区13/第二N+源区19/第三N+源区26之间P阱区5上方的第一平面栅10/第二平面栅15/第三平面栅16；
所述第一N+漏区12和第一P+体接触区14位于第一介质隔离槽11和第二介质隔离槽17之间的P阱区5上层两端；所述第二N+漏区18和第二P+体接触区20位于第二介质隔离槽17和第三介质隔离槽24之间的P阱区5上层两端；所述第三N+漏区25和第三P+体接触区27位于第三介质隔离槽24远离第二介质隔离槽17一侧的P阱区5上层两端；所述第一N+漏区12/第二N+漏区18/第三N+漏区25与第一介质隔离槽11/第二介质隔离槽17/第三介质隔离槽24接触；所述第一N+源区13与第一P+体接触区14、第二N+源区19与第二P+体接触区20、第三N+源区26于第三P+体接触区27并列设置；
所述槽栅结构9和第三平面栅16的共同引出端为栅极；所述第一N+源区13、第二N+源区19、第二P+体接触区20、第三N+源区26、第三P+体接触区27的共同引出端为阴极；所述N+区7、第一P+体接触区14和第三N+漏区25的引出端用浮空欧姆接触连接；所述P+区8、第一N+漏区12和第一平面栅10的引出端用浮空欧姆接触连接；所述第四P+体接触区23、第二N+漏区18和第二平面栅15的引出端用浮空欧姆接触连接。
本例的工作原理为：
本例所示的器件采用集成MOS自适应控制SOI LIGBT。正向导通时，集成MOS自适应控制SOI LIGBT寄生二极管开启，增强电导调制效应，有效降低器件的导通压降，增加器件的饱和电流，提高器件的驱动能力；正向关断时，集成MOS自适应控制SOI LIGBT槽栅靠近阳极一侧的P阱区辅助耗尽漂移区，且提供一条额外的空穴抽取通道，有效降低关断损耗，缓解Von～Eoff矛盾关系；短路状态下，集成MOS自适应控制SOI LIGBT寄生二极管截止，抑制闩锁效应，提高器件的抗短路能力。

Claims (1)

1.一种集成MOS自适应控制SOI LIGBT，包括自下而上依次层叠设置的P衬底(1)、埋氧层(2)和顶部半导体层；所述的顶部半导体层具有N型掺杂，沿器件横向方向，所述的顶部半导体层上层两端具有P阱区(5)和N型缓冲层(4)，在P阱区(5)和N型缓冲层(4)之间的N型半导体为N漂移区(3)；N型缓冲层(4)的上层具有P+阳极区(6)，所述P+阳极区(6)的引出端为阳极；在P阱区(5)上层靠近N型缓冲层(4)的方向依次具有集成MOS结构、并列设置的P+区(8)和N+区(7)、第四P+体接触区(23)，且集成MOS结构和P+区(8)之间通过第一介质隔离槽(11)隔离，P+区(8)与第一介质隔离槽(11)接触；在N+区(7)和第四P+体接触区(23)之间具有LIGBT槽栅结构(9)；所述槽栅结构(9)从表面沿器件垂直方向向下穿过P阱区(5)至N漂移区(3)中；所述槽栅结构(9)侧面靠近N型缓冲层(4)一侧与第四P+体接触区(23)、P阱区(5)和N漂移区(3)接触，另一侧与N+区(7)、P阱区(5)和N漂移区(3)接触；
其特征在于，所述集成MOS结构包括第一MOS、第二MOS和第三MOS；所述第一MOS与P+区(8)通过第一介质隔离槽(11)隔离，第一MOS和第二MOS通过第二介质隔离槽(17)隔离，第二MOS和第三MOS通过第三介质隔离槽(24)隔离，且第一介质隔离槽(11)、第二介质隔离槽(17)和第三介质隔离槽(24)从表面沿器件垂直方向向下贯穿P阱区(5)和N漂移区(3)后与埋氧层(2)接触；所述第一MOS、第二MOS和第三MOS并列位于P阱区(5)上层，第一MOS包括第一N+漏区(12)、第一N+源区(13)、第一P+体接触区(14)、第一N+漏区(12)和第一N+源区(13)之间P阱区(5)上方的第一平面栅(10)；第二MOS包括第二N+漏区(18)、第二N+源区(19)、第二P+体接触区(20)、第二N+漏区(18)和第二N+源区(19)之间P阱区 (5)上方的第二平面栅(15)，第三MOS包括第三N+漏区(25)、第三N+源区(26)、第三P+体接触区(27)、第三N+漏区(25)和第三N+源区(26)之间P阱区 (5)上方的第三平面栅(16)；所述第一N+漏区(12)和第一P+体接触区(14)位于第一介质隔离槽(11)和第二介质隔离槽(17)之间的P阱区(5)上层两端；所述第二N+漏区(18)和第二P+体接触区(20)位于第二介质隔离槽(17)和第三介质隔离槽(24)之间的P阱区(5)上层两端；所述第三N+漏区(25)和第三P+体接触区(27)位于第三介质隔离槽(24)远离第二介质隔离槽(17)一侧的P阱区(5)上层两端；所述第一N+漏区(12)与第一介质隔离槽(11)接触，所述第二N+漏区(18)与第二介质隔离槽(17)接触，所述第三N+漏区(25)与第三介质隔离槽(24)接触；所述第一N+源区(13)与第一P+体接触区(14)、第二N+源区(19)与第二P+体接触区(20)、第三N+源区(26)于第三P+体接触区(27)并列设置；
所述槽栅结构(9)和第三平面栅(16)的共同引出端为栅极；所述第一N+源区(13)、第二N+源区(19)、第二P+体接触区(20)、第三N+源区(26)、第三P+体接触区(27)的共同引出端为阴极；所述N+区(7)、第一P+体接触区(14)和第三N+漏区(25)的引出端用浮空欧姆接触连接；所述P+区(8)、第一N+漏区(12)和第一平面栅(10)的引出端用浮空欧姆接触连接；所述第四P+体接触区(23)、第二N+漏区(18)和第二平面栅(15)的引出端用浮空欧姆接触连接。
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