CN113066799A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN113066799A CN113066799A CN202110281808.1A CN202110281808A CN113066799A CN 113066799 A CN113066799 A CN 113066799A CN 202110281808 A CN202110281808 A CN 202110281808A CN 113066799 A CN113066799 A CN 113066799A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims description 12
- 239000004020 conductor Substances 0.000 claims abstract description 110
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 239000002184 metal Substances 0.000 abstract description 15
- 229910052751 metal Inorganic materials 0.000 abstract description 15
- 230000009897 systematic effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 230000000750 progressive effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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Abstract
The application discloses a semiconductor device and a manufacturing method thereof, the semiconductor device comprises: the first conductor layer comprises at least one first routing wire; the second conductor layer comprises at least one second routing wire; the first wire is in cross contact with the second wire; the insulating layer is positioned on one side, away from the first conductor layer, of the second conductor layer; the through hole penetrates through the insulating layer, and the through hole is arranged at least one intersection position of the first routing and the second routing; and the third conductor layer is positioned on one side of the insulating layer, which is deviated from the first conductor layer and the second conductor layer. According to the scheme of the invention, through arranging the through holes at least at one crossing position of the first routing and the second routing and uniformly distributing the rest through holes as much as possible, the connectivity of the metal on the same layer can be increased, and the reliability is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a manufacturing method thereof.
Background
With the rapid advances in semiconductor processing capabilities, high performance new process device designs are becoming more and more numerous. As the process is getting smaller and smaller, the nanometer-scale error may cause the device performance to have large fluctuation, even the device fails to be produced. Because the manufacturing plant systematic error and random error always exist, the situation that the circuit break occurs between the metals of the same layer can be caused frequently, and the connection reliability is poor.
Disclosure of Invention
In view of this, the present invention provides a semiconductor device and a method for manufacturing the same, which can increase the connectivity of the metal in the same layer and improve the reliability.
In order to achieve the above purpose, the invention provides the following technical scheme:
a semiconductor device, the semiconductor device comprising:
the first conductor layer comprises at least one first routing wire;
the second conductor layer comprises at least one second routing wire; the first wire is in cross contact with the second wire;
the insulating layer is positioned on one side, away from the first conductor layer, of the second conductor layer;
the through hole penetrates through the insulating layer, and the through hole is arranged at least one intersection position of the first routing and the second routing;
a third conductor layer on a side of the insulating layer facing away from the first and second conductor layers;
the third conductor layer is connected with the first wire and the second wire through the through hole.
Preferably, in the above semiconductor device, there are a plurality of the crossing positions, and at least one of the through holes is provided at each of the crossing positions.
Preferably, in the semiconductor device described above, the through holes are all located on the first wiring;
the through holes on the same first routing line are uniformly distributed.
Preferably, in the above semiconductor device, the through holes are all located on the second routing line;
the through holes on the same second routing line are uniformly distributed.
Preferably, in the semiconductor device described above, a part of the through holes is located on the first wiring, and another part of the through holes is located on the second wiring;
the through holes on the same first routing are uniformly distributed;
the through holes on the same second routing line are uniformly distributed.
Preferably, in the above semiconductor device, there is at least one first trace;
the second routing lines are arranged in parallel;
wherein the first trace crosses all the second traces.
Preferably, in the above semiconductor device, each of the crossing positions has one of the through holes; n through holes are formed between a first crossing position and a second crossing position which are adjacent in a first direction, and the first direction is the extending direction of the first routing;
N＝floor((S+En1+En2-smin)/(smin+w))
s0＝(S+En1+En2–N*w)/(N+1)
wherein smin is the minimum design distance of two adjacent through holes in the first direction; w is the width of the through hole in the first direction; s is the line spacing between two adjacent second wires; the through hole at the first intersection location has a distance En1 from the edge of the first intersection location towards the second intersection location; the through hole at the second intersection location has a distance En2 from the edge of the second intersection location towards the first intersection location; s0 is the actual spacing of the two vias.
Preferably, in the above semiconductor device, there is at least one second trace;
the first routing lines are arranged in parallel;
wherein the second trace crosses all the first traces.
Preferably, in the above semiconductor device, each of the crossing positions has one of the through holes; m through holes are formed between a third crossing position and a fourth crossing position which are adjacent to each other in a second direction, and the second direction is the extending direction of the second routing;
M＝floor((S’+En1’+En2’-smin’)/(smin’+w’))
s0’＝(S’+En1’+En2’–M*w’)/(M+1)
wherein smin' is the minimum design distance of two adjacent through holes in the second direction; w' is the width of the through hole in the second direction; s' is the line spacing between two adjacent first wires; the via at the fourth intersection location is a distance En 1' from the edge of the third intersection location towards the fourth intersection location; the via at the fourth intersection location has a distance En 2' from the edge of the fourth intersection location towards the third intersection location; s 0' is the actual spacing of the two vias.
The invention also provides a manufacturing method of the semiconductor device, which comprises the following steps:
forming a first conductor layer, wherein the first conductor layer comprises at least one first routing wire;
forming a second conductor layer, wherein the second conductor layer comprises at least one second routing wire; the first wire is in cross contact with the second wire;
forming an insulating layer on one side, away from the first conductor layer, of the second conductor layer;
forming a through hole penetrating through the insulating layer, wherein the through hole is formed in at least one crossed position of the first routing and the second routing;
forming a third conductor layer on one side of the insulating layer, which is far away from the first conductor layer and the second conductor layer;
the third conductor layer is connected with the first wire and the second wire through the through hole.
As can be seen from the above description, in the semiconductor device and the manufacturing method thereof provided in the technical solution of the present invention, the through holes are disposed at least one intersection position of the first trace and the second trace, and the connection property of the metal on the same layer can be increased and the reliability can be improved by calculating the through hole distance and the number of the through holes between the two conductor layers and uniformly distributing the rest through holes as much as possible.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
The structures, proportions, and dimensions shown in the drawings and described in the specification are for illustrative purposes only and are not intended to limit the scope of the present disclosure, which is defined by the claims, but rather by the claims, it is understood that these drawings and their equivalents are merely illustrative and not intended to limit the scope of the present disclosure.
FIG. 1 is a top view of a conventional semiconductor device;
fig. 2 is a top view of another conventional semiconductor device;
FIG. 3a is a cross-sectional view of a conventional semiconductor device in which a circuit break occurs;
FIG. 3b is a schematic diagram of a second conductor layer having a disconnection problem in a conventional semiconductor device;
fig. 4 is a top view of a semiconductor device according to an embodiment of the present invention;
fig. 5 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention;
fig. 6 is a top view of another semiconductor device provided in accordance with an embodiment of the present invention;
fig. 7 is a top view of a further semiconductor device provided in accordance with an embodiment of the present invention;
fig. 8 is a top view of yet another semiconductor device provided in accordance with an embodiment of the present invention;
fig. 9 is a top view of yet another semiconductor device provided in accordance with an embodiment of the present invention;
fig. 10 is a top view of yet another semiconductor device provided in accordance with an embodiment of the present invention;
fig. 11 is a top view of a further semiconductor device provided in accordance with an embodiment of the present invention;
fig. 12 is a top view of yet another semiconductor device provided in accordance with an embodiment of the present invention;
fig. 13 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown, and in which it is to be understood that the embodiments described are merely illustrative of some, but not all, of the embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
With the rapid advances in semiconductor processing capabilities, high performance new process device designs are becoming more and more numerous. As the process is getting smaller and smaller, the nanometer-scale error may cause the device performance to have large fluctuation, even the device fails to be produced. Because the systematic error and the random error of the manufacturing plant always exist, the design of the through hole connection and the through hole distribution which can reduce the systematic error and the random error can greatly reduce the proportion of tape-out failure and improve the yield of the manufacturing plant.
In the prior art, without considering the connection relationship of the same metal layer, only through holes are uniformly distributed on a single metal layer as many as possible, and the upper and lower metal layers are connected, as shown in fig. 1 and 2, fig. 1 is a top view of a conventional semiconductor device, and fig. 2 is a top view of another conventional semiconductor device. In this method, the through holes are uniformly distributed as many as possible only according to the rule of the first conductor layer 01, and the connection reliability at the intersection of the first conductor layer 01 and the second conductor layer 02 is not considered. The first conductor layer 01 and the second conductor layer 02 are two conductor layers on the same layer, and the two conductor layers are prepared through different process steps.
In the manner of fig. 1 and 2, this has the advantage that: the first conductor layer 01 and the second conductor layer 02 which are in the same layer are connected reliably by default, and are not disconnected during manufacturing, so that the design is facilitated, and the difficulty in developing and drawing a layout is reduced. However, such disadvantages are: if the connection between the first conductive layer 01 and the second conductive layer 02 is unreliable and a circuit break occurs due to the existence of a systematic error or a random error, there is a high probability that the design of the whole chip will fail.
As shown in fig. 3a, fig. 3a is a schematic structural diagram of a conventional semiconductor device when a circuit is broken at a crossing position of two conductor layers, in this way, due to the existence of systematic errors or random errors, the connection relationship between the first conductor layer 01 and the second conductor layer 02 at the crossing position is unreliable and a circuit is broken, a region 05 is a broken range of the first conductor layer 01 and the second conductor layer 02 at the crossing position, and if a through hole 04 is just above one first conductor layer 01, an open circuit phenomenon occurs between the through hole 04 and the second conductor layer 02.
As shown in fig. 3b, fig. 3b is a schematic diagram illustrating a problem of open circuit of the second conductor layer 02 in the conventional semiconductor device, in which the second conductor layer 02 is open circuit due to the existence of systematic error or random error, and the conventional punching method may cause an open circuit between the via 04 and the second conductor layer 02.
In order to solve the problems, the present application designs a semiconductor device and a manufacturing method thereof, which can reduce the via connection and via distribution due to systematic errors and random errors, and can greatly reduce the proportion of tape-out failure and improve the yield of a factory. The semiconductor device includes:
the first conductor layer comprises at least one first routing wire;
the second conductor layer comprises at least one second routing wire; the first wire is in cross contact with the second wire;
the insulating layer is positioned on one side, away from the first conductor layer, of the second conductor layer;
the through hole penetrates through the insulating layer, and the through hole is arranged at least one intersection position of the first routing and the second routing;
a third conductor layer on a side of the insulating layer facing away from the first and second conductor layers; the third conductor layer is connected with the first wire and the second wire through the through hole.
Aiming at the problem that when the first conductor layer and the second conductor layer are disconnected in the prior art, the distributed through holes can increase the connectivity of the same layer of metal (the first conductor layer and the second conductor layer); when the first conductor layer or the second conductor layer is broken in the prior art, the upper metal layer can still be connected with other devices connected with the upper metal layer in series through the through holes, and the connection reliability is improved.
As can be seen from the above description, in the semiconductor device and the manufacturing method thereof provided in the technical solution of the present invention, the through holes are disposed at least one intersection position of the first trace and the second trace, and the connection property of the metal on the same layer can be increased and the reliability can be improved by calculating the through hole distance and the number of the through holes between the two conductor layers and uniformly distributing the rest through holes as much as possible. And the system error and the random error can be reduced, the proportion of tape-out failure can be greatly reduced, and the yield of a factory is improved.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.
Referring to fig. 4 and 5, fig. 4 is a top view of a semiconductor device according to an embodiment of the present invention, and fig. 5 is a cross-sectional view of the semiconductor device according to the embodiment of the present invention.
As shown in fig. 4 and 5, the semiconductor device includes:
a first conductor layer 11, wherein the first conductor layer 11 includes at least one first trace;
a second conductor layer 12, wherein the second conductor layer 12 includes at least one second trace; the first wire is in cross contact with the second wire;
an insulating layer 15, wherein the insulating layer 15 is located on a side of the second conductor layer 12 facing away from the first conductor layer 11;
a through hole 14, wherein the through hole 14 penetrates through the insulating layer 15, and the through hole 14 is arranged at least one intersection position of the first trace and the second trace;
a third conductor layer 13, wherein the third conductor layer 13 is located on a side of the insulating layer 15 away from the first conductor layer 11 and the second conductor layer 12;
wherein the third conductor layer 13 is connected to the first trace and the second trace through the through hole 14.
The first conductor layer 11, the second conductor layer 12, and the third conductor layer 13 are not particularly limited to metal materials, and may be any conductor material, and the first conductor layer 11 may be the same as or different from the second conductor layer 12.
In the scheme, through arranging the through holes 14 at least one cross position of the first routing wire and the second routing wire and uniformly distributing the rest through holes 14 as much as possible, the connectivity of the metal on the same layer can be increased, and the reliability is improved.
In the semiconductor device provided by the embodiment of the present invention, the first trace and the second trace have a plurality of crossing positions, and each crossing position is provided with at least one through hole 14.
In one form, the crossover location may have a through hole 14, as shown in figure 4.
In another mode, as shown in fig. 6, fig. 6 is a top view of another semiconductor device provided in the embodiment of the present invention, and the crossing position may have 2 through holes.
In another mode, as shown in fig. 7, fig. 7 is a top view of another semiconductor device provided in the embodiment of the present invention, and there may be 3 through holes at the crossing positions.
In the embodiment of the present invention, the number of the through holes at the intersection position may be set based on a requirement, without being limited to the illustrated manner.
In the embodiment of the present invention, the arrangement manner of the through holes 14 may be uniformly distributed on the first routing line according to the rule of the first conductor layer 11, may also be uniformly distributed on the second routing line according to the rule of the second conductor layer 12, and may also be that a part of the through holes 14 are uniformly distributed on the first routing line and a part of the through holes 14 are uniformly distributed on the second routing line.
As shown in fig. 8, fig. 8 is a top view of another semiconductor device according to an embodiment of the present invention, where the through holes 14 are all located on the first trace; the through holes 14 on the same first trace are uniformly distributed.
As shown in fig. 9, fig. 9 is a top view of another semiconductor device provided in the embodiment of the present invention, where the through holes 14 are all located on the second routing line; the through holes 14 on the same second trace are uniformly distributed.
As shown in fig. 10, fig. 10 is a top view of another semiconductor device according to an embodiment of the present invention, in which a portion of the through holes 14 is located on the first trace, and another portion of the through holes 14 is located on the second trace; the through holes 14 on the same first trace are uniformly distributed; the through holes 14 on the same second trace are uniformly distributed.
Referring to fig. 11, fig. 11 is a top view of another semiconductor device according to an embodiment of the invention, which has at least one first trace; the second routing lines are arranged in parallel; wherein the first trace crosses all the second traces. It should be noted that, when there are a plurality of first wires, all the first wires are arranged in parallel.
Furthermore, the crossing positions are provided with one through hole 14; n through holes 14 are formed between adjacent first crossing positions and second crossing positions in a first direction, where the first direction is an extending direction of the first trace;
N＝floor((S+En1+En2-smin)/(smin+w))
s0＝(S+En1+En2–N*w)/(N+1)
where smin is the minimum design distance of two adjacent through holes 14 in the first direction, and smin is less than or equal to s 0; w is the width of the through hole 14 in the first direction; s is the line spacing between two adjacent second wires; the through hole 14 at the first crossing location has a distance En1 from the edge of the first crossing location towards the second crossing location; the through hole 14 at the second crossing location has a distance En2 from the edge of the second crossing location towards the first crossing location; s0 is the actual spacing of two vias 14.
N ═ floor (x) may be the largest positive integer not greater than x, such as floor (1.0) ═ 1, floor (1.5) ═ 1, and floor (2.3) ═ 2.
The number of the through holes 14 between the two second conductor layers 12 and the distance of the through holes 14 between the two second conductor layers 12 can be accurately calculated through the calculation mode of the arrangement of the through holes 14, the through holes 14 are arranged at least one cross position of the first routing and the second routing, and the rest through holes 14 are uniformly distributed as much as possible, so that the connectivity of the metal on the same layer is increased, and the reliability is improved.
Referring to fig. 12, fig. 12 is a top view of another semiconductor device according to an embodiment of the invention, which has at least one second trace; the first routing lines are arranged in parallel; wherein the second trace crosses all the first traces. It should be noted that, when a plurality of second routing lines are provided, all the second routing lines are arranged in parallel.
Furthermore, the crossing positions are provided with one through hole 14; m through holes 14 are formed between a third crossing position and a fourth crossing position which are adjacent to each other in a second direction, and the second direction is the extending direction of the second routing;
M＝floor((S’+En1’+En2’-smin’)/(smin’+w’))
s0’＝(S’+En1’+En2’–M*w’)/(M+1)
where smin' is the minimum design distance of two adjacent through holes 14 in the second direction; w' is the width of the through hole 14 in the second direction; s' is the line spacing between two adjacent first wires; the through hole 14 at the fourth crossing location has a distance En 1' from the edge of the third crossing location towards the fourth crossing location; the through hole 14 at the fourth crossing location has a distance En 2' from the side of the fourth crossing location facing the third crossing location; s 0' is the actual spacing of two vias 14.
Where M ═ floor (x) may take the largest positive integer no greater than x.
It should be noted that all the first traces are the same in width and are arranged at equal intervals, the second traces are the same in width and are arranged at equal intervals, and the through holes 14 at the intersection are preferably arranged in the middle area of the intersection, in other ways, individual traces may also be arranged at unequal intervals, and the through holes 14 at the intersection may be arranged at non-middle positions.
The number of the through holes 14 between the two first conductor layers 11 and the distance of the through holes 14 between the two first conductor layers 11 can be accurately calculated through the calculation mode of the arrangement of the through holes 14, the through holes 14 are arranged at least one cross position of the first routing and the second routing, and the rest through holes 14 are uniformly distributed as much as possible, so that the connectivity of the metal on the same layer is increased, and the reliability is improved.
Based on the foregoing embodiment, another embodiment of the present invention further provides a manufacturing method of the semiconductor device in the foregoing embodiment, as shown in fig. 13, where fig. 13 is a flowchart of a manufacturing method of the semiconductor device provided in the embodiment of the present invention, and the manufacturing method includes:
step S11: forming a first conductor layer, wherein the first conductor layer comprises at least one first routing wire;
step S12: forming a second conductor layer, wherein the second conductor layer comprises at least one second routing wire; the first wire is in cross contact with the second wire;
step S13: forming an insulating layer on one side, away from the first conductor layer, of the second conductor layer;
step S14: forming a through hole penetrating through the insulating layer, wherein the through hole is formed in at least one crossed position of the first routing and the second routing;
step S15: forming a third conductor layer on one side of the insulating layer, which is far away from the first conductor layer and the second conductor layer; the third conductor layer is connected with the first wire and the second wire through the through hole.
As can be seen from the above description, in the manufacturing method of the semiconductor device according to the technical solution of the present invention, the through holes are disposed at least one intersection position of the first trace and the second trace, and the through hole distance and the number of the through holes between the two conductor layers are calculated, and the remaining through holes are uniformly distributed as much as possible, so that the connectivity of the metal on the same layer is increased, and the reliability is improved. And the system error and the random error can be reduced, the proportion of tape-out failure can be greatly reduced, and the yield of a factory is improved.
The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other. The manufacturing method disclosed by the embodiment corresponds to the semiconductor device disclosed by the embodiment, so that the description is relatively simple, and the relevant points can be referred to the partial description of the semiconductor device.
It should be noted that in the description of the present application, it is to be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only used for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be configured and operated in a specific orientation, and thus, should not be construed as limiting the present application. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A semiconductor device, characterized in that the semiconductor device comprises:
the first conductor layer comprises at least one first routing wire;
the second conductor layer comprises at least one second routing wire; the first wire is in cross contact with the second wire;
the insulating layer is positioned on one side, away from the first conductor layer, of the second conductor layer;
the through hole penetrates through the insulating layer, and the through hole is arranged at least one intersection position of the first routing and the second routing;
a third conductor layer on a side of the insulating layer facing away from the first and second conductor layers;
the third conductor layer is connected with the first wire and the second wire through the through hole.
2. The semiconductor device of claim 1, wherein there are a plurality of said crossover locations, each having at least one said via disposed thereon.
3. The semiconductor device according to claim 2, wherein the vias are all located on the first wiring;
the through holes on the same first routing line are uniformly distributed.
4. The semiconductor device according to claim 2, wherein the vias are all located on the second wiring;
the through holes on the same second routing line are uniformly distributed.
5. The semiconductor device according to claim 2, wherein a part of the via hole is located on the first wiring, and another part of the via hole is located on the second wiring;
the through holes on the same first routing are uniformly distributed;
the through holes on the same second routing line are uniformly distributed.
6. The semiconductor device according to claim 1, wherein there is at least one of the first traces;
the second routing lines are arranged in parallel;
wherein the first trace crosses all the second traces.
7. The semiconductor device of claim 6, wherein each of said crossover locations has one of said vias; n through holes are formed between a first crossing position and a second crossing position which are adjacent in a first direction, and the first direction is the extending direction of the first routing;
N＝floor((S+En1+En2-smin)/(smin+w))
s0＝(S+En1+En2–N*w)/(N+1)
wherein smin is the minimum design distance of two adjacent through holes in the first direction; w is the width of the through hole in the first direction; s is the line spacing between two adjacent second wires; the through hole at the first intersection location has a distance En1 from the edge of the first intersection location towards the second intersection location; the through hole at the second intersection location has a distance En2 from the edge of the second intersection location towards the first intersection location; s0 is the actual spacing of the two vias.
8. The semiconductor device according to claim 1, wherein there is at least one of the second traces;
the first routing lines are arranged in parallel;
wherein the second trace crosses all the first traces.
9. The semiconductor device of claim 8, wherein each of said crossover locations has one of said vias; m through holes are formed between a third crossing position and a fourth crossing position which are adjacent to each other in a second direction, and the second direction is the extending direction of the second routing;
M＝floor((S’+En1’+En2’-smin’)/(smin’+w’))
s0’＝(S’+En1’+En2’–M*w’)/(M+1)
wherein smin' is the minimum design distance of two adjacent through holes in the second direction; w' is the width of the through hole in the second direction; s' is the line spacing between two adjacent first wires; the via at the fourth intersection location is a distance En 1' from the edge of the third intersection location towards the fourth intersection location; the via at the fourth intersection location has a distance En 2' from the edge of the fourth intersection location towards the third intersection location; s 0' is the actual spacing of the two vias.
10. A method of manufacturing a semiconductor device according to any of claims 1 to 9, the method comprising:
forming a first conductor layer, wherein the first conductor layer comprises at least one first routing wire;
forming a second conductor layer, wherein the second conductor layer comprises at least one second routing wire; the first wire is in cross contact with the second wire;
forming an insulating layer on one side, away from the first conductor layer, of the second conductor layer;
forming a through hole penetrating through the insulating layer, wherein the through hole is formed in at least one crossed position of the first routing and the second routing;
forming a third conductor layer on one side of the insulating layer, which is far away from the first conductor layer and the second conductor layer;
the third conductor layer is connected with the first wire and the second wire through the through hole.
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050199934A1 (en) * | 2002-10-22 | 2005-09-15 | Infineon Technologies Ag | Electronic component having an integrated passive electronic component and associated production method |
| US20130328208A1 (en) * | 2012-06-07 | 2013-12-12 | International Business Machines Corporation | Dual damascene dual alignment interconnect scheme |
| CN104319274A (en) * | 2014-11-14 | 2015-01-28 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate, display panel and display device |
| CN105679771A (en) * | 2016-01-29 | 2016-06-15 | 厦门天马微电子有限公司 | Array substrate and manufacturing method thereof and display panel comprising array substrate |
| CN106057774A (en) * | 2015-04-09 | 2016-10-26 | 三星电子株式会社 | Semiconductor device and method for manufacturing the same |
| CN206178742U (en) * | 2016-10-31 | 2017-05-17 | 上海中航光电子有限公司 | Display panel and display device |
| CN107680976A (en) * | 2017-10-30 | 2018-02-09 | 上海天马微电子有限公司 | A kind of array base palte, display panel and electronic equipment |
| CN108122833A (en) * | 2016-11-28 | 2018-06-05 | 台湾积体电路制造股份有限公司 | The method for making semiconductor device |
| US20190289718A1 (en) * | 2016-02-03 | 2019-09-19 | Fujitsu Limited | Capacitor built-in multilayer wiring substrate and manufacturing method thereof |
| CN110286789A (en) * | 2019-06-12 | 2019-09-27 | 武汉华星光电半导体显示技术有限公司 | Display panel and display module |
| CN112015299A (en) * | 2020-08-27 | 2020-12-01 | 合肥鑫晟光电科技有限公司 | Touch substrate and touch device |
| CN112255852A (en) * | 2020-10-23 | 2021-01-22 | 深圳市华星光电半导体显示技术有限公司 | Display device and light-emitting panel |
-
2021
- 2021-03-16 CN CN202110281808.1A patent/CN113066799B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050199934A1 (en) * | 2002-10-22 | 2005-09-15 | Infineon Technologies Ag | Electronic component having an integrated passive electronic component and associated production method |
| US20130328208A1 (en) * | 2012-06-07 | 2013-12-12 | International Business Machines Corporation | Dual damascene dual alignment interconnect scheme |
| CN104319274A (en) * | 2014-11-14 | 2015-01-28 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate, display panel and display device |
| CN106057774A (en) * | 2015-04-09 | 2016-10-26 | 三星电子株式会社 | Semiconductor device and method for manufacturing the same |
| CN105679771A (en) * | 2016-01-29 | 2016-06-15 | 厦门天马微电子有限公司 | Array substrate and manufacturing method thereof and display panel comprising array substrate |
| US20190289718A1 (en) * | 2016-02-03 | 2019-09-19 | Fujitsu Limited | Capacitor built-in multilayer wiring substrate and manufacturing method thereof |
| CN206178742U (en) * | 2016-10-31 | 2017-05-17 | 上海中航光电子有限公司 | Display panel and display device |
| CN108122833A (en) * | 2016-11-28 | 2018-06-05 | 台湾积体电路制造股份有限公司 | The method for making semiconductor device |
| CN107680976A (en) * | 2017-10-30 | 2018-02-09 | 上海天马微电子有限公司 | A kind of array base palte, display panel and electronic equipment |
| CN110286789A (en) * | 2019-06-12 | 2019-09-27 | 武汉华星光电半导体显示技术有限公司 | Display panel and display module |
| CN112015299A (en) * | 2020-08-27 | 2020-12-01 | 合肥鑫晟光电科技有限公司 | Touch substrate and touch device |
| CN112255852A (en) * | 2020-10-23 | 2021-01-22 | 深圳市华星光电半导体显示技术有限公司 | Display device and light-emitting panel |
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|---|---|
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