CN113066794B

CN113066794B - Memory cell and method for manufacturing the same

Info

Publication number: CN113066794B
Application number: CN202110286295.3A
Authority: CN
Inventors: 吴公一
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-03-17
Filing date: 2021-03-17
Publication date: 2022-06-24
Anticipated expiration: 2041-03-17
Also published as: CN113066794A

Abstract

The present disclosure provides a memory cell and a method of manufacturing the same, the memory cell including: the vertical transistor is partially arranged in the substrate and provided with a source electrode, a grid electrode and a drain electrode from bottom to top, the grid electrode is connected with a word line, and the source electrode is connected with a bit line; a storage contact structure comprising: the embedded part is positioned in the first groove, the side surface of the first groove is wrapped by the isolation structure, and the lower surface of the embedded part is connected with the drain electrode of the vertical transistor; the protruding part is positioned above the embedded part and connected with the upper surface of the embedded part, and the protruding part is of a columnar structure; the storage capacitor is provided with a lower pole plate, a dielectric layer and an upper pole plate, wherein the lower pole plate is attached to the side surface of the protruding portion, the dielectric layer is attached to the lower pole plate and the upper surface of the protruding portion, and the upper pole plate is attached to the dielectric layer. The memory cell structure can improve the structural strength and the arrangement density of the memory cells.

Description

Memory cell and method for manufacturing the same

Technical Field

The present disclosure relates to the field of integrated circuit manufacturing technologies, and in particular, to a memory cell and a method for manufacturing the same.

Background

With the development of the integrated circuit manufacturing process, the device size is smaller and the arrangement density is larger, which poses a great challenge to the manufacturing process.

In the DRAM manufacturing process, a vertical memory cell (composed of a vertical transistor and a vertical capacitor) becomes a new technology for increasing the number of memory cells per unit area. In the vertical storage unit, a source electrode, a grid electrode and a drain electrode of a transistor are sequentially arranged from bottom to top, a storage capacitor is positioned above the drain electrode of the transistor, and a lower polar plate of the capacitor is connected with the drain electrode of the transistor through a Storage Node Contact (SNC). Along with the reduction of the size of the transistor and the size of a channel, the connecting area between the source electrode of the vertical transistor and the lower electrode plate of the capacitor is smaller and smaller; along with the increase of the arrangement density, the distance between the vertical capacitors is closer and closer, the cross section is smaller and smaller, in order to keep the capacitance value unchanged or increase the capacitance value, the height of the vertical capacitors is higher and higher, the increased capacitors and the reduced connection area bring great challenges to the connection strength between the vertical capacitors and the source electrode, the stability of the vertical capacitors and the process reliability.

It is noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure and therefore may include information that does not constitute prior art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

An object of the present disclosure is to provide a memory cell and a method for fabricating the same, which overcome, at least to some extent, the problem of insufficient structural stability of vertical capacitance in a high density arrangement due to the limitations and disadvantages of the related art.

According to a first aspect of the present disclosure, there is provided a memory cell comprising: the vertical transistor is partially arranged in the substrate and provided with a source electrode, a grid electrode and a drain electrode from bottom to top, the grid electrode is connected with a word line, and the source electrode is connected with a bit line; a storage contact structure comprising: the embedded part is positioned in the first groove, the side surface of the first groove is wrapped by the isolation structure, and the lower surface of the embedded part is connected with the drain electrode of the vertical transistor; the protruding part is positioned above the embedded part and connected with the upper surface of the embedded part, and the protruding part is of a columnar structure; the storage capacitor is provided with a lower pole plate, a dielectric layer and an upper pole plate, wherein the lower pole plate is attached to the protruding part, the dielectric layer is attached to the lower pole plate, and the upper pole plate is attached to the dielectric layer.

In an exemplary embodiment of the present disclosure, an upper surface of the embedded portion is larger than a lower surface, and both upper and lower surfaces of the protruding portion are equal to the upper surface of the embedded portion.

In an exemplary embodiment of the present disclosure, the buried portion and the protruding portion are both made of a doped semiconductor, a kind of doping particles of the buried portion is not identical to a kind of doping particles of the protruding portion, and a doping concentration of the buried portion is not identical to a doping concentration of the protruding portion.

In an exemplary embodiment of the present disclosure, a portion of the isolation structure surrounds the drain of the vertical transistor and the buried portion of the storage contact structure, and another portion of the isolation structure is disposed between two adjacent word lines.

In an exemplary embodiment of the present disclosure, the isolation structure includes a plurality of sub-structures, the materials of the plurality of sub-structures not being identical.

In an exemplary embodiment of the present disclosure, the isolation structure includes: a first substructure having an upper portion, a middle portion and a lower portion connected in sequence, the upper portion connecting the lower plate of the storage capacitor and the dielectric layer and extending downward between two adjacent word lines, the middle portion surrounding a side surface of the first trench, the lower portion connecting the drain of the vertical transistor and the word lines; a second sub-structure connecting the upper portion, the middle portion, the lower portion, and the word line of the first sub-structure.

In an exemplary embodiment of the present disclosure, the material of the first substructure comprises silicon nitride and the material of the second substructure comprises silicon dioxide.

In an exemplary embodiment of the present disclosure, the second substructure includes: an inner layer structure connecting the middle and lower portions of the first substructure; an outer layer structure disposed between the inner layer structure and the first substructure, connecting an upper portion and a middle portion of the first substructure and a side portion of the word line; the outer layer structure is manufactured by a different process than the inner layer structure.

According to a second aspect of the present disclosure, there is provided a memory cell manufacturing method for manufacturing the memory cell as defined in any one of the above, comprising: providing a substrate, and manufacturing a vertical transistor and an isolation structure positioned on the vertical transistor and between two adjacent bit lines on the basis of the substrate, wherein the vertical transistor is provided with a source electrode, a grid electrode and a drain electrode from bottom to top, the grid electrode is connected with a word line, and the source electrode is connected with the bit line; manufacturing a first groove in the isolation structure at a position opposite to the vertical transistor, wherein the drain electrode of the vertical transistor is exposed from the lower surface of the first groove; depositing a conductive layer in the first trench and on an upper surface of the first trench in sequence, the upper surface of the conductive layer having a first height from the upper surface of the first trench; etching a second groove with the first height at a position, which is not opposite to the first groove, in the conductive layer to form a storage contact structure comprising an embedded part and a protruding part, wherein the embedded part is positioned in the first groove, and the protruding part is positioned on the embedded part; and sequentially forming a lower polar plate, a dielectric layer and an upper polar plate of the storage capacitor on the outer surface of the bulge.

In an exemplary embodiment of the present disclosure, the fabricating a vertical transistor based on the substrate and an isolation structure on the vertical transistor and between two adjacent bit lines includes: manufacturing a buried bit line in the substrate; forming a conductive channel perpendicular to the surface of the substrate above the buried bit line, a lower portion of the conductive channel being connected to the buried bit line and located in the substrate; a gate oxide layer, a metal gate layer and a word line structure are sequentially formed around the middle part of the conductive channel from inside to outside, and the word line structure is formed by two adjacent word lines; forming a primary isolation structure on the word line structure and the upper portion of the conductive channel; etching a position opposite to a midpoint of the word line structure in the preliminary isolation structure and the word line structure to form a word line isolation groove; and filling an insulating material in the word line isolation groove and the top layer of the primary isolation structure to form the isolation structure.

In an exemplary embodiment of the present disclosure, the forming of the preliminary isolation structure on the upper portions of the word line structure and the conductive channel includes: forming a first isolation material layer on the word line structure and the upper part of the conductive channel; and forming a second isolation material layer on the upper surface of the first isolation material layer.

In an exemplary embodiment of the present disclosure, the filling of an insulating material in the word line isolation trench and a top layer of the preliminary isolation structure to form the isolation structure includes: forming a third isolation material layer on the side wall of the word line isolation groove and the top layer of the primary isolation structure; and forming a fourth isolation material layer on the upper surface of the third isolation material layer, wherein the upper surface of the fourth isolation material layer is a plane.

In an exemplary embodiment of the present disclosure, the fabricating a first trench in the isolation structure at a position opposite to the vertical transistor includes: etching the first groove at a position opposite to the conductive channel of the vertical transistor in the isolation structure, so that the lower surface of the first groove exposes the drain electrode of the vertical transistor, and the upper surface of the first groove is larger than the lower surface; and forming a side wall isolation structure on the side wall of the first groove.

In an exemplary embodiment of the present disclosure, the sequentially depositing the conductive layer in the first trench and the upper surface of the first trench includes: and changing the doping particle type and the particle doping concentration in the deposited polysilicon in the process of depositing the conductive layer.

According to a third aspect of the present disclosure, there is provided a memory comprising the memory cell as defined in any one of the above.

The storage contact structure in the vertical storage unit is set to be the embedded part and the protruding part, the embedded part is wrapped by the isolation structure, the lower pole plate of the storage capacitor is manufactured on the surface of the protruding part, the contact area between the lower pole plate of the thin and high storage capacitor and the storage contact structure can be increased by a large area through the side surface of the protruding part, the problem that the connection between the storage capacitor and the storage contact structure is unstable due to reduction of the cross section of the storage capacitor and increase of the height of the storage capacitor in the manufacturing process of the vertical storage unit is solved, and powerful technical support is provided for further reducing the device size of the vertical storage unit and increasing the arrangement density of the vertical storage unit.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a schematic structural diagram of a memory cell in an exemplary embodiment of the present disclosure.

Fig. 2 is a schematic structural diagram of a storage contact structure 2 in one embodiment of the present disclosure.

Fig. 3 is a schematic structural diagram of a storage contact structure 2 in another embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of an isolation structure 4 in one embodiment of the present disclosure.

Fig. 5 is a schematic structural diagram of an isolation structure 4 in another embodiment of the present disclosure.

Fig. 6 is a flow chart of a method of manufacturing a memory cell in an exemplary embodiment of the disclosure.

Fig. 7 is a schematic sub-flow chart of step S1 in an embodiment of the present disclosure.

Fig. 8A to 8K are schematic diagrams illustrating the process of forming the conductive channel perpendicular to the surface of the substrate 10 above the buried bit line 200 in step S12.

Fig. 9A to 9D are schematic views of the manufacturing process of step S13 in one embodiment.

Fig. 10A and 10B are schematic views of the manufacturing process of step S14 in one embodiment.

Fig. 11A to 11C are schematic views of the manufacturing process of the step shown in step S15.

FIGS. 12A-12B are schematic diagrams illustrating the process of step S16 according to one embodiment.

FIG. 13 is a sub-flowchart of step S2 in one embodiment of the present disclosure.

Fig. 14A to 14C are schematic views of the process shown in fig. 13.

Fig. 15 is a schematic diagram of the step shown in step S3 in the embodiment of the present disclosure.

Fig. 16 is a schematic diagram of the step shown in step S4 in the embodiment of the present disclosure.

Fig. 17 is a schematic diagram of the step shown in step S5 in the embodiment of the present disclosure.

Fig. 18 is a schematic diagram of a memory cell 2 fabricated in an embodiment of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Further, the drawings are merely schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

The following detailed description of exemplary embodiments of the disclosure refers to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a memory cell in an exemplary embodiment of the present disclosure. The left side of fig. 1 is a cross-sectional view of the memory cell in a direction perpendicular to the bit line (a-a), the middle of fig. 1 is a cross-sectional view of the memory cell in a direction along the bit line (B-B), and the right side of fig. 1 is a schematic cross-sectional view.

Referring to fig. 1, the memory cell 100 may include:

the vertical transistor 1 is partially arranged in the substrate 10, the vertical transistor 1 is provided with a source electrode 11, a gate electrode 12 and a drain electrode 13 from bottom to top, the source electrode 11 is connected with the bit line 200, and the gate electrode 12 is connected with the word line 300;

storage contact structure 2, comprising:

an embedded portion 21 located in the first trench 20, a side surface of the first trench 20 being surrounded by the isolation structure 4, a lower surface of the embedded portion 21 being connected to the drain 13 of the vertical transistor 1;

a protrusion 22 located above the embedded portion 21 and connected to the upper surface of the embedded portion 21, the protrusion 22 having a columnar structure;

the storage capacitor 3 has a lower plate 31, a dielectric layer 32, and an upper plate 33, wherein the lower plate 31 is attached to the protrusion 22, the dielectric layer 32 is attached to the lower plate 31, and the upper plate 33 is attached to the dielectric layer 32.

In the memory cell 100 shown in fig. 1, since the lower portion (buried portion) of the storage contact structure 2 is disposed in the first trench 20, and the first trench 20 is surrounded by the isolation structure 4, even if the transistor size is reduced and the connection area of the storage contact structure 2 and the conduction channel of the vertical transistor 1 is reduced, the storage contact structure 2 can be stably connected to the drain 13 of the vertical transistor 1, the storage capacitor 3 formed by attaching the protruding portion 22 of the storage contact structure 2 can have high structural strength, and the storage capacitor 3 can be stable under the trend of increasing the height and reducing the width of the storage capacitor 3.

In addition, in the related art, the lower plate of the vertical storage capacitor has a columnar structure, and the connection area between the lower plate of the storage capacitor and the storage contact Structure (SNC) is a cross section of the columnar structure, and the connection area is continuously reduced with a tendency of reducing the width of the storage capacitor. In the embodiment of the present disclosure, since the lower plate 31 of the storage capacitor 3 is attached to the outer surface of the protrusion 22 of the columnar structure of the storage contact structure 2, the connection area between the lower plate 31 and the storage contact structure 2 is the surface area of the columnar structure except the bottom surface, and is much larger than the bottom area of the columnar structure (conventional contact structure), even if the feature size of the device is reduced and the device arrangement density is increased, the lower plate and the storage contact structure can be kept to have a larger contact area.

Fig. 2 is a schematic structural diagram of a storage contact structure 2 in one embodiment of the present disclosure. The left side of fig. 2 is a cross-sectional view of the memory cell in a direction perpendicular to the bit line (a-a), the middle of fig. 2 is a cross-sectional view of the memory cell in a direction along the bit line (B-B), and the right side of fig. 2 is a schematic cross-sectional view.

Referring to fig. 2, in one embodiment of the present disclosure, the upper surface of the embedded portion 21 in the storage contact structure 2 is larger than the lower surface, and both the upper surface and the lower surface of the protruding portion 22 are equal to the upper surface of the embedded portion 21.

The structure shown in fig. 2 can improve the structural strength of the storage contact structure 2 when the channel size is limited and the storage capacitor height requirement is high. Because the upper surface of the embedded part 21 is larger than the lower surface, and the upper surface and the lower surface of the protruding part 22 are both equal to the upper surface of the embedded part 21, the surface area of the protruding part 22 can be increased without increasing the size of a conductive channel of a transistor, so that the contact area between the lower plate of the storage capacitor and the storage contact structure 2 is increased, the performance of the capacitor is improved, and the storage capacitor with higher capacitance value is formed at the same height; under the same capacitance value, the requirement on the height of the storage capacitor is reduced, and the height of the storage capacitor is reduced, so that the connection strength of the storage capacitor can be further improved.

Fig. 3 is a schematic structural diagram of a storage contact structure 2 in another embodiment of the present disclosure. The left side of fig. 3 is a cross-sectional view of the memory cell in a direction perpendicular to the bit line (a-a), the middle of fig. 3 is a cross-sectional view of the memory cell in a direction along the bit line (B-B), and the right side of fig. 3 is a schematic cross-sectional view.

Referring to fig. 3, in the embodiment of the present disclosure, the buried portion 21 and the protruding portion 22 are both made of a doped semiconductor, such as polysilicon (poly) doped with conductive particles. The conductive particles doped in the embedded portion 21 and the protruding portion 22 may be trivalent particles or pentavalent particles, such As conductive particles of boron (B), phosphorus (P), arsenic (As), and the like, for example, and the disclosure is not limited thereto.

In the embodiment of the present disclosure, the doping particle type of the embedded portion 21 and the doping particle type of the protruding portion 22 may not be completely the same, and the doping concentration of the embedded portion 21 and the doping concentration of the protruding portion 22 may not be completely the same.

In the embodiment shown in fig. 3, the doping concentration of the projections 22 is greater than that of the buried portion 21 to achieve better conductivity in the region close to the bottom plate 31. In other embodiments of the present disclosure, the doping concentrations of the protruding portion 22 and the embedded portion 21 may be the same, or the doping concentration of the particles may be gradually increased from the embedded portion 21 toward the protruding portion 22, and the ratio of each type of doped particles may be gradually changed from the embedded portion 21 toward the protruding portion 22.

In the embodiments shown in fig. 1 to 3, the isolation structure 4 may have a portion surrounding the drain of the vertical transistor and the buried portion 21 of the memory contact structure 2, and another portion disposed between two adjacent word lines 300.

In other embodiments of the present disclosure, the isolation structure 4 may also include a plurality of sub-structures, the materials of which are not identical.

Fig. 4 is a schematic structural diagram of an isolation structure 4 in one embodiment of the present disclosure. The left side of fig. 4 is a cross-sectional view of the memory cell in the direction perpendicular to the bit line (a-a), the middle of fig. 4 is a cross-sectional view of the memory cell in the direction along the bit line (B-B), and the right side of fig. 4 is a schematic cross-sectional view.

Referring to fig. 4, in one embodiment, the isolation structure 4 may include:

a first substructure 41 having an upper portion 411, a middle portion 412 and a lower portion 413 connected in sequence, the upper portion 411 being connected to the lower plate 31 of the storage capacitor 3 and extending downward between two adjacent word lines 300, the middle portion 412 surrounding the side surface of the first trench 20, the lower portion 413 being connected to the drain 13 of the vertical transistor 1 and the word lines 300;

the second sub-structure 42 connects the upper portion 411, the middle portion 412, the lower portion 413 of the first sub-structure 41 and the word line 300.

The material of the first sub-structure 41 may be, for example, silicon nitride (SiN), and the material of the second sub-structure 42 may be, for example, silicon dioxide (SiO)₂) Or other oxides.

In the manufacturing process, the lower part 413 of the first substructure 41 is manufactured first, followed by the second substructure 42 and the upper part 411 of the first substructure 41, and the upper part 411 of the first substructure 41 and the second substructure 42 are etched. Since the material of the first sub-structure 41 is different from the material of the second sub-structure 42, the etching gas has an etching selectivity for the material of the first sub-structure 41 and the material of the second sub-structure 42, and thus, by providing the isolation structure 4 as a plurality of sub-portions of different materials, it is possible to reduce the extent to which the entire isolation structure 4 is damaged during the etching of the first trench 20 when etching the first trench 20 during the manufacturing process.

When the material of the first substructure 41 is silicon nitride and the material of the second substructure 42 is oxide, the external structural strength of the isolation structure 4 can be improved by using the characteristic that silicon nitride is harder, and the structural error caused by stress release due to the high thermal expansion coefficient of silicon nitride can be reduced by arranging the oxide inside the isolation structure 4, thereby reducing the manufacturing cost.

Fig. 5 is a schematic structural diagram of an isolation structure 4 in another embodiment of the present disclosure. The left side of fig. 5 is a cross-sectional view of the memory cell in a direction perpendicular to the bit line direction (a-a), the middle of fig. 5 is a cross-sectional view of the memory cell in a direction along the bit line direction (B-B), and the right side of fig. 5 is a schematic cross-sectional view.

Referring to fig. 5, in yet another embodiment of the present disclosure, the second substructure 42 may include:

an inner layer structure 421 connecting the middle part 412 and the lower part 413 of the first substructure 41;

and an outer layer structure 422 disposed between the inner layer structure 421 and the first substructure 41, connecting the upper portion 411, the middle portion 412 of the first substructure 41 and the side portion of the word line 300.

The outer layer structure 422 and the inner layer structure 421 are manufactured by different processes.

In the embodiment shown in fig. 5, the inner Layer 421 may be fabricated by TEOS (Tetraethyl orthosilicate), for example, and the outer Layer 422 may be fabricated by ALD (Atomic Layer Deposition), for example.

TEOS can generate silicon dioxide quickly, a loose and porous inner layer structure 421 can be formed quickly, and the method plays a positive role in improving process efficiency and reducing manufacturing cost. However, contact between silicon dioxide manufactured via TEOS and silicon nitride forming the first sub-structure 41 is poor, and therefore, the outer layer structure 422 manufactured by the ALD process is disposed between the inner layer structure 421 and the first sub-structure 41 in the embodiment of the present disclosure to improve adhesion and structural strength of each portion in the entire isolation structure 4.

ALD is a process that can plate a substance as a monoatomic film layer by layer on a substrate surface, involves a complicated surface chemical process, has a low deposition rate, and deposits a layer with an extremely uniform thickness and excellent uniformity. Because the deposition speed is slow and the deposition quality is good, the outer layer structure 422, the inner layer structure 421 and the first sub-structure 41 manufactured by the ALD process have good connection strength, and when the outer layer structure 422, the inner layer structure 421 and the first sub-structure 41 are extended to the space between the silicon nitride and the gate metal layer of the bit line 300, the connection strength between the isolation structure 4 and the bit line 300 can be improved, and poor contact between the silicon nitride and the gate metal layer of the bit line 300 is avoided. The outer structure 422 need not be thick in order to increase manufacturing speed. The thickness of the outer layer 422 may be set by one skilled in the art, and the present disclosure is not limited in this regard.

Any of the embodiments of fig. 2-5 can be freely combined, i.e., in other embodiments of the present disclosure, there are solutions that include any two or more combinations of the features shown in fig. 2, fig. 3, fig. 4, or fig. 5. The disclosure is not further illustrated herein.

Referring to fig. 6, in an embodiment of the present disclosure, a memory cell manufacturing method 600 may include:

step S1, providing a substrate, and manufacturing a vertical transistor and an isolation structure positioned on the vertical transistor and between two adjacent bit lines on the basis of the substrate, wherein the vertical transistor is provided with a source electrode, a grid electrode and a drain electrode from bottom to top, the grid electrode is connected with a word line, and the source electrode is connected with the bit line;

step S2, manufacturing a first groove in the isolation structure at a position opposite to the vertical transistor, wherein the drain electrode of the vertical transistor is exposed from the lower surface of the first groove;

step S3, depositing a conductive layer in the first trench and on an upper surface of the first trench in sequence, the upper surface of the conductive layer having a first height from the upper surface of the first trench;

step S4, etching a second trench having a depth equal to the first height at a position of the conductive layer not opposite to the first trench to form a storage contact structure including a buried portion and a protruding portion, wherein the buried portion is located in the first trench and the protruding portion is located on the buried portion;

in step S5, a lower plate, a dielectric layer, and an upper plate of a storage capacitor are sequentially formed on the outer surface of the protrusion.

The method of fig. 6 may be used to fabricate a memory cell as shown in any of the embodiments of fig. 1-5.

Next, each step in fig. 6 will be explained in detail.

Referring to fig. 7, in one embodiment, step S1 may include:

step S11, fabricating buried bit lines in the substrate;

step S12, forming a conductive channel perpendicular to the surface of the substrate above the buried bit line, a lower portion of the conductive channel being connected to the buried bit line and located in the substrate;

step S13, forming a gate oxide layer, a metal gate layer and a word line structure in sequence from inside to outside around the middle part of the conductive channel, wherein the word line structure is formed by two adjacent word lines;

step S14, forming a primary isolation structure on the word line structure and the upper portion of the conductive channel;

step S15, etching the position of the primary isolation structure opposite to the midpoint of the word line structure and the word line structure to form a word line isolation groove;

step S16, filling an insulating material in the word line isolation trench and the top layer of the preliminary isolation structure to form the isolation structure.

The process of fabricating the buried bit line 200 in the substrate 10 at step S11 may first include etching a trench in the substrate 10, in which the buried bit line 200 is fabricated. The buried bit line 200 may include an outer titanium nitride (TiN) layer 201 and an inner tungsten (W) structure 202. The process of fabricating the buried bit line 200 may be a general scheme, and thus the present disclosure does not specifically describe this.

Fig. 8A to 8K are schematic diagrams illustrating the process of forming the conductive channel perpendicular to the surface of the substrate 10 above the buried bit line 200 in step S12. The lower portion of the conductive channel is connected to the buried bit line 200 and located in the substrate 10.

In fig. 8A, polysilicon is first filled in the trench formed during the fabrication of the buried bit line 200, and the hard mask layer 101 disposed during the trench fabrication remains on the surface of the substrate 10.

In fig. 8B, the polysilicon portion is N-type ion doped to form the source 11.

In fig. 8C, the hard mask layer 101 is removed to provide an operation plane for subsequent processes.

In fig. 8D, a hard mask layer 101, an oxide layer 102, a first Organic Carbon (SOC) layer 103, a first silicon oxynitride (SiON) layer 104, a second Organic Carbon layer 105, a second silicon oxynitride layer 106, and a photoresist layer 107 are sequentially deposited on the plane of fig. 8C. Wherein the hard mask layer 101 may be, for example, silicon nitride, and the oxide layer 102 may be deposited by TEOS.

In fig. 8E, after the photoresist layer 107 is masked, exposed, developed, and stripped, a trench 108 is formed in the first organic carbon layer 103.

In fig. 8F, after etching the oxide layer 102 and the hard mask layer 101 corresponding to the trench 108, a trench 109 is formed to accommodate the conductive channel.

In fig. 8G, oxide layer 110 is deposited over trench 109 and the surface of oxide layer 102.

In fig. 8H, the oxide layer 110 is etched to expose the source 11 of the conductive channel.

In fig. 8I, the trench 109 with an oxide layer formed on its sidewalls is filled with the body material silicon of the conductive channel to form a channel region 121 for fabricating the gate and the drain.

In fig. 8J, the channel region 121 is doped to form a gate corresponding conductive channel 12 and drain 13. At this time, the oxide layer 110 outside the channel region may serve as a stop layer for reducing an etching Loading Effect (Loading Effect) of the wet etching process.

In fig. 8K, the oxide layer 102 and the damaged oxide layer 110 are removed.

Fig. 9A to 9D are schematic process diagrams of step S13. In step S13, a gate oxide layer, a metal gate layer, and a word line structure are sequentially formed from inside to outside around the middle portion of the conductive channel, the word line structure being composed of two adjacent word lines.

In fig. 9A, a gate oxide layer 122 is formed on a surface layer of the conductive channel, the gate oxide layer 122 may be deposited by, for example, an ALD process, and specifically, the gate oxide layer 122 may be formed by an ISSG (in-situ steam generation) process to have a thickness of 2 to 8nm, and an RPN (remote plasma-assisted nitridation) process is used to perform an annealing process under a high temperature nitrogen condition.

In fig. 9B, a gate metal layer 123 is deposited, and the material of the gate metal layer 123 may be, for example, titanium nitride (TiN).

In fig. 9C, the word line metal layer material 301 is deposited with tungsten (W) followed by CMP planarization.

In fig. 9D, the existing structure is etched to form a bitline structure base 302 (uncut bitlines) surrounding each gate. Because the etching ratio of tungsten to titanium nitride is larger than 4:1, and the etching ratio of titanium nitride to oxide layer is larger than 10:1, the oxide layer 122 can be used as an etching stop layer in the etching process, and silicon damage of the drain part is avoided.

In one embodiment, when the memory cell is provided with the isolation structure as shown in fig. 5, step S14 can be implemented by fig. 10A and 10B.

In fig. 10A, a first isolation material layer 401 is deposited on the word line structure and the upper portion of the conductive channel, the material of the first isolation material layer 401 may be, for example, silicon nitride (SiN), the deposition process may be, for example, ALD, and the deposition thickness may be, for example, 2 to 5 nm. The insulating layer deposited this time may serve as an insulating layer of the bit line structure 300, on the one hand, and may serve as an etch stop layer for a subsequent process, on the other hand.

In fig. 10B, a second isolation material layer 402 is deposited on the upper surface of the first isolation material layer 401, the material of the second isolation material layer 402 may be, for example, an oxide such as silicon oxide, and the filling process may be TEOS, for example.

The first isolation material layer and the second isolation material layer are collectively referred to as a primary isolation structure. When the isolation structure of the memory cell is the structure shown in fig. 4, the preliminary isolation structure may be formed by one deposition, which is not described herein again.

11B, 11C, and subsequent figures all show schematic diagrams perpendicular to both the bit line direction (A-A) and the bit line extension direction (B-B), since step S15 is followed by operations primarily perpendicular to the bit line direction.

In fig. 11A, first, a first Organic Carbon (SOC) layer 103, a first silicon oxynitride (SiON) layer 104, a second Organic Carbon layer 105, a second silicon oxynitride layer 106, and a photoresist layer 107 are sequentially deposited on the primary isolation structure.

In fig. 11B, after processes of masking, wave-irradiating, developing, photoresist-removing, etc. the photoresist layer 107, a trench is formed in the first organic carbon layer 103 and the first silicon oxynitride (SiON) layer 104 opposite to the midpoint of the word line structure 300.

In fig. 11C, after etching is performed downward from a position corresponding to the trench 108, a word line isolation groove 403 is formed.

Referring to fig. 12A and 12B, in one embodiment, step S16 may include making a third layer of isolation material and a fourth layer of isolation material.

In fig. 12A, a third isolation material layer 404 is formed on the sidewalls of the word line isolation trenches 403 and the top layer of the preliminary isolation structure.

In fig. 12B, a fourth isolation material layer 405 is formed on the upper surface of the third isolation material layer 404, and the upper surface of the fourth isolation material layer 405 is a plane.

To this end, an isolation structure between the word line isolation structure and the next memory contact structure 2 is fabricated at once.

Referring to fig. 13, in one embodiment, step S2 may include:

step S21, etching the first trench at a position opposite to the conductive channel of the vertical transistor in the isolation structure, so that the lower surface of the first trench exposes the drain of the vertical transistor, and the upper surface of the first trench is larger than the lower surface;

in step S22, a sidewall isolation structure is formed on the sidewall of the first trench.

Fig. 14A to 14C are schematic views of the process shown in fig. 13.

In fig. 14A, the positioning groove 406 is first formed using an oxide layer and a photolithography process.

In FIG. 14B, the first trench 20 is etched down along the trenches 406. The bottom of the first trench 20 exposes the drain, and in some embodiments, the critical dimension of the bottom of the first trench 20 may be etched by more than 1.1 times the critical dimension of the word line, so that the contact area between the memory contact structure 2 and the conductive channel is increased, and the memory contact structure 2 and the conductive channel have lower contact resistance.

In fig. 14C, sidewall isolation structures are deposited around the first trench 20 to form a first substructure 41 and a second substructure 42 as in the embodiment shown in fig. 5, completing the fabrication of the isolation structure 4. The sidewall isolation structure is used as the middle portion of the first sub-structure 41, and the material of the sidewall isolation structure may be, for example, silicon nitride (SiN), and is integrated with the upper portion and the lower portion of the first sub-structure 41. The process of depositing the sidewall isolation structure may be, for example, ALD in order to achieve precise deposition.

Referring to fig. 15, in step S3, a conductive layer 23 is sequentially deposited in the first trench 20 and on an upper surface of the first trench 20, the upper surface of the conductive layer 23 having a first height H1 from the upper surface of the first trench.

During deposition of the conductive layer, the type of doping particles and the doping concentration of the particles in the deposited polysilicon may be varied to achieve the features of the storage contact structure 2 in the embodiment shown in fig. 3.

Referring to fig. 16, in step S4, a second trench 24 having a first height H1 is etched into the conductive layer 23 at a position not opposite to the first trench 20 to form a storage contact structure 2 including a buried portion 21 and a protruding portion 22, the buried portion 21 being located in the first trench 20, the protruding portion 22 being located on the buried portion 21. The stop layer of the second trench 24 is etched to be the top of the isolation structure 4, and by etching the second trench 24, the isolation between the memory cells and the isolation of the memory contact structure are manufactured at one time, so that AIO (all in one, one-step molding) is realized.

The oxide layer and the SOC layer may also be used to fabricate a mask layer and a lithographic groove prior to etching for precise positioning, and the disclosure is not repeated herein.

Referring to fig. 17, at step S5, the lower plate 32, the dielectric layer 32, and the upper plate 33 of the storage capacitor 3 are sequentially formed on the outer surface of the projection 22.

After depositing the bottom plate material (e.g., titanium nitride), etching back, a Hi-K material (high dielectric parameter material) is deposited as the dielectric layer 32, and then a top plate material is deposited.

After the top plate is deposited, the capacitors can be filled with a conductive material 181 (e.g., polysilicon) to a certain height (at least above the top of the top plate of the capacitor), and then planarized with a top layer covered with a hard mask material 182, as shown in fig. 18.

The embodiment shown in fig. 18 has the features shown in fig. 2 and 5, the upper surface of the first groove 20 is larger than the lower surface, the isolation structure is divided into a first substructure 41 and a second substructure 42, the first substructure 41 comprises an upper portion 411, a middle portion 412 and a lower portion 413, and the second substructure 42 comprises an inner layer structure 421 and an outer layer structure 422. In other embodiments of the present disclosure, the specific implementation of the steps may be modified to fabricate memory cells with other features.

The present disclosure also provides a memory comprising a memory cell as defined in any one of the above, manufactured by a method of manufacturing a memory cell as defined in any one of the above.

It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice in the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A memory cell, comprising:

the vertical transistor is partially arranged in the substrate and provided with a source electrode, a grid electrode and a drain electrode from bottom to top, the grid electrode is connected with a word line, and the source electrode is connected with a bit line;

a storage contact structure comprising:

the embedded part is positioned in the first groove, the side surface of the first groove is wrapped by the isolation structure, and the lower surface of the embedded part is connected with the drain electrode of the vertical transistor;

the protruding part is positioned above the embedded part and connected with the upper surface of the embedded part, and the protruding part is of a columnar structure;

the storage capacitor is provided with a lower polar plate, a dielectric layer and an upper polar plate, wherein the lower polar plate is attached to the protruding part, the dielectric layer is attached to the lower polar plate, and the upper polar plate is attached to the dielectric layer;

wherein a portion of the isolation structure surrounds the drain of the vertical transistor and the buried portion of the storage contact structure, and another portion of the isolation structure is disposed between two adjacent word lines;

in the storage contact structure, the upper surface of the embedded part is larger than the lower surface of the embedded part, and the upper surface and the lower surface of the protruding part are equal to the upper surface of the embedded part; and/or the embedded part and the bulge part are both made of doped semiconductors, the type of doped particles of the embedded part is not completely the same as that of the bulge part, and the doping concentration of the embedded part is not completely the same as that of the bulge part.

2. The memory cell of claim 1, wherein the isolation structure comprises a plurality of sub-structures, the materials of the plurality of sub-structures not being identical.

3. The memory cell of claim 2, wherein the isolation structure comprises:

a first substructure having an upper portion, a middle portion and a lower portion connected in sequence, the upper portion connecting the lower plate of the storage capacitor and the dielectric layer and extending downward between two adjacent word lines, the middle portion surrounding a side surface of the first trench, the lower portion connecting the drain of the vertical transistor and the word lines;

a second sub-structure connecting the upper portion, the middle portion, the lower portion, and the word line of the first sub-structure.

4. The memory cell of claim 3 wherein the material of the first substructure comprises silicon nitride and the material of the second substructure comprises silicon dioxide.

5. The memory cell of claim 3, wherein the second substructure comprises:

an inner layer structure connecting the middle and lower portions of the first substructure;

an outer layer structure disposed between the inner layer structure and the first substructure, connecting an upper portion and a middle portion of the first substructure and a side portion of the word line;

the outer layer structure is manufactured by a different process than the inner layer structure.

6. A method for manufacturing a memory cell according to any one of claims 1 to 5, comprising:

providing a substrate, and manufacturing a vertical transistor and an isolation structure positioned on the vertical transistor and between two adjacent bit lines on the basis of the substrate, wherein the vertical transistor is provided with a source electrode, a grid electrode and a drain electrode from bottom to top, the grid electrode is connected with a word line, and the source electrode is connected with the bit line;

manufacturing a first groove in the isolation structure at a position opposite to the vertical transistor, wherein the drain electrode of the vertical transistor is exposed from the lower surface of the first groove;

sequentially depositing a conductive layer in the first trench and on an upper surface of the first trench, the upper surface of the conductive layer having a first height from the upper surface of the first trench;

etching a second groove with the first height at a position, which is not opposite to the first groove, in the conductive layer to form a storage contact structure comprising an embedded part and a protruding part, wherein the embedded part is positioned in the first groove, and the protruding part is positioned on the embedded part;

and sequentially forming a lower electrode plate, a dielectric layer and an upper electrode plate of the storage capacitor on the outer surface of the bulge part.

7. The method of claim 6, wherein fabricating a vertical transistor based on the substrate and an isolation structure over the vertical transistor and between two adjacent bit lines comprises:

manufacturing a buried bit line in the substrate;

forming a conductive channel perpendicular to the surface of the substrate above the buried bit line, a lower portion of the conductive channel being connected to the buried bit line and located in the substrate;

a gate oxide layer, a metal gate layer and a word line structure are sequentially formed around the middle part of the conductive channel from inside to outside, and the word line structure is formed by two adjacent word lines;

forming a primary isolation structure on the word line structure and the upper portion of the conductive channel;

etching a position opposite to a midpoint of the word line structure in the preliminary isolation structure and the word line structure to form a word line isolation groove;

and filling an insulating material in the word line isolation groove and the top layer of the primary isolation structure to form the isolation structure.

8. The method of manufacturing a memory cell of claim 7, wherein said forming a preliminary isolation structure on top of said word line structure and said conductive channel comprises:

forming a first isolation material layer on the word line structure and the upper part of the conductive channel;

and forming a second isolation material layer on the upper surface of the first isolation material layer.

9. The method of manufacturing a memory cell according to claim 7, wherein the filling of an insulating material in the wordline isolation trench and a top layer of the preliminary isolation structure to form the isolation structure comprises:

forming a third isolation material layer on the side wall of the word line isolation groove and the top layer of the primary isolation structure;

and forming a fourth isolation material layer on the upper surface of the third isolation material layer, wherein the upper surface of the fourth isolation material layer is a plane.

10. The method of manufacturing a memory cell according to claim 6, wherein said manufacturing a first trench in the isolation structure opposite the vertical transistor comprises:

etching the first groove at a position opposite to the conductive channel of the vertical transistor in the isolation structure, so that the lower surface of the first groove exposes the drain electrode of the vertical transistor, and the upper surface of the first groove is larger than the lower surface;

and forming a side wall isolation structure on the side wall of the first groove.

11. The method of manufacturing a memory cell according to claim 6, wherein said sequentially depositing a conductive layer in the first trench and on an upper surface of the first trench comprises:

and in the process of depositing the conductive layer, changing the doping particle type and the particle doping concentration in the deposited polysilicon.

12. A memory comprising a memory cell according to any one of claims 1 to 5.