CN113066732B - Method for forming integrated circuit structure - Google Patents
Method for forming integrated circuit structure Download PDFInfo
- Publication number
- CN113066732B CN113066732B CN202110273795.3A CN202110273795A CN113066732B CN 113066732 B CN113066732 B CN 113066732B CN 202110273795 A CN202110273795 A CN 202110273795A CN 113066732 B CN113066732 B CN 113066732B
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- processor
- circuit structure
- conductive
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 239000004020 conductor Substances 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000003466 welding Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 10
- 239000002184 metal Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000007906 compression Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
Abstract
The application discloses a forming method of an integrated circuit structure, which is characterized by comprising a processor device, wherein the surface of the processor device is provided with conductive bumps, at least one memory device is provided with conductive bumps on the inverted top surface, the memory device and the processor device are partially overlapped, and part of the conductive bumps on the memory device and part of the conductive bumps on the processor device are contacted and conducted with each other; welding the conductive bump and the conductive bump which are in contact with each other; inverting the processor device with the memory device fixed on a semiconductor medium so that the conductive boss on the semiconductor medium with the conductive boss on the top surface and the conductive boss which is not blocked by the memory device and is positioned on the processor device are formed; the conductive bumps and conductive lands are soldered in contact with each other such that the memory device, the processor device and the semiconductor medium form the memory, the processor and the semiconductor substrate, respectively, in the integrated circuit structure described above.
Description
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a method for forming an integrated circuit structure.
Background
Currently, with the continuous development of technology, high Performance Computing (HPC) and Artificial Intelligence (AI) technologies are rapidly developed, and the performance requirements on integrated circuit chips are also higher and higher. In particular, as 5G technology continues to be combined with various industries, some areas require integrated circuit chips with high data transfer rates, high throughput, low latency, and large bandwidth capabilities.
For many years, the technical development and market application of integrated circuit chip manufacturers followed moore's law, i.e., the number of integrated circuits on an integrated circuit chip doubles every 18 months, while the price drops by half. However, the number of integrated circuits increases and the size of the chip is getting smaller, so as the number of integrated transistors on the silicon chip increases, the line density increases and the complexity and error rate will also increase exponentially, thus making full and thorough chip testing almost impossible.
Once the width of the line on the chip reaches the order of nanometers (10-9 meters), which is equivalent to the size of a few molecules, the physical and chemical properties of the material are changed, and the semiconductor device adopting the existing technology cannot work normally, so that the Moore's law is reached.
Two major challenges facing the chip industry today are how to achieve integration complexity minimization. And how to optimize the cost. Because of the limitations of the structure of the integrated circuit chip itself, manufacturers have expanded from advanced packaging technology to advanced packaging technology in the interest of pursuing higher frequencies and smaller size advanced process technologies. The currently prevailing advanced packaging technologies include 7 important technologies of Flip-Chip, WLCSP, fan-Out, embedded IC, 3D WLCSP, 3D IC, 2.5D inter, etc. Whatever packaging technique is used, it is desirable to address how memory is placed closest to an integrated circuit chip (e.g., processor) to reduce latency and power consumption by connecting via shorter wires.
One prior art technique is to arrange the memory and processor side-by-side on a substrate, connected by wiring within the substrate. However, with this technique, a predetermined distance is required between the processor and the memory in the lateral direction. In this way, the distance between the memory and the processor cannot be minimized, and the size of the integrated circuit chip in the lateral direction is increased. The size in the lateral direction of the chip increases, so that the cost of the chip increases. Another technical approach is to deploy multiple memory and processor die (die) on one or more layers of silicon substrate (Si interposer) with TSV vertical interconnect vias and high density metal routing, and then package. But with this technique, a via needs to be opened and a metal conductive layer needs to be implanted in the via. Therefore, this technique is very complex and is disadvantageous for improving the yield and efficiency of integrated circuit chip production. Moreover, the silicon substrate is always spaced between the memory and the processor die, and therefore, the spacing between the memory and the processor cannot be minimized.
Disclosure of Invention
Another advantage of the present invention is to provide a method of forming an integrated circuit structure, wherein the integrated circuit structure formed by the method of forming an integrated circuit structure can be made smaller in size, and can also be made smaller in pitch between a processor and a memory, thereby satisfying the requirement for the integrated circuit structure.
Another advantage of the present invention is to provide a method for forming an integrated circuit structure, in which a manufacturing process of the integrated circuit structure formed by the method for forming an integrated circuit structure is simple, so that manufacturing efficiency of the integrated circuit structure can be improved.
Another advantage of the present invention is to provide a method of forming an integrated circuit structure, in which the integrated circuit structure formed by the method of forming an integrated circuit structure can be smaller in size in the lateral direction, and thus the manufacturing cost of a chip manufacturer can be reduced.
Another advantage of the present invention is to provide a method of forming an integrated circuit structure having a relatively low delay rate due to a relatively reduced pitch between the memory and the processor.
Another advantage of the present invention is to provide a method for forming an integrated circuit structure, wherein after a space between a memory and a processor in the integrated circuit structure formed by the method for forming an integrated circuit structure is reduced, a length of a conductor required to be disposed for conducting the memory and the processor is effectively reduced, thereby effectively reducing energy consumption of the integrated circuit structure.
Another advantage of the present invention is to provide a method of forming an integrated circuit structure in which the spacing between a memory and a processor in the integrated circuit structure formed by the method of forming an integrated circuit structure can be reduced, and thus, the error rate of the integrated circuit structure is correspondingly reduced.
Another advantage of the present invention is to provide a method of forming an integrated circuit structure in which a pitch between a memory and a processor in the integrated circuit structure formed by the method of forming an integrated circuit structure can be reduced, and thus, the integrated circuit structure generates less heat.
To achieve at least one of the above advantages, the present invention provides a method for forming an integrated circuit structure, comprising the steps of:
s1, inverting at least one memory device with a conductive bump on the top surface and a processor device with a conductive bump on the surface, and enabling the memory device and the processor device to be partially overlapped, wherein part of the conductive bump on the memory device and part of the conductive bump on the processor device are mutually contacted and conducted;
s2, thermocompression bonding the conductive bump and the conductive bump which are in contact with each other;
s3, inverting the processor device with the memory device fixed on a semiconductor medium so that the conductive boss on the semiconductor medium with the conductive boss arranged on the top surface and the conductive boss which is not blocked by the memory device and is positioned on the processor device are formed; and
s4, thermocompression bonding the conductive bump and the conductive boss which are in contact with each other, so that the memory device, the processor device and the semiconductor medium respectively form a memory, a processor and a semiconductor substrate in an integrated circuit structure.
According to an embodiment of the present invention, the semiconductor medium is provided with a wiring layer in advance.
According to an embodiment of the present invention, the method for forming an integrated circuit structure further includes the steps of:
s5, providing a bearing plate with a groove;
s6, placing the processor device in the groove in a mode that the conductive protrusion faces upwards; and
and S7, after the step S3 is completed, removing the bearing plate.
According to an embodiment of the present invention, a sum of heights of the memory and the thermocompression-bonded conductive bump and the conductive bump in a thickness direction of the semiconductor substrate is adapted to a sum of heights of the conductive bump and the conductive bump provided between a side of the processor facing the semiconductor substrate and the semiconductor substrate in the thickness direction of the semiconductor substrate.
According to an embodiment of the present invention, the plurality of conductive bumps and the plurality of conductive bumps are disposed at intervals.
According to an embodiment of the present invention, the integrated circuit structure includes two wiring layers symmetrically formed on both sides of the semiconductor substrate.
According to an embodiment of the present invention, the integrated circuit structure includes a plurality of electrical conductors, wherein a plurality of through holes are formed between the top side and the bottom side of the semiconductor substrate, and each of the electrical conductors is electrically connected to the wiring layer on the top side of the semiconductor substrate and the wiring layer on the bottom side of the semiconductor substrate at two ends after passing through the through holes, respectively, so as to form a specific circuit structure.
According to an embodiment of the present invention, the integrated circuit structure further includes a power board, wherein the power board is electrically connected to the memory by the electrical connector.
According to an embodiment of the present invention, at least one bypass capacitor is disposed on the power board.
According to one embodiment of the invention, the processor is implemented as a microprocessor.
Drawings
Fig. 1 shows a perspective view of an integrated circuit structure according to the invention.
Fig. 2 shows a partial cross-sectional view of a semiconductor substrate and wiring layer of an integrated circuit structure according to the present invention.
Figure 3 shows a partial cross-sectional view of an integrated circuit structure according to the present invention.
Fig. 4 shows a cross-sectional view of a wiring layer according to the present invention.
Fig. 5 is a schematic diagram illustrating a stage in the fabrication process of the integrated circuit structure according to the present invention.
Fig. 6 is a schematic diagram illustrating a second stage of the fabrication process of the integrated circuit structure according to the present invention.
Fig. 7 is a schematic diagram showing a third stage of the fabrication process of the integrated circuit structure according to the present invention.
Fig. 8 shows a flow chart of the fabrication of the integrated circuit structure of the present invention.
Detailed Description
The following description is presented to enable one of ordinary skill in the art to make and use the invention. The preferred embodiments in the following description are by way of example only and other obvious variations will occur to those skilled in the art. The basic principles of the invention defined in the following description may be applied to other embodiments, variations, modifications, equivalents, and other technical solutions without departing from the spirit and scope of the invention.
It will be appreciated by those skilled in the art that in the present disclosure, the terms "longitudinal," "transverse," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," etc. refer to an orientation or positional relationship based on that shown in the drawings, which is merely for convenience of description and to simplify the description, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore the above terms should not be construed as limiting the present invention.
It will be understood that the terms "a" and "an" should be interpreted as referring to "at least one" or "one or more," i.e., in one embodiment, the number of elements may be one, while in another embodiment, the number of elements may be plural, and the term "a" should not be interpreted as limiting the number.
Referring to fig. 1 to 4, an integrated circuit structure according to a preferred embodiment of the present invention will be described in detail below, wherein the integrated circuit structure can be used in a variety of electronic or electrical devices, such as mobile phones, computers, and the like.
In particular, the integrated circuit structure includes at least one semiconductor substrate 10, at least one wiring layer 20, at least one memory 30, and at least one processor 40. The wiring layer 20 is formed on one side of the semiconductor substrate 10. Each of the memory 30 and the processor 40 is mounted on the same side of the semiconductor substrate 10 so as to partially overlap, and the memory 30 and the processor 40 are in communication with each other, and furthermore, the processor 40 is disposed in communication with the wiring layer 20, wherein the back surface of the memory 30 is inverted to the semiconductor substrate 10.
Those skilled in the art will appreciate that the memory 30 may be implemented as any one or a combination of two or more selected from HBM, DRAM, SRAM or solid state storage such as flash memory devices, and the invention is not limited in this respect. The processor 40 may be implemented as a central processing unit CPU or as a microprocessor MPU, as the invention is not limited in this respect.
It should be noted that, since the memory 30 and the processor 40 are partially mounted overlapping on the same side of the semiconductor substrate 10 and the memory 30 and the processor 40 are in communication with each other, the lateral size of the semiconductor substrate 10 required for the integrated circuit structure can be reduced, thereby enabling the cost of the integrated circuit structure as a whole to be reduced.
It is further noted that the memory 30 and the processor 40 are provided with electrical connectors 50 at overlapping portions thereof. And the electrical connection 50 is provided between the memory 30 or the processor 40, which is inverted with respect to the semiconductor substrate 10, and the top of the semiconductor substrate 10 facing the processor 40.
In one embodiment, the processor 40 is inverted to the semiconductor substrate 10 and is conducted to the set wiring layer 20 by the electrical connection 50. It should be noted that the electrical connection 50 is implemented as at least one conductive bump, and the plurality of conductive bumps disposed between the processor 40 and the semiconductor substrate 10 have uniform heights, so that the processor 40 can be supported by the electrical connection 50 when the processor 40 is inverted on the semiconductor substrate 10.
In addition, when the integrated circuit structure includes a plurality of the electrical connectors 50, the plurality of electrical connectors 50 are disposed at intervals in such a manner that a predetermined size of gap between the processor 40 and the semiconductor substrate 10 will be able to be formed. Therefore, when the integrated circuit structure is mounted on an electronic device or an electric device and the processor 40 in the integrated circuit structure operates for a long time or a high load to generate a large amount of heat, the heat can be dissipated through the gap between the processor 40 and the semiconductor substrate 10, that is, the integrated circuit structure of the present invention has a good heat dissipation effect.
In addition, since the processor 40 and the memory 30 are partially overlapped, and the processor 40 and the memory 30 are electrically connected to each other through the electrical connector 50 provided between the overlapped portions of the processor 40 and the memory 30, the distance between the processor 40 and the memory 30 can be controlled by controlling the necessary length of the electrical connector 50. Also, due to this arrangement, the distance between the processor 40 and the memory 30 can be controlled to be smaller than the distance between the processor 40 and the memory 30 in the prior art.
It should be noted that, in the process of electrically conducting the processor 40 and the memory 30 by the electrical connector 50, only the electrical connector 50 needs to be fixed to the memory 30 and the processor 40, and no complex wiring process and TSV process are required, so that the fabrication of the integrated circuit structure can be simplified.
Preferably, in the present embodiment, one side of the memory 30 is attached to the wiring layer 20. It is understood that the wiring layer 20 includes a metal conductive layer 21, a contact layer 22 electrically connected to the metal conductive layer 21, and an insulating layer 23 formed of the semiconductor substrate 10. The memory 30 is mounted on the wiring layer 20 and then contacts the contact layer 22 in the wiring layer 20. The contact layer 22 is implemented as a material with a high thermal conductivity, such as copper, so that the memory 30 can dissipate heat through the contact layer 22 after being mounted on the contact layer 22. It will be appreciated that the wiring layer 20 can be formed by a semiconductor process such as etching, developing, plating, etc. on the semiconductor substrate 10.
When the memory 30 is mounted on the semiconductor substrate 10, the memory 30 is electrically connected to the contact layer 22, and thus electrically connected to the metal conductive layer 21. Preferably, the electrical connection 50 electrically connecting the memory 30 and the processor 40 is secured to the memory 30. When the memory 30 and the processor 40 are partially overlapped, the tip of the electrical connection 50 between the memory 30 and the processor 40 is thermocompression bonded (thermo-compression-bonding) to a contact on the processor 40, so that the memory 30 and the processor 40 are fixed to each other and are electrically conductive to each other. More preferably, the electrical connection 50 is formed by thermocompression bonding (thermo-compression-bonding) of respective conductive bumps disposed on the processor 40 and the memory 30.
It should be noted that the metal conductive layer 21 forms a specific circuit structure according to a predetermined design.
In a variant embodiment, the memory 30 and the processor 40, the electrical connection 50 may also be provided on the side of the processor 40 facing the semiconductor substrate 10, and the bottom end of the electrical connection 50 is thermocompression bonded (thermo-compression-bonding) to a contact on the memory 30 when the memory 30 and the processor 40 are partially overlapped.
It is worth mentioning that the sum of the heights of the memory 30 and the electrical connection 50 in the thickness direction of the semiconductor substrate 10 is adapted to the electrical connection 50 provided between the side of the processor 40 facing the semiconductor substrate 10 and the semiconductor substrate 10, so that after the processor 40 is inverted, the electrical connection 50 can be brought into contact with the contact layer 22 on the wiring layer 20, so that it can be subsequently conducted with the wiring layer 20 by thermocompression bonding (thermo-compression-bonding). More importantly, by limiting the height, the levelness of the processor 40 can be effectively ensured, and thus the electrical conductors 100 arranged side by side between the processor 40 and the memory 30 and the electrical connections 50 between the processor 40 and the semiconductor substrate 10 can be brought into contact with the corresponding contacts.
From the foregoing description, those skilled in the art will appreciate that the spacing between the memory 30 and the processor 40 is small compared to prior art connections, and therefore, has the ability to transmit signals with low latency when the integrated circuit structure is powered on.
It will be appreciated by those skilled in the art that since the electrical conduction between the memory 30 and the processor 40 is through the electrical connection 50 in the thickness direction of the semiconductor substrate 10, and the memory 30 and the processor 40 overlap partially, the lateral dimensions of the semiconductor substrate 10 may be reduced, which in turn may result in a reduction in the lateral dimensions of the overall integrated circuit structure. At the same time, the spacing between the memory 40 and the processor 40 is smaller than the prior art spacing between memory and processor, resulting in increased latency resistance and less power consumption for the overall integrated circuit structure. More importantly, compared with the TSV technology in the prior art, the process for forming the integrated circuit structure is simpler and more efficient, and the yield of the integrated circuit structure can be effectively improved.
Preferably, the integrated circuit structure comprises two of the wiring layers 20. Two of the wiring layers 20 are provided on the top side of the semiconductor substrate 10 and the bottom side of the semiconductor substrate 10, respectively.
Preferably, the integrated circuit structure includes a plurality of electrical conductors 300, with a plurality of vias 101 formed between the top and bottom sides of the semiconductor substrate 10. Each of the electrical conductors 300 is electrically connected at both ends thereof to the metal conductive layer 21 in the wiring layer 20 on the top side of the semiconductor substrate 10 and the metal conductive layer 21 in the wiring layer 20 on the bottom side of the semiconductor substrate 10, respectively, after passing through the through holes, to form a specific circuit structure. In this way, the processor 40 can be electrically connected to other semiconductor devices on the back side. In addition, after the memory 40 is mounted on the semiconductor substrate 10, the back surface of the memory 40 is in contact with the contact layer 22 of the wiring layer 20, so that the memory 40 can be conducted away from the memory 40 through the contact layer 22 and the electrical conductor 300 generated during operation of the memory 40, so as to achieve a better heat dissipation effect. That is, the electrical conductor 300 not only serves to electrically connect the processor 40 to other semiconductor devices on the back side, but also allows the memory 40 to dissipate heat better.
Still further, the integrated circuit structure further includes a plurality of conductive bumps 60, wherein the conductive bumps 60 are electrically connected to the metal conductive layer 21, and the conductive bumps 60 protrude from the wiring layer 20 so as to be electrically connected to other devices by thermal-compression-bonding (thermocompression-bonding) later. It should be noted that the memory 30 and the processor 40 are also correspondingly provided with the conductive convex hulls 60, so that after the memory 30 and the processor 40 are overlapped, the conductive convex hulls 60 are bonded by thermocompression (thermo-compression-bonding) to form the electrical connection 50.
It will be appreciated that the devices electrically connected to the processor 40 may extend to the back side of the semiconductor substrate 10 on which the processor 40 is mounted, by means of the electrical connections 50 and the conductive bumps 60.
More importantly, by means of the conductive bump 60, the integrated circuit structure can be electrically connected with other devices in the thickness direction of the semiconductor substrate 10 by means of thermo-compression bonding (thermo-compression bonding), so that the lateral dimension of the semiconductor substrate 10 can be further reduced.
Further, the integrated circuit structure further includes a power board 70, wherein the power board 70 is electrically connected to the memory 30 by the electrical connector 50. Preferably, at least one bypass capacitor 80 is disposed on the power board 70.
Referring to fig. 5-8, according to another aspect of the present invention, there is also provided a method of forming an integrated circuit structure, wherein the method of forming an integrated circuit structure includes the steps of:
s1, inverting at least one memory device 800 with a conductive bump 801 on the top surface and providing a processor device 900 with a conductive bump 901 on the surface, and overlapping the memory device 800 and the processor device 900, wherein a part of the conductive bump 801 on the memory device 800 and a part of the conductive bump 901 on the processor device 900 are in contact and conduction with each other;
s2, thermocompression bonding (thermo-compression-bonding) the conductive bump 901 and the conductive bump 801 in contact with each other;
s3, inverting the processor device 900 with the memory device 800 fixed to a semiconductor medium 700 so that the conductive bump 701 on the semiconductor medium 700 with the conductive bump 701 on the top surface and the conductive bump 901 which is not shielded by the memory device 800 and is located on the processor device 900 are formed; and
s4, thermocompression bonding (thermo-compression-bonding) the conductive bump 901 and the conductive bump 701 contacting each other, so that the memory device 800, the processor device 900, and the semiconductor medium 700 form the memory 30, the processor 40, and the semiconductor substrate 10 in the integrated circuit structure described above, respectively.
It should be noted that the semiconductor medium 700 is pre-arranged with the wiring layer 20. It should be noted that after the conductive bump 901 and the conductive bump 801 are thermally compression-bonded (thermo-compression-bonding) between the processor 40 and the memory 30, the electrical connection 50 between the processor 40 and the memory 30 is formed. After thermocompression bonding (thermo-compression-bonding) of the conductive bumps 901 contacting the conductive bumps 701 with the conductive bumps 701, the electrical connections 50 in the integrated circuit structure between the processor 40 and the semiconductor medium 10 will be formed.
The method for forming the integrated circuit structure further comprises the following steps:
s5, providing a bearing plate 500 with a groove 501;
s6, placing the processor device 900 in the groove 501 in a manner that the conductive protrusions 901 face upwards so as to prevent the processor device 900 from shaking during the manufacturing process;
and S7, after the step S3 is completed, removing the bearing plate.
It will be appreciated by persons skilled in the art that the embodiments of the invention described above and shown in the drawings are by way of example only and are not limiting. The advantages of the present invention have been fully and effectively realized. The functional and structural principles of the present invention have been shown and described in the examples and embodiments of the invention may be modified or practiced without departing from the principles described.
Claims (10)
1. A method of forming an integrated circuit structure, comprising the steps of:
s1, inverting at least one memory device with a conductive bump on the top surface and a processor device with a conductive bump on the surface, and enabling the memory device and the processor device to be partially overlapped, wherein part of the conductive bump on the memory device and part of the conductive bump on the processor device are mutually contacted and conducted;
s2, thermocompression bonding the conductive bump and the conductive bump which are in contact with each other;
s3, inverting the processor device with the memory device fixed on a semiconductor medium so that the conductive boss on the semiconductor medium with the conductive boss arranged on the top surface and the conductive boss which is not blocked by the memory device and is positioned on the processor device are formed; and
s4, thermocompression bonding the conductive bump and the conductive boss which are in contact with each other, so that the memory device, the processor device and the semiconductor medium respectively form a memory, a processor and a semiconductor substrate in the integrated circuit structure, and a gap with a preset size is formed between the processor and the semiconductor substrate.
2. The method of forming an integrated circuit structure of claim 1, wherein the semiconductor medium is pre-arranged with a wiring layer.
3. The method of forming an integrated circuit structure of claim 1, further comprising the steps of:
s5, providing a bearing plate with a groove;
s6, placing the processor device in the groove in a mode that the conductive protrusion faces upwards; and
and S7, after the step S3 is completed, removing the bearing plate.
4. The method according to claim 1, wherein a sum of heights of the memory and the thermocompression-bonded conductive bump and the conductive bump in a thickness direction of the semiconductor substrate is adapted to a sum of heights of the conductive bump and the conductive bump provided between a side of the processor facing the semiconductor substrate and the semiconductor substrate in the thickness direction of the semiconductor substrate.
5. The method of forming an integrated circuit structure of claim 1, wherein a plurality of said conductive bumps and a plurality of said conductive bumps are spaced apart.
6. The method of forming an integrated circuit structure according to claim 1, wherein the integrated circuit structure comprises two wiring layers symmetrically formed on both sides of the semiconductor substrate.
7. The method of forming an integrated circuit structure of claim 6, wherein the integrated circuit structure comprises a plurality of electrical conductors, a plurality of vias are formed between a top side and a bottom side of the semiconductor substrate, and each of the electrical conductors is electrically connected at both ends to the wiring layer on the top side of the semiconductor substrate and the wiring layer on the bottom side of the semiconductor substrate, respectively, after passing through the vias, to form a specific circuit structure.
8. The method of claim 1, further comprising a power board, wherein the power board is electrically connected to the memory.
9. The method of claim 8, wherein at least one bypass capacitor is disposed on the power board.
10. The method of claim 1, wherein the processor is implemented as a microprocessor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110273795.3A CN113066732B (en) | 2021-03-15 | 2021-03-15 | Method for forming integrated circuit structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110273795.3A CN113066732B (en) | 2021-03-15 | 2021-03-15 | Method for forming integrated circuit structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113066732A CN113066732A (en) | 2021-07-02 |
| CN113066732B true CN113066732B (en) | 2024-04-09 |
Family
ID=76560743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110273795.3A Active CN113066732B (en) | 2021-03-15 | 2021-03-15 | Method for forming integrated circuit structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113066732B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151337A (en) * | 2011-12-07 | 2013-06-12 | 台湾积体电路制造股份有限公司 | Test probing structure |
| CN103258806A (en) * | 2013-05-08 | 2013-08-21 | 日月光半导体制造股份有限公司 | Semiconductor package structure with bridging structure and manufacturing method thereof |
| CN104253115A (en) * | 2013-06-28 | 2014-12-31 | 英特尔公司 | Underfill material flow control for reduced die-to-die spacing in semiconductor packages |
| CN107644839A (en) * | 2017-08-31 | 2018-01-30 | 长江存储科技有限责任公司 | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090212420A1 (en) * | 2008-02-22 | 2009-08-27 | Harry Hedler | integrated circuit device and method for fabricating same |
-
2021
- 2021-03-15 CN CN202110273795.3A patent/CN113066732B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151337A (en) * | 2011-12-07 | 2013-06-12 | 台湾积体电路制造股份有限公司 | Test probing structure |
| CN103258806A (en) * | 2013-05-08 | 2013-08-21 | 日月光半导体制造股份有限公司 | Semiconductor package structure with bridging structure and manufacturing method thereof |
| CN104253115A (en) * | 2013-06-28 | 2014-12-31 | 英特尔公司 | Underfill material flow control for reduced die-to-die spacing in semiconductor packages |
| CN107644839A (en) * | 2017-08-31 | 2018-01-30 | 长江存储科技有限责任公司 | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113066732A (en) | 2021-07-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9324696B2 (en) | Package-on-package devices, methods of fabricating the same, and semiconductor packages | |
| US9583430B2 (en) | Package-on-package device | |
| KR102198858B1 (en) | Semiconductor package stack structure having interposer substrate | |
| US9041205B2 (en) | Reliable microstrip routing for electronics components | |
| US8115291B2 (en) | Semiconductor package | |
| US7209366B2 (en) | Delivery regions for power, ground and I/O signal paths in an IC package | |
| US20150022985A1 (en) | Device-embedded package substrate and semiconductor package including the same | |
| US20130077374A1 (en) | Stacked semiconductor apparatus, system and method of fabrication | |
| US20120199981A1 (en) | Semiconductor device and method of fabricating the semiconductor device | |
| US20180158809A1 (en) | Semiconductor memory device including stacked chips and memory module having the same | |
| US10083934B2 (en) | Multi-chip package with interconnects extending through logic chip | |
| CN104253115A (en) | Underfill material flow control for reduced die-to-die spacing in semiconductor packages | |
| JP2012503887A (en) | Mounted processor I / O architecture | |
| CN103620774A (en) | Flip-chip, face-up and face-down wirebond combination package | |
| TW201324730A (en) | Semiconductor stack packages and methods of fabricating the same | |
| KR20120133057A (en) | Semiconductor package and fabrication method of the same | |
| CN112928101A (en) | Reconfigurable wafer assembly | |
| US8026616B2 (en) | Printed circuit board, semiconductor package, card apparatus, and system | |
| US20050258533A1 (en) | Semiconductor device mounting structure | |
| US8169066B2 (en) | Semiconductor package | |
| TW201325327A (en) | Method and apparatus for connecting inlaid chip into printed circuit board | |
| CN114400219A (en) | Semiconductor device, method of manufacturing the same, package device, and electronic apparatus | |
| CN113066732B (en) | Method for forming integrated circuit structure | |
| US7112468B2 (en) | Stacked multi-component integrated circuit microprocessor | |
| CN111863780A (en) | Packaging structure and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |