CN113055326B - Amplitude shift keying demodulation circuit based on sampling subtraction method - Google Patents
Amplitude shift keying demodulation circuit based on sampling subtraction method Download PDFInfo
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Abstract
The invention relates to an amplitude shift keying demodulation circuit based on a sampling subtraction method, which comprises an envelope detection circuit for extracting envelope of an input signal, a sampling subtraction module for eliminating energy carrier interference, a comparator module for acquiring output data and a finite-state machine module; after an amplitude shift keying modulation signal Vin interfered by an energy carrier is input into the envelope detection circuit to extract an envelope signal, a sampling signal with the same frequency as the energy carrier interference is used for sampling the envelope signal through the sampling subtraction module and carrying out difference before and after the sampling signal, the energy carrier interference is eliminated, and an amplitude shift keying data change signal is obtained; the amplitude shift keying data change signal output by the sampling subtraction module obtains amplitude shift keying data Dout through the comparator module and the finite-state machine module. The power consumption of the PCI and the control circuit can be effectively eliminated.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of analog integrated circuits, in particular to an amplitude shift keying demodulation circuit based on a sampling subtraction method.
[ background of the invention ]
Age-related Macular Degeneration (AMD) and Retinitis Pigmentosa (RP) are among the common causes of blindness in blind patients. Both types of patients are blind due to retinal degeneration, but most of the nerve cells in the eye remain intact. With the rapid development of biomedical implantable integrated circuits in recent years, it has become possible to restore a patient's vision using an implantable retinal prosthesis. In order to power the implanted device and communicate with the external coil, wireless energy and data telemetry, and in particular dual frequency telemetry links (1 MHz for energy and 13.56MHz for data) with different frequencies, have been widely used in most retinal prostheses. Amplitude Shift Keying (ASK) is one of the popular modulation schemes due to its simple implementation to clock and data recovery hardware. However, due to mutual inductance between the two link coils, the received signal will be disturbed by energy carriers (power-carrier interference PCI). As a result, a large PCI inevitably leads to a reduction in the signal-to-interference ratio (SIR) of the received data signal. Simulations show that in practical situations the PCI amplitude can be up to 3 times the ASK carrier amplitude. Therefore, it is important to implement ASK demodulators with good interference rejection capabilities in retinal prostheses.
Fig. 1 is a diagram illustrating the demodulation effect of a prior art amplitude shift keying demodulator under the condition of containing PCI. As shown in fig. 1, the existing ASK demodulator in retinal prostheses is mainly based on an envelope detector and a comparator, and the envelope of ASK signals is detected by the envelope detector and then compared with the average value of the envelope to restore data, which has obvious advantages of simplicity and low power consumption. However, the coupled large PCI will lower SIR, resulting in a higher Bit Error Rate (BER) under large PCI interference. The conventional approach to solve the above problem is to add a filter to filter the PCI from the frequency domain. However, since the PCI and the data carrier frequency bands are very close, a high order filter is required to filter out the PCI, which greatly increases power consumption.
[ summary of the invention ]
The invention aims to provide an amplitude shift keying demodulation circuit capable of effectively eliminating PCI and controlling circuit power consumption.
In order to achieve the above object, the technical solution adopted by the present invention is an amplitude shift keying demodulation circuit based on a sampling subtraction method, wherein the amplitude shift keying demodulation circuit comprises an envelope detection circuit for extracting an envelope of an input signal, a sampling subtraction module for eliminating energy carrier interference, a comparator module for acquiring output data, and a finite state machine module; after an amplitude shift keying modulation signal Vin interfered by an energy carrier is input into the envelope detection circuit to extract an envelope signal, a sampling signal with the same frequency as the energy carrier interference is used for sampling the envelope signal through the sampling subtraction module and carrying out difference before and after the sampling signal, the energy carrier interference is eliminated, and an amplitude shift keying data change signal is obtained; the amplitude shift keying data change signal output by the sampling subtraction module obtains amplitude shift keying data Dout through the comparator module and the finite-state machine module.
Preferably, the sampling subtraction module is formed by connecting a first sampling subtraction circuit and a second sampling subtraction circuit in parallel; the first sampling subtraction circuit and the second sampling subtraction circuit have four working phases which are reset and are used for first sampling, first holding, second sampling and subtraction of two sampling results respectively; the first sampling subtraction circuit and the second sampling subtraction circuit work in two different working phases, and the sampling subtraction result Vsub is alternately output, so that data loss during resetting and first sampling is avoided.
Preferably, the sampling signal with the same frequency as the energy carrier interference is a source clock clkin recovered by the energy carrier interference signal, so as to ensure that the amplitude shift keying demodulation circuit and the energy carrier interference keep synchronous; generating signals ph11, ph12, ph21, ph22, ph31 and ph32 for controlling switch closure and digital logic circuit action on the basis of recovering a source clock clkin, wherein ph31 is ph11+ ph21, ph32 is ph12+ ph22, and the signals are triggered at the falling edge of the source clock clkin; the sampling subtraction module also comprises a switch controlled to be closed by the signal ph22 being true and a switch controlled to be closed by the signal ph12 being true; the first sampling subtraction circuit is connected in series with a switch which is controlled to be closed by the signal ph22, the second sampling subtraction circuit is connected in series with a switch which is controlled to be closed by the signal ph12, and then the two series circuits are connected in parallel; the first sampling subtraction circuit and the second sampling subtraction circuit comprise switched capacitors and fully differential operational amplifiers, the switched capacitors comprise four switches which are controlled to be closed by the signal ph11, two switches which are controlled to be closed by the signal ph21, two switches which are controlled to be closed by the signal ph31, four switches which are controlled to be closed by the signal ph32, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, wherein the first capacitor is the third capacitor, and the second capacitor is the fourth capacitor; the second capacitor is connected with the negative input end and the positive output end of the fully differential operational amplifier, and the fourth capacitor is connected with the positive input end and the negative output end of the fully differential operational amplifier; when the first sampling subtraction circuit is reset and carries out sampling for the first time, the switch controlled by the signal ph11 being true is closed, the switch controlled by the signal ph31 being true is closed, the envelope output signal Venv of the envelope detector and half Vcom of the direct-current power supply voltage are sampled to the lower plates of the first capacitor and the third capacitor, the Vcom is connected to the upper plates of the first capacitor and the third capacitor, and the second capacitor and the fourth capacitor are in a short circuit reset state; when the first sampling subtraction circuit is used for holding for the first time, the switch controlled by the signal ph12 being true is closed, the switch controlled by the signal ph32 being true is closed, the lower plates of the first capacitor and the third capacitor are connected to Vcom, and charges in the first capacitor and the third capacitor are transferred to two ends of the second capacitor and the fourth capacitor; when the first sampling subtraction circuit samples for the second time, the switch controlled by the signal ph21 being true is closed, and the switch controlled by the signal ph31 being true is closed, the envelope output signals Venv and Vcom of the envelope detector are sampled onto the first capacitor and the third capacitor, the sampled capacitors are exchanged compared with the sampled capacitors in the previous period, and meanwhile, the second capacitor and the fourth capacitor are not reset, namely, the charges in the previous period are still stored on the second capacitor and the fourth capacitor; when the two sampling results of the first sampling subtraction circuit are subtracted, a switch controlled by the signal ph22 being true and a switch controlled by the signal ph32 being true are closed, charges collected on the first capacitor and the third capacitor are transferred to the second capacitor and the fourth capacitor during the second sampling, and a sampling subtraction result Vsub is output through the switch controlled by the signal ph22 being true; the second sampling subtraction circuit and the first sampling subtraction circuit are different in working phase by two working phases, and when the first sampling subtraction circuit is in a first holding state, a switch which is controlled to be true through a signal ph12 outputs a sampling subtraction result Vsub.
Preferably, the analog signal of the subtraction result Vsub is converted into two-bit digital signals Dflag [1], Dflag [0] by the comparator module, and the amplitude shift keying data Dout is demodulated and output by the finite state machine.
Preferably, the comparator module is formed by connecting a first dynamic comparator and a second dynamic comparator in parallel, and outputs a two-bit digital signal; the positive inputs of the first dynamic comparator and the second dynamic comparator are connected with the output Vsub of the sampling subtraction circuit, and the negative inputs are respectively connected with two reference voltages Vref + Delta and Vref-Delta, so that two working states of comparison and latching are divided, and the two working states are kept synchronous with the switching of the working states of the sampling subtraction module.
Preferably, the first dynamic comparator and the second dynamic comparator are composed of a pre-amplification stage module and a latch module; the pre-amplification stage module comprises four switches controlled to be closed by the signal of ph31, two switches controlled to be closed by the signal of ph32, a seventh capacitor and an eighth capacitor, two working phases are reset and compared in total, and the working phases are kept synchronous with the working state switching of the sampling subtraction module; when the pre-amplification stage module of the first dynamic comparator is reset, the four switches controlled by the ph31 signal as true are closed, the reference voltage Vref + Δ is sampled by the seventh capacitor, and the eighth capacitor is reset; when the preamplification stage module of the first dynamic comparator is used for comparison, two switches controlled by the ph32 signal to be true are closed, the sampling subtraction result Vsub is sampled onto a seventh capacitor, and the difference between the sampling subtraction result Vsub and the reference voltage Vref + Delta is amplified by seventh capacitor/eighth capacitor times; when the next ph31 signal is true, the latch module of the first dynamic comparator starts to work, the result of the closing of the switch controlled by the ph32 signal is converted into a digital signal Dflag [1] through the latch module of the first dynamic comparator, and the pre-amplification stage module of the first dynamic comparator is reset; when the ph32 signal is true, the latch module of the first dynamic comparator does not work, and Dflag [1] is locked; when the pre-amplification stage module of the second dynamic comparator is reset, the four switches controlled by the ph31 signal as true are closed, the reference voltage Vref-Delta is sampled by the seventh capacitor, and the eighth capacitor is reset; when the pre-amplification stage module of the second dynamic comparator compares, two switches controlled by the ph32 signal being true are closed, the sampling subtraction result Vsub is sampled to a seventh capacitor, and the difference between the sampling subtraction result Vsub and the reference voltage Vref- Δ is amplified by a factor of seventh capacitor/eighth capacitor; when the next ph31 signal is true, the latch module of the second dynamic comparator starts to work, the result of the closing of the switch controlled by the ph32 signal is converted into a digital signal Dflag [0] through the latch module of the second dynamic comparator, and the pre-amplification stage module of the second dynamic comparator is reset; when the ph32 signal is true, the latch module of the second dynamic comparator is not activated and Dflag [0] is locked.
Preferably, the finite state machine module is composed of a three-input and gate, a three-input or gate, a two-input and gate, a two-input or gate and a D flip-flop; the two-bit digital output Dflag [1] and Dflag [0] of the comparator module is used as a sign of switching state, and is accessed to the inputs of a three-input AND gate and a three-input OR gate together with the non-input of the previous state, the output of the three-input OR gate and the input of the previous state are connected with the inputs of a two-input AND gate, the outputs of the two-input AND gate and the three-input AND gate are connected with the inputs of the two-input OR gate, the outputs of the two-input OR gate are connected with the input of a D trigger and are simultaneously used as the output of the finite state machine module, namely amplitude shift keying data Dout; the positive output of the D flip-flop is the last state and the negative output is the not of the last state, and the D flip-flop updates the state when the ph31 signal is true.
Preferably, the envelope detection circuit comprises a source follower, a differential operational amplifier, a 1: X current mirror, a voltage stabilizing capacitor and a leakage resistor; the voltage stabilizing capacitor is formed by connecting a fifth capacitor and a sixth capacitor in series, the leakage resistor is formed by connecting a first resistor and a second resistor in series, the voltage stabilizing capacitor is connected with the leakage resistor in parallel, the first ends of the first resistor and the fifth capacitor of the parallel circuit are connected with the output Venv of the envelope detection circuit, the first ends of the second resistor and the sixth capacitor of the parallel circuit are grounded, and the second ends of the second resistor and the sixth capacitor of the parallel circuit are connected with the positive input end of the differential operational amplifier; the source follower is used for improving the common-mode value of the input signal and plays a role of a voltage buffer; the negative input end of the differential operational amplifier is connected with the output of the source follower, and the output of the differential operational amplifier is connected with the input of the 1: X current mirror; the output of the 1: X current mirror is taken as the output Venv of the envelope detector.
Preferably, the source follower is composed of a first field effect transistor and a second field effect transistor of two P-type metal oxide semiconductor field effect transistors connected in series, a gate of the second field effect transistor is connected with an input signal, a drain of the second field effect transistor is grounded, and a source of the second field effect transistor is connected with a drain of the first field effect transistor and a negative input of the differential operational amplifier; the differential operational amplifier consists of five P-type metal oxide semiconductor field effect transistors; the 1: X current mirror consists of two P-type metal oxide semiconductor field effect transistors.
Compared with the prior art, the invention has the following beneficial effects: the PCI is eliminated by a sampling subtraction method, and the traditional method using a high-order filter is replaced, so that the PCI can be effectively eliminated, and meanwhile, the power consumption is well controlled.
[ description of the drawings ]
FIG. 1 is a diagram illustrating the demodulation effect of a prior art amplitude shift keying demodulator under the condition of containing PCI;
FIG. 2 is a schematic diagram of an overall framework of an amplitude shift keying demodulation circuit based on a sampling subtraction method;
FIG. 3 is a schematic diagram of an envelope detector of an amplitude shift keying demodulation circuit based on a sampling subtraction method;
FIG. 4 is a schematic diagram of a sampling subtraction circuit of an amplitude shift keying demodulation circuit based on a sampling subtraction method;
FIG. 5 is a schematic diagram of an operational amplifier used in a sampling subtraction circuit of an amplitude shift keying demodulation circuit based on a sampling subtraction method;
FIG. 6 is a schematic diagram of an amplitude shift keying demodulation circuit comparator module based on a sampling subtraction method;
FIG. 7 is a schematic diagram of a dynamic comparator for an amplitude shift keying demodulator module based on a sampling subtraction method;
FIG. 8 is a schematic diagram of a pre-amplifier stage circuit structure for a dynamic comparator of an amplitude shift keying demodulation circuit comparator module based on a sampling subtraction method;
FIG. 9 is a schematic diagram of a latch structure for a dynamic comparator of an amplitude shift keying demodulator circuit comparator module based on a sampling subtraction method;
FIG. 10 is a state transition diagram of a finite state machine for an amplitude shift keying demodulation circuit based on a sample subtraction method;
FIG. 11 is a schematic diagram of a finite state machine of an amplitude shift keying demodulation circuit based on a sampling subtraction method;
FIG. 12 is a timing diagram of the operation of an amplitude shift keying demodulation circuit based on a sampling subtraction method;
fig. 13 is a schematic diagram of a simulation result of an amplitude shift keying demodulation circuit based on a sampling subtraction method when the PCI is a triple data carrier amplitude.
The reference numerals and components referred to in the drawings are as follows: 1. the circuit comprises an envelope detection circuit 11, a source follower 12, a differential operational amplifier 13, a 1: X current mirror 14, a voltage stabilizing capacitor 15, a leakage resistor 2, a sampling subtraction module 21, a first sampling subtraction circuit 211, a switch capacitor 212, a fully differential operational amplifier 22, a second sampling subtraction circuit 3, a comparator module 31, a first dynamic comparator 311, a pre-amplification stage module 312, a latch module 32, a second dynamic comparator 4 and a finite state machine module.
[ detailed description ] embodiments
The invention is further described with reference to the following examples and with reference to the accompanying drawings.
Example 1
The embodiment realizes an amplitude shift keying demodulation circuit based on a sampling subtraction method.
Fig. 2 is a schematic diagram of an overall framework of an amplitude shift keying demodulation circuit based on a sampling subtraction method. As shown in fig. 2, the amplitude shift keying demodulation circuit based on the sampling subtraction method in this embodiment includes: envelope detection circuit 1, sample subtraction module 2, comparator module 3 and finite state machine module 4.
Fig. 3 is a schematic structural diagram of an envelope detector of an amplitude shift keying demodulation circuit based on a sampling subtraction method. As shown in fig. 3, the envelope detection circuit 1 of the amplitude shift keying demodulation circuit based on the sampling subtraction method in this embodiment is composed of a source follower 11, a differential operational amplifier 12, a 1: X current mirror 13, a voltage stabilizing capacitor 14, and a leakage resistor 15. The source follower 11 is composed of two P-type metal oxide semiconductor field effect transistors (PMOS for short) M2 and M3 connected in series, and is used to raise the common-mode value of the input signal, and to function as a voltage buffer. The gate of M3 is connected to the input signal, the drain is connected to ground, and the source is connected to the drain of M2 and the negative input of differential operational amplifier 12. The differential operational amplifier 12 is composed of five transistors M6, M7, M8, M9 and M10, a negative input end is connected with an output of the source follower 11, a positive input end is connected with the leakage resistor 15 and the voltage stabilizing capacitor 14, and an output is connected with an input of the 1: X current mirror 13. The 1: X current mirror 13 is composed of M11 and M12, and the output of the 1: X current mirror 13 is used as the output of the envelope detector 1, and is connected to one end of the voltage-stabilizing capacitor C1 and the leakage resistor R1. The voltage-stabilizing capacitor 14 is formed by connecting C1 and C2 in series, and the leakage resistor 15 is formed by connecting R1 and R2 in series. The voltage stabilizing capacitor 14 is connected in parallel with the leakage resistor 15, one end of the voltage stabilizing capacitor is connected with the output of the 1: X current mirror 13, and the other end of the voltage stabilizing capacitor is grounded. The other ends of the leakage resistor R2 and the voltage-stabilizing capacitor C2 are connected to the positive input end of the differential operational amplifier 12. Assuming that the output of the envelope detector 1 is constant, the voltage at the positive input terminal of the differential operational amplifier 12 remains constant after being divided by R1 and R2, and the current of the right branch is also constant. When the input signal becomes larger, the voltage at the negative input terminal of the differential operational amplifier 12 becomes larger, the current flowing through M7 in the left branch becomes larger, and the current of M9 still keeps the same as that in the right branch, I7> I9, and the current in M11 is the difference between the currents of M7 and M9. After the amplification of the 1: X current mirror 13, the M12 current is X times of that in M11, and the voltage stabilizing capacitor 14 is charged, so that the output of the envelope detector 1 is increased. Similarly, when the input signal becomes smaller, the current of M7 becomes smaller, and at this time, M11 will have no current, i.e. no charge, to charge the voltage stabilizing capacitor 14. At which point the charge will be discharged to ground along the leakage resistor 15, completing the reduction of the output of the envelope detector 1. Since the common-mode voltages of the input and envelope outputs of the amplifier are not the same, the voltage-stabilizing capacitor 14 and the leakage resistor 15 are split into R1, R2, C1 and C2, and the relationship between the output of the envelope detector 1 and the common-mode voltage at the positive input of the differential operational amplifier 12 is Venv/Vip (R1+ R2)/R2.
Fig. 4 is a schematic diagram of a sampling subtraction circuit structure of an amplitude shift keying demodulation circuit based on a sampling subtraction method. As shown in fig. 4, in the amplitude shift keying demodulation circuit based on the sample subtraction method according to this embodiment, the sample subtraction module 2 is formed by connecting a first sample subtraction circuit 21 in series with a switch controlled to be closed by the signal ph22 being true, and connecting a second sample subtraction circuit 22 in series with a switch controlled to be closed by the signal ph12 being true, and then connecting the two series circuits in parallel. The first sampling subtraction circuit 21 and the second sampling subtraction circuit 22 include a switched capacitor 211 and a fully differential operational amplifier 212. The switched capacitor 211 comprises 12 switches (four closed by true control of a ph11 signal, two closed by true control of a ph21 signal, two closed by true control of a ph31 signal, and four closed by true control of a ph32 signal) and 4 capacitors (C1, C2, C3, and C4), wherein the capacitor C1 is C3, and the capacitor C2 is C4. C2 is connected to the negative and positive inputs of the fully differential operational amplifier 212 and C4 is connected to the positive and negative outputs of the fully differential operational amplifier 212. The first sampling subtraction circuit 21 and the second sampling subtraction circuit 22 have four working phases in common, which are reset and perform first sampling (ph11/ph31, i.e., the switch closed under the control of the ph11 signal is true and the switch closed under the control of the ph31 signal is true), first holding (ph12/ph32, i.e., the switch closed under the control of the ph12 signal is true and the switch closed under the control of the ph32 signal is true), second sampling (ph21/ph31, i.e., the switch closed under the control of the ph21 signal is true and the switch closed under the control of the ph31 signal is true), and two-time sampling result subtraction (ph22/ph32, i.e., the switch closed under the control of the ph22 signal is true and the switch closed under the control of the ph32 signal is true). When the first sampling subtraction circuit 21 is reset and sampling for the first time, the output Venv and Vcom signals (direct current signals, which are set to be half of the power supply voltage) of the envelope detector 1 are sampled to the lower plates of C1 and C3, and Vcom is connected to the upper plates of C1 and C3; meanwhile, both C2 and C4 are in the short reset state. When the first sampling subtraction circuit 21 holds for the first time, the lower plates of C1 and C3 are connected to Vcom, and the charges in C1 and C3 are transferred to both ends of C2 and C4. Likewise, the first sample subtraction circuit 21 samples the envelope detector 1 output and Vcom onto C1 and C3 at the second sampling; the sampled capacitances are interchanged compared to the previous cycle, while C2 and C4 are not reset, i.e., the charge of the previous cycle remains on C2 and C4. The first sampling subtraction circuit 21 transfers charges to C2 and C4 when the two sampling results are subtracted. When the result of sampling the output signal of the envelope detector 1 in the switch-on state (reset and first sampling) in which the signal ph11 is true is denoted by V1 and the result of sampling the output signal of the envelope detector 1 in the switch-on state (second sampling) in which the signal ph21 is true is denoted by V2, the difference output result of Vsub _ p-Vsub _ n-C1/C2 (V2-V1) can be obtained in the switch-on state (subtraction of the two sampling results) in which the signal ph22 is true. After the switch closed state (subtracting the results of two sampling) controlled by the signal ph22 is true, the switch closed state (reset and first sampling) controlled by the signal ph11 is returned again, the last data is cleared, and the next sampling subtraction is started.
The two parallel sample subtraction circuits, i.e., the first sample subtraction circuit 21 and the second sample subtraction circuit 22, are provided to solve data loss due to reset and reset at the time of first sampling. By providing two sampling subtraction circuits, i.e., the first sampling subtraction circuit 21 and the second sampling subtraction circuit 22 differ by one duty cycle (two duty phases), the sampling subtraction results can be obtained alternately, thereby avoiding data loss.
Fig. 5 is a schematic structural diagram of an operational amplifier used in a sampling subtraction circuit of an amplitude shift keying demodulation circuit based on a sampling subtraction method. As shown in fig. 5, the present embodiment is an amplitude shift keying demodulation circuit based on a sample subtraction method, and the sample subtraction circuit is a fully differential operational amplifier 212 used by the first sample subtraction circuit 21 and the second sample subtraction circuit 22.
Fig. 6 is a schematic diagram of an amplitude shift keying demodulation circuit comparator module structure based on a sampling subtraction method. As shown in fig. 6, the comparator module 3 of the amplitude shift keying demodulation circuit based on the sample subtraction method in this embodiment is formed by connecting two dynamic comparators, i.e., a first dynamic comparator 31 and a second dynamic comparator 32 in parallel, a positive input terminal of the amplitude shift keying demodulation circuit based on the sample subtraction method in this embodiment is connected to a sample subtraction result Vsub, a negative input terminal of the first dynamic comparator 31 is connected to + Δ, and a negative input terminal of the second dynamic comparator 32 is connected to- Δ. The result of the sample subtraction is divided into a high voltage, a low voltage and a zero voltage, corresponding to data from 0 to 1, from 1 to 0 and 11, 00, respectively. After passing through a comparator, the signal is converted into a 2-bit digital signal Dflag [1:0] (11, 00, 01). After simulation verification, Δ is generated by an external circuit and needs to be controlled above zero voltage and below high voltage to ensure the correctness of data comparison.
Fig. 7 is a schematic diagram of an amplitude shift keying demodulation circuit comparator module structure based on a sampling subtraction method. As shown in fig. 7, the first dynamic comparator 31 and the second dynamic comparator 32 of the amplitude shift keying demodulation circuit based on the sample subtraction method according to the present embodiment are composed of a pre-amplifier stage module 311 and a latch module 312. The pre-amplifier stage module 311 is composed of a switched capacitor and an operational amplifier. Vrefp, Vrefn are differential signals of + Δ, respectively, and Vsub _ p, Vsub _ n are differential signals of the sampling subtraction result Vsub, respectively. When the switch controlled by the ph31 signal true is closed, the reference voltage + Δ is sampled onto C1 and C2 is reset; with the switch closed, which is true controlled by the ph32 signal, the sample subtraction result Vsub is sampled at C1, and Vsub- Δ is amplified by a factor of C1/C2. When the next ph31 signal is true, the latch module 312 starts working, and the result of the closing of the previous switch controlled by the ph32 signal is converted into the digital signal Dflag [1] through the latch module 312, and the pre-amplifier stage module 311 is reset; when the ph32 signal is true, latch module 312 is disabled and the previous Dflag is locked.
Fig. 8 is a schematic diagram of a circuit structure of a pre-amplifier stage used in a dynamic comparator of an amplitude shift keying demodulation circuit comparator module based on a sampling subtraction method. As shown in fig. 8, the present embodiment is an operational amplifier used in the pre-amplifier stage module 311 of the amplitude shift keying demodulation circuit based on the sampling subtraction method.
Fig. 9 is a schematic diagram of a latch structure used by a dynamic comparator of an amplitude shift keying demodulation circuit comparator module based on a sampling subtraction method. As shown in fig. 9, the present embodiment is a schematic structural diagram of an amplitude shift keying demodulation circuit latch module 312 based on a sampling subtraction method. When clk is high, the Dflag changes with the input change, and when vip > vin, the Dflag is a digital "1", whereas the other way around is a digital "0". When the clk is low level, the Dflag keeps the previous state unchanged, and the locking effect is achieved.
Fig. 10 is a state transition diagram of an amplitude shift keying demodulation circuit finite state machine based on a sampling subtraction method. As shown in fig. 10, the present embodiment is a state transition diagram of an amplitude shift keying demodulation circuit finite state machine 4 based on a sampling subtraction method. When the last digit is "0", it becomes "1" when dtlag is 11, and remains "0" when dtlag is 01 or 00; when the last number is "1", it becomes "0" when Dflag 00 is encountered, and "1" is maintained when Dflag 01 or 11 is encountered.
Fig. 11 is a schematic diagram of a finite-state machine structure of an amplitude shift keying demodulation circuit based on a sampling subtraction method. As shown in fig. 11, a schematic structural diagram of the finite-state machine 4 of the amplitude shift keying demodulation circuit based on the sampling subtraction method according to this embodiment is shown. The operating state of the latch module 312 remains the same, switching state when the ph31 signal is true, and holding state when the ph32 signal is true.
Fig. 12 is a schematic diagram of the operation timing sequence of an amplitude shift keying demodulation circuit based on a sampling subtraction method. As shown in fig. 12, the working timing diagram of the amplitude shift keying demodulation circuit based on the sampling subtraction method in this embodiment is shown. And the source clock clkin is recovered through the PCI, so that the working time of the circuit is ensured to be synchronous with the PCI. Then, ph11, ph12, ph21, ph22, ph31 and ph32 signals are generated through a digital circuit, wherein ph31 is ph11+ ph21, and ph32 is ph12+ ph22, and the signals are triggered at the falling edge of clkin.
Fig. 13 is a schematic diagram of a simulation result of an amplitude shift keying demodulation circuit based on a sampling subtraction method when the PCI is a triple data carrier amplitude. As shown in fig. 13, in the amplitude shift keying demodulation circuit based on the sampling subtraction method according to this embodiment, after the amplitude shift keying modulation signal contains PCI 3 times as much as the data carrier, the demodulator can still correctly demodulate data, and has good anti-interference capability.
In the present embodiment, the envelope detection circuit 1 extracts the envelope of the input signal, and the envelope signal is sampled and subtracted from the PCI signal in the sampling subtraction module 2 using the same sampling signal as the PCI frequency. After sampling subtraction, PCI interference can be effectively eliminated, and meanwhile, the change condition of data is obtained. And the analog signal obtained by subtracting is converted into a digital signal with 2 bits by using a comparator module 3, and finally demodulated data is obtained by a finite-state machine 4. The whole process does not use a high-order filter, and can effectively demodulate data from the amplitude shift keying modulation signal containing large interference.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and additions can be made without departing from the principle of the present invention, and these should also be considered as the protection scope of the present invention.
Claims (9)
1. An amplitude shift keying demodulation circuit based on a sampling subtraction method is characterized in that: the amplitude shift keying demodulation circuit comprises an envelope detection circuit (1) for extracting envelope of an input signal, a sampling subtraction module (2) for eliminating energy carrier interference, a comparator module (3) for acquiring output data and a finite state machine module (4); after an amplitude shift keying modulation signal Vin interfered by an energy carrier is input into the envelope detection circuit (1) to extract an envelope signal, a sampling signal with the same frequency as the energy carrier interference is used for sampling the envelope signal through the sampling subtraction module (2) and carrying out difference on the sampling signal and the envelope signal, so that the energy carrier interference is eliminated, and an amplitude shift keying data change signal is obtained; restoring a source clock clkin through an energy carrier interference signal to ensure that the amplitude shift keying demodulation circuit and the energy carrier interference keep synchronous; generating ph11, ph12, ph21, ph22, ph31 and ph32 signals for controlling switch closure and digital logic circuit action on the basis of recovering a source clock clkin, wherein ph31 is ph11+ ph21, and ph32 is ph12+ ph22, and the signals are triggered at a falling edge of the source clock clkin; the amplitude shift keying data change signal output by the sampling subtraction module (2) obtains amplitude shift keying data Dout through the comparator module (3) and the finite-state machine module (4).
2. The amplitude shift keying demodulation circuit based on the sampling subtraction method as claimed in claim 1, wherein: the sampling subtraction module (2) is formed by connecting a first sampling subtraction circuit (21) and a second sampling subtraction circuit (22) in parallel; the first sampling subtraction circuit (21) and the second sampling subtraction circuit (22) have four working phases which are reset and are used for first sampling, first holding, second sampling and subtraction of two sampling results respectively; the first sampling subtraction circuit (21) and the second sampling subtraction circuit (22) work in a different phase, and output sampling subtraction results Vsub alternately, so that data loss during resetting and first sampling is avoided.
3. The amplitude shift keying demodulation circuit based on the sampling subtraction method according to claim 2, wherein: the sampling subtraction module (2) further comprises a switch controlled to be closed by the signal of ph22 being true and a switch controlled to be closed by the signal of ph12 being true; the first sampling subtraction circuit (21) is connected in series with a switch which is controlled to be closed by a signal ph22, the second sampling subtraction circuit (22) is connected in series with a switch which is controlled to be closed by a signal ph12, and then the two series circuits are connected in parallel; the first sampling subtraction circuit (21) and the second sampling subtraction circuit (22) comprise a switched capacitor (211) and a fully differential operational amplifier (212), wherein the switched capacitor (211) comprises four switches controlled to be closed by a ph11 signal, two switches controlled to be closed by a ph21 signal, two switches controlled to be closed by a ph31 signal, four switches controlled to be closed by a ph32 signal, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor, wherein the first capacitor is the third capacitor, and the second capacitor is the fourth capacitor; the second capacitor is connected with the negative input end and the positive output end of the fully differential operational amplifier (212), and the fourth capacitor is connected with the positive input end and the negative output end of the fully differential operational amplifier (212); when the first sampling subtraction circuit (21) is reset and samples for the first time, a switch controlled by a signal ph11 being true is closed, a switch controlled by a signal ph31 being true is closed, an envelope detector (1) envelope output signal Venv and half Vcom of a direct current power supply voltage are sampled to lower plates of a first capacitor and a third capacitor, the Vcom is connected to upper plates of the first capacitor and the third capacitor, and a second capacitor and a fourth capacitor are in a short circuit reset state; when the first sampling subtraction circuit (21) is used for holding for the first time, the switch controlled by the signal ph12 being true is closed, the switch controlled by the signal ph32 being true is closed, the lower plates of the first capacitor and the third capacitor are connected to Vcom, and charges in the first capacitor and the third capacitor are transferred to two ends of the second capacitor and the fourth capacitor; when the first sampling subtraction circuit (21) samples for the second time, the switch controlled by the signal ph21 being true is closed, and the switch controlled by the signal ph31 being true is closed, the envelope detector (1) envelope output signals Venv and Vcom are sampled onto the first capacitor and the third capacitor, the sampled capacitors are interchanged compared with the sampled capacitors in the previous period, and meanwhile, the second capacitor and the fourth capacitor are not reset, namely, the charges in the previous period are still stored on the second capacitor and the fourth capacitor; when the two sampling results of the first sampling subtraction circuit (21) are subtracted, a switch controlled by the signal ph22 being true and a switch controlled by the signal ph32 being true are closed, the charges collected on the first capacitor and the third capacitor are transferred to the second capacitor and the fourth capacitor during the second sampling, and the sampling subtraction result Vsub is output through the switch controlled by the signal ph22 being true; the second sampling subtraction circuit (22) and the first sampling subtraction circuit (21) are different in working phase by two working phases, and when the first sampling subtraction circuit (21) is in a first holding state, a sampling subtraction result Vsub is output through a switch which is controlled to be true through a ph12 signal.
4. The amplitude shift keying demodulation circuit based on the sampling subtraction method as claimed in claim 3, wherein: and converting the Vsub analog signal into two-bit digital signals Dflag [1] and Dflag [0] through the comparator module (3), and demodulating and outputting amplitude shift keying data Dout through the finite-state machine module (4).
5. The amplitude shift keying demodulation circuit based on the sampling subtraction method as claimed in claim 4, wherein: the comparator module (3) is formed by connecting a first dynamic comparator (31) and a second dynamic comparator (32) in parallel and outputs a two-bit digital signal; the positive inputs of the first dynamic comparator (31) and the second dynamic comparator (32) are connected with the output Vsub of the sampling subtraction circuit (2), the negative inputs are respectively connected with two reference voltages Vref + delta and Vref-delta, two working states are divided into comparison and latching, and the two working states are switched and kept synchronous with the working state of the sampling subtraction module (2).
6. The amplitude shift keying demodulation circuit based on the sampling subtraction method as claimed in claim 5, wherein: the first dynamic comparator (31) and the second dynamic comparator (32) are composed of a pre-amplification stage module (311) and a latch module (312); the pre-amplification stage module (311) comprises four switches controlled to be closed by a signal ph31, two switches controlled to be closed by a signal ph32, a seventh capacitor and an eighth capacitor, and two working phases are reset and compared in total and are kept synchronous with the switching of the working states of the sampling subtraction module (2); when the pre-amplification stage module (311) of the first dynamic comparator (31) is reset, four switches controlled by the ph31 signal as true are closed, the reference voltage Vref + Delta is sampled by the seventh capacitor, and the eighth capacitor is reset; when the pre-amplification stage module (311) of the first dynamic comparator (31) compares, two switches controlled by the ph32 signal being true are closed, the sampling subtraction result Vsub is sampled to a seventh capacitance, and the difference between the sampling subtraction result Vsub and the reference voltage Vref + Δ is amplified by a seventh capacitance/eighth capacitance; when the next ph31 signal is true, the latch module (312) of the first dynamic comparator (31) starts to operate, the result of the closing of the previous switch controlled by the ph32 signal being true is converted into a digital signal Dflag [1] through the latch module (312) of the first dynamic comparator (31), and simultaneously the pre-amplification stage module (311) of the first dynamic comparator (31) is reset; when the ph32 signal is true, the latch module (312) of the first dynamic comparator (31) is not operated, and Dflag [1] is locked; when the pre-amplification stage module (311) of the second dynamic comparator (32) is reset, four switches controlled by the ph31 signal as true are closed, the reference voltage Vref-Delta is sampled by the seventh capacitor, and the eighth capacitor is reset; when the pre-amplification stage module (311) of the second dynamic comparator (32) compares, two switches controlled by the ph32 signal being true are closed, the sampling subtraction result Vsub is sampled to a seventh capacitance, and the difference between the sampling subtraction result Vsub and the reference voltage Vref- Δ is amplified by a seventh capacitance/eighth capacitance; when the next ph31 signal is true, the latch module (312) of the second dynamic comparator (32) starts to operate, the result of the closing of the switch previously controlled by the ph32 signal being true is converted into a digital signal Dflag [0] through the latch module (312) of the second dynamic comparator (32), and simultaneously the pre-amplification stage module (311) of the second dynamic comparator (32) is reset; when the ph32 signal is true, the latch module (312) of the second dynamic comparator (32) is disabled and Dflag [0] is locked.
7. The amplitude shift keying demodulation circuit based on the sampling subtraction method as claimed in claim 6, wherein: the finite state machine module (4) consists of a three-input AND gate, a three-input OR gate, a two-input AND gate, a two-input OR gate and a D trigger; two-bit digital outputs Dflag [1] and Dflag [0] of the comparator module (3) are used as a mark for switching states, the mark and a non-previous state are connected to the inputs of a three-input AND gate and a three-input OR gate, the output of the three-input OR gate and the input of a two-input AND gate are connected, the outputs of the two-input AND gate and the three-input AND gate are connected with the inputs of the two-input OR gate, the outputs of the two-input OR gate and the D trigger are connected, and the outputs of the two-input OR gate and the D trigger are used as the output of the finite state machine module (4), namely amplitude shift keying data Dout; the positive output of the D flip-flop is the last state and the negative output is the not of the last state, the D flip-flop updates the state when the ph31 signal is true.
8. The amplitude shift keying demodulation circuit based on the sampling subtraction method as claimed in claim 1, wherein: the envelope detection circuit (1) comprises a source follower (11), a differential operational amplifier (12), a 1: X current mirror (13), a voltage stabilizing capacitor (14) and a leakage resistor (15); the voltage-stabilizing capacitor (14) is formed by connecting a fifth capacitor and a sixth capacitor in series, the leakage resistor (15) is formed by connecting a first resistor and a second resistor in series, the voltage-stabilizing capacitor (14) is connected with the leakage resistor (15) in parallel, the first ends of the first resistor and the fifth capacitor of the parallel circuit are connected with the output Venv of the envelope detection circuit (1), the first ends of the second resistor and the sixth capacitor of the parallel circuit are grounded, and the second ends of the second resistor and the sixth capacitor of the parallel circuit are connected with the positive input end of the differential operational amplifier (12); the source follower (11) is used for improving the common-mode value of an input signal and playing a role of a voltage buffer; the negative input end of the differential operational amplifier (12) is connected with the output of the source follower (11), and the output of the differential operational amplifier is connected with the input of a 1: X current mirror (13); the output of the 1: X current mirror (13) is taken as the output Venv of the envelope detection circuit (1).
9. The amplitude shift keying demodulation circuit based on the sampling subtraction method as claimed in claim 8, wherein: the source follower (11) consists of a first field effect transistor and a second field effect transistor of two P-type metal oxide semiconductor field effect transistors which are connected in series, the grid electrode of the second field effect transistor is connected with an input signal, the drain electrode of the second field effect transistor is grounded, and the source electrode of the second field effect transistor is connected with the drain electrode of the first field effect transistor and the negative input of the differential operational amplifier (12); the differential operational amplifier (12) consists of five P-type metal oxide semiconductor field effect transistors; the 1: X current mirror (13) is composed of two P-type metal oxide semiconductor field effect transistors.
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