CN113055050B - Wired communication circuit and wired communication system - Google Patents
Wired communication circuit and wired communication system Download PDFInfo
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- CN113055050B CN113055050B CN202110330555.2A CN202110330555A CN113055050B CN 113055050 B CN113055050 B CN 113055050B CN 202110330555 A CN202110330555 A CN 202110330555A CN 113055050 B CN113055050 B CN 113055050B
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Abstract
A wired communication circuit and a wired communication system convert a first differential signal into a first communication signal and convert a second communication signal into a second differential signal through a first transceiver circuit; the second transceiver circuit converts the third differential signal into a third communication signal, converts the fourth communication signal into a fourth differential signal, and forwards fault information; the control circuit converts the first communication signal into a fourth communication signal when receiving only the first communication signal; converting the third communication signal into a second communication signal when only the third communication signal is received; outputting fault information when the first communication signal and the third communication signal are received simultaneously; communication failure detection is achieved.
Description
Technical Field
The present application belongs to the field of wired communication, and in particular, relates to a wired communication circuit and a wired communication system.
Background
Wired communication, such as RS485 communication, is a communication method widely used between electronic devices, and has the advantages of economy, simplicity, strong interference rejection, and many communication nodes. However, in the wired communication, since the device and the device are directly connected by two wires, communication failure is easy to occur with the increase of the devices and the increase of the communication distance, and the conventional wired communication device has no communication failure detection function.
Disclosure of Invention
The application aims to provide a wired communication circuit and wired communication equipment, and aims to overcome the defect that the traditional wired communication equipment cannot detect communication faults.
The embodiment of the application provides a wired communication circuit, includes:
a first transceiving circuit having a first side and a second side, configured to convert a first differential signal into a first communication signal and output from the second side of the first transceiving circuit when the first side of the first transceiving circuit receives the first differential signal, and configured to convert a second communication signal received from the second side of the first transceiving circuit into a second differential signal and output from the first side of the first transceiving circuit;
a second transceiving circuit having a first side and a second side, configured to convert a third differential signal into a third communication signal and output from the second side of the second transceiving circuit when the first side of the second transceiving circuit receives the third differential signal, and configured to convert a fourth communication signal received by the second side of the second transceiving circuit into a fourth differential signal and output from the first side of the second transceiving circuit, and to forward fault information;
a control circuit connected between the first transceiver circuit and the second transceiver circuit, configured to convert the first communication signal into the fourth communication signal when receiving only the first communication signal; converting the third communication signal into the second communication signal when only the third communication signal is received; outputting the fault information when the first communication signal and the third communication signal are received simultaneously;
the second transceiver circuit is further configured to forward the fault information to a master or a slave to alarm the master or the slave.
The embodiment of the invention also provides a wired communication system which is characterized by comprising a host, a plurality of slaves and n wired communication circuits, wherein the first wired communication circuit is respectively connected with the rest n-1 wired communication circuits, and n is an integer more than or equal to 2;
the first wired communication circuit is connected with the host, and the plurality of slaves are respectively connected with the remaining n-1 wired communication circuits in a one-to-one correspondence manner.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: when the control circuit receives the first communication signal and the third communication signal simultaneously, the control circuit outputs fault information to enable the second transceiver circuit to forward the fault information, so that the communication fault detection function is realized, and the reliability of wired communication is improved.
Drawings
In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts.
Fig. 1 is a schematic structural diagram of a wired communication circuit according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a wired communication circuit according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a wired communication circuit according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a wired communication circuit according to an embodiment of the present application;
FIG. 5 is a partial schematic circuit diagram of a wired communication circuit according to an embodiment of the present application;
fig. 6 is a partially schematic circuit diagram of a wired communication circuit according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Fig. 1 shows a schematic structural diagram of a wired communication circuit provided in a preferred embodiment of the present application, and for convenience of description, only the portions related to the present embodiment are shown, which is detailed as follows:
the wired communication circuit includes a first transceiver circuit 11, a second transceiver circuit 12, and a control circuit 13.
The first transceiver circuit 11 has a first side and a second side, and is configured to convert the first differential signal into a first communication signal and output the first communication signal from the second side of the first transceiver circuit when the first side of the first transceiver circuit receives the first differential signal, and is further configured to convert a second communication signal received from the second side of the first transceiver circuit into a second differential signal and output the second differential signal from the first side of the first transceiver circuit.
And a second transceiving circuit 12 having a first side and a second side, configured to convert the third differential signal into a third communication signal and output the third communication signal from the second side of the second transceiving circuit when the first side of the second transceiving circuit receives the third differential signal, and configured to convert the fourth communication signal received from the second side of the second transceiving circuit into a fourth differential signal and output the fourth differential signal from the first side of the second transceiving circuit, and to forward the fault information.
A control circuit 13 connected between the first transceiver circuit and the second transceiver circuit, configured to convert the first communication signal into a fourth communication signal when receiving only the first communication signal; converting the third communication signal into a second communication signal when only the third communication signal is received; when the first communication signal and the third communication signal are simultaneously received, failure information is output.
The second transceiver circuit 12 is further configured to forward the fault information to the master or slave to alert the master or slave.
The first transceiver circuit is specifically configured to convert the first differential signal into a first communication signal according to a first control signal and output the first communication signal from the second side of the first transceiver circuit when the first side of the first transceiver circuit receives the first differential signal, and is further configured to convert a second communication signal received by the second side of the first transceiver circuit into a second differential signal according to a second control signal and output the second differential signal from the first side of the first transceiver circuit; the second transceiver circuit is specifically configured to, when the first side of the second transceiver circuit receives the third differential signal, convert the third differential signal into a third communication signal according to a third control signal and output the third communication signal from the second side of the second transceiver circuit, and further configured to convert a fourth communication signal received by the second side of the second transceiver circuit into a fourth differential signal according to a fourth control signal and output the fourth differential signal from the first side of the second transceiver circuit, and forward the fault information according to the fourth control signal; the control circuit is specifically configured to output a first control signal and a third control signal when powered on; when only the first communication signal is received, outputting a fourth control signal and converting the first communication signal into a fourth communication signal, and outputting a third control signal after the conversion of the first communication signal is finished; when only the third communication signal is received, outputting a second control signal, converting the third communication signal into a second communication signal, and outputting a first control signal after the conversion of the third communication signal is finished; when the first communication signal and the third communication signal are simultaneously received, a fourth control signal and fault information are output.
In a specific implementation, the second transceiver circuit 12 is specifically configured to forward the fault information to the slave or the master according to the fourth control signal so as to alarm the slave or the master. The first and second control signals may be at a high level, and the third and fourth control signals may be at a low level. The first, second, third, and fourth communication signals may be Universal Asynchronous Receiver/Transmitter (UART) signals. The first, second, third, and fourth differential signals may be RS485 signals.
If the data receiving and data sending occur on the bus at the same time, the wired communication circuit can detect the fault, so that the purpose of judging the state of the bus is achieved.
As shown in fig. 2, the wired communication circuit further includes a first isolation circuit 14 and a second isolation circuit 15.
The first isolation circuit 14 is connected to the first transceiver circuit 11 and the control circuit 13, and configured to perform isolated transmission on the first communication signal and the second communication signal.
And the second isolation circuit 15 is connected with the second transceiver circuit 12 and the control circuit 13, and is configured to perform isolated transmission on the fault information, the third communication signal and the fourth communication signal.
The first isolation circuit 14 is specifically configured to isolate transmission of the first control signal, the second control signal, the first communication signal, and the second communication signal.
The second isolation circuit 15 is specifically configured to perform isolated transmission on the fault information, the third control signal, the fourth control signal, the third communication signal, and the fourth communication signal.
The first transceiver circuit 11 is specifically configured to convert the first differential signal into a first communication signal according to the isolated first control signal and output the first communication signal from the second side of the first transceiver circuit when the first side of the first transceiver circuit receives the first differential signal, and is further configured to convert the isolated second communication signal received by the second side of the first transceiver circuit into a second differential signal according to the isolated second control signal and output the second differential signal from the first side of the first transceiver circuit.
The second transceiver circuit 12 is specifically configured to, when the first side of the second transceiver circuit receives the third differential signal, convert the third differential signal into a third communication signal according to the isolated third control signal and output the third communication signal from the second side of the second transceiver circuit, and further configured to, according to the isolated fourth control signal, convert the isolated fourth communication signal received by the second side of the second transceiver circuit into a fourth differential signal and output the fourth differential signal from the first side of the second transceiver circuit, and forward the fault information according to the isolated fourth control signal.
The control circuit 13 is specifically configured to output a first control signal and a third control signal after being powered on; when only receiving the isolated first communication signal, outputting a fourth control signal and converting the isolated first communication signal into a fourth communication signal, and when the isolated first communication signal is converted, outputting a third control signal; when only receiving the isolated third communication signal, outputting a second control signal and converting the isolated third communication signal into a second communication signal, and outputting a first control signal after the conversion of the isolated third communication signal is completed; and outputting a fourth control signal and fault information when the isolated first communication signal and the isolated third communication signal are received simultaneously.
By isolating the signals transmitted between the first transceiver circuit 11 and the control circuit 13 and the signals transmitted between the second transceiver circuit 12 and the control circuit 13, the damage of spike voltage to the control circuit 13 is prevented, the quality of wired communication is improved, and the reliability of the wired communication circuit is improved.
As shown in fig. 3, the wired communication circuit further includes a first surge protection circuit 16 and a second surge protection circuit 17.
The first surge protection circuit 16 is connected to the first transceiver circuit 11 and configured to surge-protect the first differential signal.
The second surge protection circuit 17 is connected to the second transceiver circuit 12, and configured to surge-protect the third differential signal.
The first transceiver circuit 11 is specifically configured to convert the first differential signal into a first communication signal according to a first control signal and output the first communication signal from the second side of the first transceiver circuit when the first side of the first transceiver circuit receives the surge-protected first differential signal, and is further configured to convert a second communication signal received by the second side of the first transceiver circuit into a second differential signal according to a second control signal and output the second differential signal from the first side of the first transceiver circuit.
And a second transceiver circuit 12 configured to convert the third differential signal into a third communication signal according to a third control signal and output the third communication signal from the second side of the second transceiver circuit when the first side of the second transceiver circuit receives the surge-protected third differential signal, and further configured to convert a fourth communication signal received by the second side of the second transceiver circuit into a fourth differential signal according to a fourth control signal and output the fourth differential signal from the first side of the second transceiver circuit, and forward fault information according to the fourth control signal.
In a large complex communication network, a traditional two-wire connection is used, a master computer of equipment is connected to other multiple slave computers, and due to the fact that the potentials of different equipment are unequal, other transceivers on a bus are prone to being burnt out due to overhigh common-mode voltage. Resulting in the failure of normal operation of the whole communication. By performing surge protection on the first differential signal and the third differential signal, damage of surge voltage to the control circuit 13 is prevented, the quality of wired communication is improved, and the reliability of the wired communication circuit is improved. The equipment is completely isolated from the equipment, and other parallel equipment cannot be damaged due to the fact that an overhigh surge voltage occurs to one equipment. Even if the abnormality occurs, only one device is abnormal, and the safety of other devices is guaranteed.
As shown in fig. 4, the wired communication circuit further includes a setting circuit 18.
And a setting circuit 18 connected to the control circuit 13 and configured to output a setting signal according to the sensed operation instruction.
The control circuit 13 is specifically configured to convert the first communication signal into a fourth communication signal in accordance with the setting signal when receiving only the first communication signal; converting the third communication signal into a second communication signal according to the setting signal when only the third communication signal is received; when the first communication signal and the third communication signal are simultaneously received, failure information is output.
The control circuit 13 is specifically configured to output a first control signal and a third control signal after being powered on; when only the first communication signal is received, outputting a fourth control signal, converting the first communication signal into the fourth communication signal according to the setting signal, and outputting a third control signal after the conversion of the first communication signal is finished; when only the third communication signal is received, outputting a second control signal, converting the third communication signal into a second communication signal according to the setting signal, and outputting a first control signal after the conversion of the third communication signal is finished; when the first communication signal and the third communication signal are simultaneously received, a fourth control signal and fault information are output.
As an example and not by way of limitation, the setting signal may be a baud rate setting signal, the control circuit 13 is specifically configured to obtain a baud rate parameter according to the baud rate setting signal, output a fourth control signal and convert the first communication signal into a fourth communication signal according to the baud rate parameter when only the first communication signal is received, and output a third control signal when the conversion of the first communication signal is completed; when only the third communication signal is received, outputting a second control signal, converting the third communication signal into a second communication signal according to the baud rate parameter, and outputting a first control signal after the conversion of the third communication signal is finished; when the first communication signal and the third communication signal are simultaneously received, a fourth control signal and fault information are output.
The baud rate parameter of the control circuit 13 can be configured through the setting circuit 18, so that the wired communication circuit can be applied to various transmission rates according to requirements, and the functions of products are enriched.
Fig. 5 shows a partial example circuit structure of a wired communication circuit provided by an embodiment of the present invention, fig. 6 shows a partial example circuit structure of a wired communication circuit provided by an embodiment of the present invention, and for convenience of description, only the parts related to the embodiment of the present invention are shown, and the following details are described:
the first isolation circuit 14 and the second isolation circuit 15 each include an isolation component including a digital isolator U1, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first resistor R1, a second resistor R2, and a third resistor R3.
The first input terminal INA of the digital isolator U1 and the first terminal of the first resistor R1 are commonly used as a fault information input terminal of the isolation component, a fourth communication signal input terminal of the isolation component or a second communication signal input terminal of the isolation component, the second input terminal INB of the digital isolator U1 and the first terminal of the second resistor R2 are commonly used as a first control signal input terminal of the isolation component, a second control signal input terminal of the isolation component, a third control signal input terminal of the isolation component and a fourth control signal input terminal of the isolation component, the third output terminal OUTD of the digital isolator U1 and the first terminal of the third resistor R3 are commonly used as an isolated first communication signal output terminal of the isolation component or an isolated third communication signal output terminal of the isolation component, the first output terminal OUTA of the digital isolator U1 is used as an isolated fault information output terminal of the isolation component, an isolated fourth communication signal output terminal of the isolation component or an isolated second communication signal output terminal of the isolation component An output terminal, a second output terminal OUTB of the digital isolator U1 is used as an isolated first control signal output terminal of the isolation component, an isolated second control signal output terminal of the isolation component, an isolated third control signal output terminal of the isolation component and an isolated fourth control signal output terminal of the isolation component, a third input terminal IND of the digital isolator U1 is used as a first communication signal input terminal of the isolation component or a third communication signal input terminal of the isolation component, a first power terminal VDD of the digital isolator U1, a first terminal of the second capacitor C2, a first terminal of the fourth capacitor C4, a second terminal of the first resistor R1, a second terminal of the second resistor R2 and a second terminal of the third resistor R3 are commonly connected to a first power supply VAA, a second power terminal VISO of the digital isolator U1, a first terminal of the first capacitor C1 and a first terminal of the third capacitor C3 are commonly connected to a second power supply VBB, the first ground GND1 of the digital isolator U1, the second terminal of the second capacitor C2, and the second terminal of the fourth capacitor C4 are connected to the power ground, and the second ground GND2 of the digital isolator U1, the second terminal of the first capacitor C1, and the second terminal of the third capacitor C3 are connected to the signal ground.
The isolation assembly is realized through the digital isolator, the integration level is high, and the circuit is simple and reliable.
The first transceiver circuit 11 and the second transceiver circuit 12 each include a transceiver component, and the transceiver component includes a transceiver U2, a fifth capacitor C5, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6.
A receiver output terminal RO of the transceiver U2 and a first terminal of the fourth resistor R4 are commonly used as a first communication signal output terminal of the transceiving module or a third communication signal output terminal of the transceiving module, a receiver enable terminal RE of the transceiver U2, a transmitter enable terminal DE of the transceiver U2 and a first terminal of the fifth resistor R5 are commonly used as a first control signal input terminal of the transceiving module, a second control signal input terminal of the transceiving module, a third control signal input terminal of the transceiving module and a fourth control signal input terminal of the transceiving module, a transmitter receiving terminal DI of the transceiver U2 and a first terminal of the sixth resistor R6 are commonly used as a fault information input terminal of the transceiving module, a fourth communication signal input terminal of the transceiving module or a second communication signal input terminal of the transceiving module, a positive differential signal input terminal a of the transceiver U2 and a negative differential signal input terminal B of the transceiver U2 are commonly used as a fault information output terminal of the transceiving module, A first differential signal input end of the transceiver component, a third differential signal input end of the transceiver component, a second differential signal output end of the transceiver component, and a fourth differential signal output end of the transceiver component, a power supply terminal VCC of the transceiver U2, a first end of a fifth capacitor C5, a second end of a fourth resistor R4, a second end of a fifth resistor R5, and a second end of a sixth resistor R6 are commonly connected to a third power supply VCC, and a second end of the fifth capacitor C5 and a ground end of the transceiver U2 are commonly connected to a signal ground;
the first communication signal output end of the transceiving component is connected with the first communication signal input end of the isolation component, the third communication signal output end of the transceiving component is connected with the third communication signal input end of the isolation component, the first control signal input end of the transceiving component is connected with the isolated first control signal output end of the isolation component, the second control signal input end of the transceiving component is connected with the isolated second control signal output end of the isolation component, the third control signal input end of the transceiving component is connected with the isolated third control signal output end of the isolation component, the fourth control signal input end of the transceiving component is connected with the isolated fourth control signal output end of the isolation component, the fault information input end of the transceiving component is connected with the isolated fault information output end of the isolation component, and the fourth communication signal input end of the transceiving component is connected with the isolated fourth communication signal output end of the isolation component, the second communication signal input end of the transceiving component is connected with the isolated second communication signal output end of the isolation component;
the transceiver U2 may be an RS485 transceiver, and the transceiver component circuit may implement conversion of differential signals to UART signals and conversion of UART signals to differential signals.
Each of the first surge protection circuit 16 and the second surge protection circuit 17 includes a surge protection component, and the surge protection component includes a first Transient Voltage Super (TVS) diode D1, a second TVS diode D2, a third TVS diode D3, a common mode inductor L6, a discharge tube U3, a first fuse F1, a second fuse F2, a first inductor L1, a second inductor L2, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9.
A first end of a seventh resistor R7, a first end of an eighth resistor R8, a first end of a first TVS tube D1, a first end of a second TVS tube D2, a first end of a sixth capacitor C6, a first end of a first inductor L1, a first end of a ninth resistor R9, a second end of an eighth resistor R8, a first end of a third TVS tube D3, a second end of a second TVS tube D2, a second end of a sixth capacitor C6 and a first end of a second inductor L2 are commonly used as a fault information input end of the surge protection component, a first differential signal output end after surge protection of the surge protection component, a third differential signal output end after surge protection of the surge protection component, a second differential signal input end of the surge protection component and a fourth differential signal input end of the surge protection component, a second end of the first inductor L1 is connected with a first end of a seventh capacitor C7 and a first coil input end of a common mode inductor L6, a second end of the second inductor L2 is connected to a first end of a ninth capacitor C9 and a first input/output end of a second coil of the common-mode inductor L6, a second input/output end of a first coil of the common-mode inductor L6 is connected to a first end of an eighth capacitor C8, a cathode of a discharge tube U3 and a first end of a first fuse F1, a second input/output end of a second coil of the common-mode inductor L6 is connected to a first end of a tenth capacitor C10, an anode of the discharge tube U3 and a first end of a second fuse F2, a second end of the first fuse F1 and a second end of the second fuse F2 are used together as a fault information output end of the surge protection component, a first differential signal input end of the surge protection component, a third differential signal input end of the surge protection component, a second differential signal output end of the surge protection component after protection and a fourth differential signal output end of the surge protection component after surge protection, the second end of the seventh resistor R7, the second end of the first TVS tube D1, the second end of the third TVS tube D3, the second end of the seventh capacitor C7, the second end of the eighth capacitor C8, the second end of the ninth capacitor C9, the second end of the tenth capacitor C10, and the ground terminal of the discharge tube U3 are all connected to the signal ground, and the second end of the ninth resistor R9 is connected to the fourth power supply.
The surge protection assembly achieves filtering through a resistance-capacitance network, achieves high-voltage discharge through a discharge tube, achieves current fusing through a first fuse and a second fuse, achieves a clamping function through a TVS tube, and improves reliability of surge protection.
The setting circuit 18 includes a dial switch U4, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a thirteenth resistor R13.
A first channel first end of the dial switch U4, a second channel first end of the dial switch U4, a third channel first end of the dial switch U4, a fourth channel first end of the dial switch U4, a first end of a tenth resistor R10, a first end of an eleventh resistor R11, a first end of a twelfth resistor R12, and a first end of a thirteenth resistor R13 are commonly used as a setting signal output end of the setting circuit 18, a second end of the tenth resistor R10, a second end of the eleventh resistor R11, a second end of the twelfth resistor R12, and a second end of the thirteenth resistor R13 are commonly connected to a fifth power supply VEE, and a first channel second end of the dial switch U4, a second channel second end of the dial switch U4, a third channel second end of the dial switch U4, and a fourth channel second end of the dial switch U4 are commonly connected to a power ground.
The generation of the setting signal is effected by means of the dip switch U4, and the user can configure different configuration parameters of the control circuit 13 by setting of the dip switch U4.
The control circuit 13 includes a microprocessor U5.
The first general input-output terminal PA5 of the microprocessor U5, the second general input-output terminal PA6 of the microprocessor U5, the third general input-output terminal PA7 of the microprocessor U5 and the fourth general input-output terminal PB0 of the microprocessor U5 are used together as the setting signal input terminal of the control circuit 13, the fifth general input-output terminal PA9 of the microprocessor U5 is used as the second communication signal output terminal of the control circuit 13, the sixth general input-output terminal PA10 of the microprocessor U5 is used as the first communication signal input terminal of the control circuit 13, the seventh general input-output terminal PA11 of the microprocessor U5 is used as the first control signal output terminal of the control circuit 13 and the second control signal output terminal of the control circuit 13, the eighth general input-output terminal PA3 of the microprocessor U5 is used as the third communication signal input terminal of the control circuit 13, the ninth general input-output terminal PA2 of the microprocessor U5 is used as the fourth communication signal output terminal of the control circuit 13 and the fault information output terminal of the control circuit 13, the tenth general input/output terminal PA0 of the microprocessor U5 serves as a third control signal output terminal of the control circuit 13 and a fourth control signal output terminal of the control circuit 13.
The following further description of fig. 5 and 6 is made in conjunction with the working principle:
after the microprocessor U5 is powered on, the first control signal is output from the seventh gpio pin PA11 of the microprocessor U5, and the third control signal is output from the tenth gpio pin PA0 of the microprocessor U5. The first control signal is isolated by the digital isolator U1 in the first isolation circuit 14 and then sent to the receiver enable terminal RE of the transceiver U2 and the transmitter enable terminal DE of the transceiver U2 in the first transceiving circuit 11; the third control signal is isolated by the digital isolator U1 in the second isolation circuit 15 and then transmitted to the receiver enable RE of the transceiver U2 and the transmitter enable DE of the transceiver U2 in the second transceiver circuit 12.
When the positive differential signal input-output terminal a of the transceiver U2 and the negative differential signal input-output terminal B of the transceiver U2 in the first transceiver circuit 11 receive the first differential signal, the transceiver U2 in the first transceiver circuit 11 converts the first differential signal into a first communication signal according to the first control signal and outputs the first communication signal from the receiver output terminal RO of the transceiver U2, the first communication signal is isolated by the digital isolator U1 in the first isolation circuit 14 and then sent to the sixth general-purpose input-output terminal PA10 of the microprocessor U5,
when the microprocessor U5 receives only the first communication signal, it outputs a fourth control signal and converts the first communication signal into a fourth communication signal, the fourth control signal is output from the tenth general input/output terminal PA0 of the microprocessor U5, the fourth communication signal is output from the ninth general input/output terminal PA2 of the microprocessor U5, and the fourth control signal is isolated by the digital isolator U1 in the second isolating circuit 15 and then sent to the receiver enable terminal RE of the transceiver U2 and the transmitter enable terminal DE of the transceiver U2 in the second transceiver circuit 12; the fourth communication signal is isolated by the digital isolator U1 in the second isolation circuit 15 and then transmitted to the transmitter receiving end DI of the transceiver U2 in the second transceiver circuit 12, and the transceiver U2 in the second transceiver circuit 12 converts the fourth communication signal into a fourth differential signal according to the fourth control signal and outputs the fourth differential signal from the positive differential signal input/output end a of the transceiver U2 in the second transceiver circuit 12 and the negative differential signal input/output end B of the transceiver U2. When the microprocessor U5 completes the conversion of the first communication signal, it outputs a third control signal; the third control signal is isolated by the digital isolator U1 in the second isolation circuit 15 and then transmitted to the receiver enable RE of the transceiver U2 and the transmitter enable DE of the transceiver U2 in the second transceiver circuit 12.
When the positive differential signal input/output terminal a of the transceiver U2 in the second transceiver circuit 12 and the negative differential signal input/output terminal B of the transceiver U2 receive the third differential signal, the third differential signal is converted into a third differential signal according to the third control signal and output from the receiver output terminal RO of the transceiver U2 in the second transceiver circuit 12, the third differential signal is isolated by the digital isolator U1 in the second isolation circuit 15 and then transmitted to the eighth general input/output terminal PA3 of the microprocessor U5 for output, when the microprocessor U5 receives only the third differential signal, the second control signal is output and converted into the second communication signal, the second control signal is output from the seventh general input/output terminal PA11 of the microprocessor U5, the second communication signal is output from the fifth general input/output terminal PA9 of the microprocessor U5, and the second control signal is isolated by the digital isolator U1 in the first isolation circuit 14 and then transmitted to the receiver of the transceiver U2 in the first transceiver circuit 11 for enabling the second control signal to be isolated by the digital isolator U1 in the first isolation circuit 14 An enable RE and a transmitter enable DE of the transceiver U2; the second communication signal is isolated by the digital isolator U1 in the first isolation circuit 14 and then sent to the transmitter receiving terminal DI of the transceiver U2 in the first transceiver circuit 11, and the transceiver U2 in the first transceiver circuit 11 converts the second communication signal into a second differential signal according to the second control signal.
When the microprocessor U5 receives the first communication signal and the third communication signal simultaneously, the microprocessor U5 outputs a fourth control signal from the tenth gpio port PA0 and outputs fault information from the ninth gpio port PA2 of the microprocessor U5, and the fourth control signal is isolated by the digital isolator U1 in the second isolation circuit 15 and then transmitted to the receiver enable RE of the transceiver U2 and the transmitter enable DE of the transceiver U2 in the second transceiver circuit 12; the fault information is isolated by the digital isolator U1 in the second isolation circuit 15 and then transmitted to the transmitter receiving terminal DI of the transceiver U2, and the positive differential signal input/output terminal a of the transceiver U2 and the negative differential signal input/output terminal B of the transceiver U2 in the second transceiver circuit 12 output the fault information to the master or the slave.
The embodiment of the invention also provides a wired communication system which comprises a host, a plurality of slaves and n wired communication circuits, wherein the first wired communication circuit is respectively connected with the rest n-1 wired communication circuits, and n is an integer more than or equal to 2;
the first wired communication circuit is connected with the host, and the plurality of slaves are respectively connected with the rest n-1 wired communication circuits in a one-to-one correspondence manner.
The host is configured to output a first main differential signal and receive a second main differential signal and first fault information;
a first wired communication circuit connected to the host and configured to convert the first main differential signal into a first bus differential signal when receiving only the first main differential signal; when only the second bus differential signal is received, converting the second bus differential signal into a second main differential signal; when the first main differential signal and the second bus differential signal are received simultaneously, first fault information is output to the host.
The remaining n-1 wired communication circuits are respectively connected with the first wired communication circuit and are configured to convert the first slave differential signal into a first branch differential signal when only the first slave differential signal is received; when only the second branch line differential signal is received, converting the second branch line differential signal into a second slave differential signal; when the first slave differential signal and the second branch differential signal are simultaneously received, outputting second fault information;
and the slave machines are respectively connected with the remaining n-1 wired communication circuits in a one-to-one correspondence mode and are configured to output first slave differential signals and receive second slave differential signals and second fault information.
In the first wired communication circuit, the first main differential signal is a third differential signal, the second main differential signal is a fourth differential signal, the first bus differential signal is a second differential signal, and the second bus differential signal is a first differential signal.
In the remaining n-1 wired communication circuits, the first slave differential signal is a third differential signal, the second slave differential signal is a fourth differential signal, the first branch differential signal is a second differential signal, and the second branch differential signal is a first differential signal.
The first bus differential signal is divided into a plurality of first branch differential signals; the plurality of first branch line differential signals together constitute a second bus line differential signal.
In the embodiment of the present invention, when the first side of the first transceiver circuit receives the first differential signal, the first transceiver circuit converts the first differential signal into the first communication signal and outputs the first communication signal from the second side of the first transceiver circuit, and is further configured to convert the second communication signal received by the second side of the first transceiver circuit into the second differential signal and output the second differential signal from the first side of the first transceiver circuit; the second transceiver circuit converts the third differential signal into a third communication signal and outputs the third communication signal from the second side of the second transceiver circuit when the first side of the second transceiver circuit receives the third differential signal, and is further configured to convert the fourth communication signal received by the second side of the second transceiver circuit into a fourth differential signal and output the fourth differential signal from the first side of the second transceiver circuit, and forward the fault information; when only receiving the first communication signal, the control circuit converts the first communication signal into a fourth communication signal; converting the third communication signal into a second communication signal when only the third communication signal is received; outputting fault information when the first communication signal and the third communication signal are received simultaneously; when the control circuit receives the first communication signal and the third communication signal simultaneously, the control circuit outputs the fault information to enable the second transceiver circuit to forward the fault information, so that the communication fault detection function is realized, and the reliability of wired communication is improved.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (9)
1. A wired communication circuit, comprising:
a first transceiving circuit having a first side and a second side, configured to convert a first differential signal into a first communication signal and output from the second side of the first transceiving circuit when the first side of the first transceiving circuit receives the first differential signal, and configured to convert a second communication signal received from the second side of the first transceiving circuit into a second differential signal and output from the first side of the first transceiving circuit;
a second transceiving circuit having a first side and a second side, configured to convert a third differential signal into a third communication signal and output from the second side of the second transceiving circuit when the first side of the second transceiving circuit receives the third differential signal, and configured to convert a fourth communication signal received by the second side of the second transceiving circuit into a fourth differential signal and output from the first side of the second transceiving circuit, and to forward fault information;
a control circuit connected between the first transceiver circuit and the second transceiver circuit, configured to convert the first communication signal into the fourth communication signal when receiving only the first communication signal; converting the third communication signal into the second communication signal when only the third communication signal is received; outputting the fault information when the first communication signal and the third communication signal are received simultaneously;
the second transceiver circuit is further configured to forward the fault information to a master or a slave to alarm the master or the slave.
2. The wired communication circuit of claim 1, wherein the first transceiver circuit is specifically configured to convert a first differential signal into a first communication signal according to a first control signal and output the first communication signal from the second side of the first transceiver circuit when the first side of the first transceiver circuit receives the first differential signal, and further configured to convert a second communication signal received from the second side of the first transceiver circuit into a second differential signal and output the second differential signal from the first side of the first transceiver circuit according to a second control signal;
the second transceiver circuit is specifically configured to, when the first side of the second transceiver circuit receives a third differential signal, convert the third differential signal into a third communication signal according to a third control signal and output the third communication signal from the second side of the second transceiver circuit, and further configured to convert a fourth communication signal received by the second side of the second transceiver circuit into a fourth differential signal according to a fourth control signal and output the fourth differential signal from the first side of the second transceiver circuit, and forward the fault information according to the fourth control signal;
the control circuit is specifically configured to output the first control signal and the third control signal after being powered on; when only the first communication signal is received, outputting the fourth control signal and converting the first communication signal into the fourth communication signal, and when the conversion of the first communication signal is completed, outputting the third control signal; when only the third communication signal is received, outputting the second control signal and converting the third communication signal into the second communication signal, and outputting the first control signal after the conversion of the third communication signal is completed; outputting the fourth control signal and the fault information when the first communication signal and the third communication signal are received simultaneously.
3. The wired communication circuit of claim 1, further comprising:
the first isolation circuit is connected between the first transceiving circuit and the control circuit and is configured to carry out isolated transmission on a first communication signal and a second communication signal;
and the second isolation circuit is connected between the second transceiver circuit and the control circuit and is configured to perform isolated transmission on the fault information, the third communication signal and the fourth communication signal.
4. The wired communication circuit of claim 3, wherein the first isolation circuit and the second isolation circuit each comprise an isolation component comprising a digital isolator, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first resistor, a second resistor, and a third resistor;
the first input end of the digital isolator and the first end of the first resistor are commonly used as the fault information input end of the isolation component, the fourth communication signal input end of the isolation component or the second communication signal input end of the isolation component, the second input end of the digital isolator and the first end of the second resistor are commonly used as the first control signal input end of the isolation component, the second control signal input end of the isolation component, the third control signal input end of the isolation component and the fourth control signal input end of the isolation component, the third output end of the digital isolator and the first end of the third resistor are commonly used as the isolated first communication signal output end of the isolation component or the isolated third communication signal output end of the isolation component, and the first output end of the digital isolator is used as the isolated fault information output end of the isolation component, The isolated fourth communication signal output end of the isolation component or the isolated second communication signal output end of the isolation component, the second output end of the digital isolator serves as the isolated first control signal output end of the isolation component, the isolated second control signal output end of the isolation component, the isolated third control signal output end of the isolation component and the isolated fourth control signal output end of the isolation component, the third input end of the digital isolator serves as the first communication signal input end of the isolation component or the third communication signal input end of the isolation component, the first power end of the digital isolator, the first end of the second capacitor, the first end of the fourth capacitor, the second end of the first resistor, the second end of the second resistor and the second end of the third resistor are commonly connected to a first power supply, the second power end of the digital isolator, the first end of the first capacitor and the first end of the third capacitor are connected to a second power supply in common, the first ground end of the digital isolator, the second end of the second capacitor and the second end of the fourth capacitor are connected to a power ground, and the second ground end of the digital isolator, the second end of the first capacitor and the second end of the third capacitor are connected to a signal ground.
5. The wired communication circuit of claim 4, wherein the first transceiver circuit and the second transceiver circuit each comprise a transceiver component comprising a transceiver, a fifth capacitor, a fourth resistor, a fifth resistor, and a sixth resistor;
the receiver output end of the transceiver and the first end of the fourth resistor are commonly used as the first communication signal output end of the transceiving component or the third communication signal output end of the transceiving component, the receiver enable end of the transceiver, the transmitter enable end of the transceiver and the first end of the fifth resistor are commonly used as the first control signal input end of the transceiving component, the second control signal input end of the transceiving component, the third control signal input end of the transceiving component and the fourth control signal input end of the transceiving component, the transmitter receiving end of the transceiver and the first end of the sixth resistor are commonly used as the fault information input end of the transceiving component, the fourth communication signal input end of the transceiving component or the second communication signal input end of the transceiving component, the positive differential signal input end of the transceiver and the negative differential signal input end of the transceiver are commonly used as the transceiving component A fault information output end of a transceiver component, a first differential signal input end of the transceiver component, a third differential signal input end of the transceiver component, a second differential signal output end of the transceiver component, and a fourth differential signal output end of the transceiver component, wherein a power supply end of the transceiver, a first end of the fifth capacitor, a second end of the fourth resistor, a second end of the fifth resistor, and a second end of the sixth resistor are commonly connected to a third power supply, and a second end of the fifth capacitor and a ground end of the transceiver are commonly connected to a signal ground;
the first communication signal output end of the transceiving component is connected with the first communication signal input end of the isolation component, the third communication signal output end of the transceiving component is connected with the third communication signal input end of the isolation component, the first control signal input end of the transceiving component is connected with the isolated first control signal output end of the isolation component, the second control signal input end of the transceiving component is connected with the isolated second control signal output end of the isolation component, the third control signal input end of the transceiving component is connected with the isolated third control signal output end of the isolation component, the fourth control signal input end of the transceiving component is connected with the isolated fourth control signal output end of the isolation component, and the fault information input end of the transceiving component is connected with the isolated fault information output end of the isolation component, and the fourth communication signal input end of the transceiving component is connected with the isolated fourth communication signal output end of the isolation component, and the second communication signal input end of the transceiving component is connected with the isolated second communication signal output end of the isolation component.
6. The wired communication circuit of claim 1, further comprising:
the first surge protection circuit is connected with the first transceiving circuit and is configured to perform surge protection on the first differential signal;
and the second surge protection circuit is connected with the second transceiving circuit and is configured to perform surge protection on the third differential signal.
7. The wired communication circuit of claim 2, further comprising:
the setting circuit is connected with the control circuit and is configured to output a setting signal according to the sensed operation instruction;
the control circuit is specifically configured to convert the first communication signal into the fourth communication signal according to the setting signal when only the first communication signal is received; converting the third communication signal into the second communication signal according to the setting signal when only the third communication signal is received; outputting the fourth control signal and the fault information when the first communication signal and the third communication signal are received simultaneously.
8. The wired communication circuit of claim 7, wherein the setting circuit includes a dial switch, a tenth resistor, an eleventh resistor, a twelfth resistor, and a thirteenth resistor;
the first end of the first channel of the dial switch, the first end of the second channel of the dial switch, the first end of the third channel of the dial switch, the first end of the fourth channel of the dial switch, the first end of the tenth resistor, the first end of the eleventh resistor, the first end of the twelfth resistor and the first end of the thirteenth resistor are jointly used as the setting signal output end of the setting circuit, the second end of the tenth resistor, the second end of the eleventh resistor, the second end of the twelfth resistor and the second end of the thirteenth resistor are jointly connected to a fifth power supply, and the second end of the first channel of the dial switch, the second end of the second channel of the dial switch, the second end of the third channel of the dial switch and the second end of the fourth channel of the dial switch are jointly connected to a power ground.
9. A wired communication system comprising a master, a plurality of slaves, and n wired communication circuits according to any one of claims 1 to 8, wherein a first one of the wired communication circuits is connected to the remaining n-1 wired communication circuits, respectively, and n is an integer of 2 or more;
the first wired communication circuit is connected with the host, and the plurality of slaves are respectively connected with the remaining n-1 wired communication circuits in a one-to-one correspondence manner.
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