CN113053853A - 半导体器件和制造半导体器件的方法 - Google Patents
半导体器件和制造半导体器件的方法 Download PDFInfo
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- CN113053853A CN113053853A CN202110185533.1A CN202110185533A CN113053853A CN 113053853 A CN113053853 A CN 113053853A CN 202110185533 A CN202110185533 A CN 202110185533A CN 113053853 A CN113053853 A CN 113053853A
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Abstract
半导体器件,包括金属栅极结构,金属栅极结构具有设置在金属栅极结构的侧壁上的侧壁间隔件。在一些实施例中,金属栅极结构的顶面相对于侧壁间隔件的顶面凹进。半导体器件可进一步包括设置在金属栅极结构的上方并且与金属栅极结构接触的金属覆盖层,其中金属覆盖层的底部的第一宽度大于金属覆盖层的顶部的第二宽度。在一些实施例中,半导体器件可进一步包括设置在金属覆盖层的任一侧上的介电材料,其中侧壁间隔件和金属栅极结构的部分设置在介电材料的下方。本申请的实施例还涉及制造半导体器件的方法。
Description
技术领域
本申请的实施例涉及半导体器件和制造半导体器件的方法。
背景技术
电子行业对更小、更快的电子器件的需求不断增长,这些电子器件同时能支持越来越多、越来越复杂的功能。因此,在半导体行业中存在着制造低成本、高性能和低功率的集成电路(IC)的持续趋势。迄今为止,通过缩小半导体IC的尺寸(例如,最小部件尺寸)并且由此提高生产效率并降低相关成本,在很大程度上已经实现了这些目标。但是,这样的缩小也增加了半导体制造工艺的复杂性。因此,实现半导体IC和器件的持续发展要求在半导体制造工艺和技术上有类似的发展。
仅作为一个例子,形成可靠的到金属栅电极的接触件,需要可靠的、低电阻的金属栅极通孔。但是,随着IC器件继续缩小,金属栅极通孔的底部尺寸(例如,金属栅极通孔的位于金属栅极通孔的底部的宽度)变得更小,金属栅极通孔和下面的金属栅电极之间的界面处的电阻变得更加重要。结果,器件性能(例如,器件速度)降低。此外,由于高度缩小的金属栅极通孔,金属栅极通孔蚀刻和金属间隙填充能力变得更加困难。在至少一些情况下,这可能导致金属栅极通孔蚀刻工艺的过早停止(例如,导致不完全形成金属栅极通孔)或在金属栅极通孔中形成严重的空隙,从而降低器件性能。在一些情况下,由于粘合层的高电阻,沿着金属栅极通孔的侧壁设置的粘合层也可能严重降低器件性能。随着器件尺寸不断缩小,这个问题变得更加明显。
因此,现有技术未被证明在所有方面都完全令人满意。
发明内容
本申请的一些实施例提供了一种半导体器件,包括:金属栅极结构,具有设置在所述金属栅极结构的侧壁上的侧壁间隔件,其中,所述金属栅极结构的顶面相对于所述侧壁间隔件的顶面凹进;金属覆盖层,设置在所述金属栅极结构的上方并与金属栅极结构接触,其中,所述金属覆盖层的底部的第一宽度大于金属覆盖层的顶部的第二宽度;以及介电材料,设置在所述金属覆盖层的任一侧上,其中,所述侧壁间隔件和所述金属栅极结构的部分设置在所述介电材料的下方。
本申请的另一些实施例提供了一种半导体器件,包括:金属栅极结构,具有顶部和底部,其中,所述金属栅极结构的顶部具有锥形轮廓,其中,所述锥形轮廓的底面的宽度大于所述锥形轮廓的顶面的宽度,并且其中所述锥形轮廓的底面的宽度小于所述金属栅极结构的底部的顶面的宽度;以及侧壁间隔件,设置在所述金属栅极结构的侧壁上,其中,所述侧壁间隔件与所述金属栅极结构的底部接触,其中,所述侧壁间隔件通过介电材料与所述金属栅极结构的顶部分离,并且其中,所述金属栅极结构的底部的部分设置在所述介电材料的下方。
本申请的又一些实施例提供了一种制造半导体器件的方法,包括:提供包括金属栅极结构的衬底,所述金属栅极结构具有设置在所述金属栅极结构的侧壁上的侧壁间隔件;对所述金属栅极结构和所述侧壁间隔件进行回蚀刻,其中,在所述回蚀刻后,所述金属栅极结构的顶面相对于所述侧壁间隔件的顶面凹进;在被回蚀刻的金属栅极结构和被回蚀刻的侧壁间隔件的上方沉积金属覆盖层;以及通过去除所述金属覆盖层的部分来使所述金属覆盖层图案化,以暴露所述被回蚀刻的侧壁间隔件和至少所述被回蚀刻的金属栅极结构的部分;其中,所述图案化的金属覆盖层提供金属栅极通孔,并且其中,所述图案化的金属覆盖层的底部的第一宽度大于所述图案化的金属覆盖层的顶部的第二宽度。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1A是根据一些实施例的MOS晶体管的截面图;
图1B是根据本发明的一个或多个方面的FinFET器件的实施例的立体图;
图2是根据一些实施例的形成包括金属栅极通孔的接触件结构的方法的流程图;
图3A、图4A、图5A、图6A、图7A、图8A以及图9A提供了根据一些实施例的处于制造的中间阶段并且根据图2的方法进行处理的器件的截面图,所沿着的平面基本上平行于图1B的BB'截面所限定的平面;
图3B、图4B、图5B、图6B、图7B、图8B以及图9B提供了根据一些实施例的处于制造的中间阶段并且根据图2的方法进行处理的器件的截面图,所沿着的平面基本上平行于图1B的AA'截面所限定的平面;
图10A提供了如图9A所示的器件的放大图,图10B提供了根据一些实施例的如图9B所示的器件的放大图;
图11是根据一些实施例的形成包括金属栅极通孔的接触件结构的另一方法的流程图;
图12A、图13A、图14A、图15A以及图16A提供了根据一些实施例的处于制造的中间阶段并且根据图11的方法进行处理的器件的截面图,所沿着的平面基本上平行于图1B的BB'截面所限定的平面;
图12B、图13B、图14B、图15B以及图16B提供了根据一些实施例的处于制造的中间阶段并且根据图11的方法进行处理的器件的截面图,所沿着的平面基本上平行于图1B的AA'截面所限定的平面;
图17A提供了如图16A所示的器件的放大图,图17B提供了根据一些实施例的如图16B所示的器件的放大图;
图18是根据一些实施例的形成包括金属栅极通孔的接触件结构的又一方法的流程图;
图19A、图20A以及图21A提供了根据一些实施例的处于制造的中间阶段并且根据图18的方法进行处理的器件的截面图,所沿着的平面基本上平行于图1B的BB'截面所限定的平面;
图19B、图20B以及图21B提供了根据一些实施例的处于制造的中间阶段并且根据图18的方法进行处理的器件的截面图,所沿着的平面基本上平行于图1B的截面AA'所限定的平面;
图22A提供了如图21A所示的器件的放大图,图22B提供了根据一些实施例的如图16B所示的器件的放大图;
图23、图24以及图25提供了根据图2的方法进行处理的器件的其他实施例。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为了便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。在各个实例中,被描述为彼此相同、基本相同或相等的厚度、宽度、高度或其他尺寸可以彼此至少在10%以内。
还应当注意,本发明以金属栅极通孔的形式呈现了可以在多种器件类型中的任何一种中采用的实施例。例如,本发明的实施例可用来在如下的器件中形成金属栅极通孔:平面体金属氧化物半导体场效应晶体管(MOSFET)、多栅极晶体管(平面或垂直)例如FinFET器件、全环栅(GAA)器件、欧米茄栅极(Ω栅极)器件、或Pi栅极(Π栅极)器件、以及应变半导体器件、绝缘体上硅(SOI)器件、部分耗尽SOI(PD-SOI)器件、完全耗尽SOI(FD-SOI)器件、或本领域已知的其他器件。另外,在P型和/或型器件的形成中可采用本文所公开的实施例。本领域的普通技术人员可以认识到可通过本发明的各方面获得的半导体器件的其他实施例。
参考图1A的实例,其中所示为MOS晶体管100,提供了仅一个器件类型的例子,其可包括本发明的实施例。应当理解,示例性晶体管100并不意味着以任何方式进行限制,并且本领域技术人员将认识到,本发明的实施例可以同等地适用于多种其他器件类型中的任何一种,例如上文所述的类型。晶体管100在衬底102上制造,并且包括栅极堆叠件104。衬底102可以是诸如硅衬底的半导体衬底。衬底102可包括各种层,包括形成在衬底102上的导电或绝缘层。如本领域所知,衬底102根据设计要求可以包括各种掺杂结构。衬底102也可以包括其他半导体,诸如锗、碳化硅(SiC)、硅锗(SiGe)或金刚石。可选地,衬底102可以包括复合半导体和/或合金半导体。此外,在一些实施例中,衬底102可以包括外延层(epi-layer),可以对衬底102进行应变以增强性能,衬底102可以包括绝缘体上硅(SOI)结构,且/或衬底102可以具有其他合适的增强部件。
栅极堆叠件104包括栅极电介质106和设置在栅极电介质106上的栅电极108。在一些实施例中,栅极电介质106可以包括诸如氧化硅层(SiO2)或氮氧化硅(SiON)的界面层,其中这种界面层可以通过化学氧化、热氧化、原子层沉积(ALD)、化学气相沉积(CVD)和/或其他合适的方法。在一些实例中,栅极电介质106包括高K介电层,例如氧化铪(HfO2)。可选地,高K介电层可以包括其他高K电介质,例如TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2、LaO、AlO、ZrO、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO3(BST)、Al2O3、Si3N4、氧氮化物(SiON)、其组合,或其他合适的材料。本发明使用和描述的高K栅极电介质包括具有高介电常数(例如大于热氧化硅的介电常数(~3.9))的介电材料。在其他实施例中,栅极电介质106可以包括二氧化硅或其他合适的电介质。栅极电介质106可以通过ALD、物理气相沉积(PVD)、CVD、氧化和/或其他合适的方法来形成。在一些实施例中,栅电极108可以作为先栅极或后栅极(例如,替换栅极)工艺的一部分沉积。在各个实施例中,栅电极108包括导电层,例如W、Ti、TiN、TiAl、TiAlN、Ta、TaN、WN、Re、Ir、Ru、Mo、Al、Cu、Co、TiSi、CoSi、Ni、NiSi、其组合、和/或其他合适的成分。在一些实施例中,栅电极108可以包括用于N型晶体管的第一金属材料和用于P型晶体管的第二金属材料。因此,晶体管100可包括双功函数金属栅极结构。例如,第一金属材料(例如,用于N型器件)可包括具有功函数的金属,该功函数基本上与衬底导带的功函数一致,或至少基本上与晶体管100的沟道区114的导带的功函数一致。类似地,第二金属材料(例如,用于P型器件)可以包括具有功函数的金属,该功函数基本上与衬底价带的功函数一致,或者至少基本上与晶体管100的沟道区114的价带的功函数一致。因此,栅电极108可以为晶体管100提供栅电极,包括N型和P型器件。在一些实施例中,栅电极108可以交替地或另外地包括多晶硅层。在各个实例中,栅电极108可以利用PVD、CVD、电子束(e-beam)蒸发、和/或其他合适的工艺来形成。在一些情况下,栅极堆叠件104可以还包括一个或多个阻挡层、填料层和/或其他合适的层。在一些实施例中,侧壁间隔件形成在栅极堆叠件104的侧壁上。这样的侧壁间隔件可以包括介电材料,例如氧化硅、氮化硅、碳化硅、氮氧化硅或其组合。
晶体管100还包括源极区110和漏极区112,它们各自形成在半导体衬底102内,邻近栅极堆叠件104且在栅极堆叠件的任一侧上。在一些实施例中,源极区110和漏极区112包括扩散的源极/漏极区、离子注入的源极/漏极区、外延生长的源极/漏极区,或其组合。晶体管100的沟道区114被限定为在栅极电介质106之下并且在半导体衬底102内的源极区110和漏极区112之间的区域。沟道区114具有相关的沟道长度“L”和相关的沟道宽度“W”。当大于晶体管100的阈值电压(Vt)的偏置电压(即,导通电压)连同在源极区110和漏极区112之间同时施加的偏置电压一起被施加到栅电极108时,电流(例如,晶体管驱动电流)通过沟道区114在源极区110和漏极区112之间流动。针对给定的偏置电压(例如,施加到栅电极108或在源极区110和漏极区112之间)而产生的驱动电流的量是用于形成沟道区114的材料的迁移率的函数。在一些实例中,沟道区114包括硅(Si)和/或高迁移率材料,例如锗,其可以外延生长,以及本领域已知的多个化合物半导体或合金半导体中的任一个。高迁移率材料包括电子和/或空穴迁移率大于硅(Si)的那些材料,其在室温(300K)下的固有电子迁移率约为1350cm2/V-s,并且在室温下的固有空穴迁移率(300K)约480cm2/V-s。
参考图1B,其中示出了FinFET器件150,提供了可以包括本发明的实施例的其他器件类型的实例。举例来说,FinFET器件150包括一个或多个基于鳍的多栅极场效应晶体管(FET)。FinFET器件150包括衬底152、从衬底152延伸的至少一个鳍元件154、隔离区156、以及布置在鳍元件154上和周围的栅极结构158。衬底152可以是诸如硅衬底的半导体衬底。在各个实施例中,如上所述,衬底152可以基本上与衬底102相同,并且可以包括一种或多种用于衬底102的材料。
鳍元件154像衬底152一样,可以包括一个或多个外延生长的层,并且可以包括硅或另一种元素半导体,例如锗;化合物半导体包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体包括SiGe、GaAsP、AlInAs、AlGaAs、InGaAs、GaInP和/或GaInAsP,或其组合。鳍元件154可使用合适的工艺包括光刻和蚀刻工艺来制造。光刻工艺可以包括:在衬底上(例如,在硅层上)形成光刻粘合层(抗蚀剂);将抗蚀剂暴露于图案;进行曝光后烘烤工艺;以及显影抗蚀剂以形成包括抗蚀剂的掩模元件。在一些实施例中,使抗蚀剂图案化以形成掩模元件可以使用电子束(e-beam)光刻工艺来进行。然后,当蚀刻工艺在硅层中形成凹进的同时,可以使用掩模元件来保护衬底的区域,从而留下延伸的鳍元件154。可以使用干蚀刻(例如,化学氧化物去除)、湿蚀刻和/或其他合适的工艺来对凹槽进行蚀刻。也可以使用许多其他实施例的方法在衬底152上形成鳍元件154。
多个鳍元件154中的每一个还包括源极区155和漏极区157,其中源极/漏极区155、157形成在鳍元件154中、上和/或周围。源极/漏极区155、157可以外延生长于鳍元件154。此外,晶体管的沟道区布置在鳍元件154内,位于栅极结构158的下面,所沿着的平面基本上平行于图1B的AA'截面所限定的平面。在一些实例中,如上所述,鳍元件154的沟道区包括高迁移率材料。
隔离区156可以是浅槽隔离(STI)部件。或者,可以在衬底152上和/或内实施场氧化物、LOCOS部件和/或其他合适的隔离部件。隔离区156可以由氧化硅、氮化硅、氮氧化硅、掺杂氟的硅酸盐玻璃(FSG)、低K电介质、其组合、和/或本领域已知的其他合适的材料组成。在一实施例中,隔离区156是STI部件,并且通过在衬底152中蚀刻沟槽来形成。然后,沟槽可以用隔离材料来填充,然后进行化学机械抛光(CMP)工艺。但是,其他实施例也可以。在一些实施例中,隔离区156可以包括多层结构,例如,具有一个或多个衬层。
栅极结构158包括具有界面层160的栅极堆叠件,界面层形成在鳍154的沟道区的上方,栅极介电层162形成在界面层160的上方,金属层164形成在栅极介电层162的上方。在各个实施例中,界面层160基本上与被描述为栅极电介质106的部分的界面层相同。在一些实施例中,栅极介电层162基本上与栅极电介质106相同,并且可以包括与栅极电介质106所用材料相似的高K电介质。类似地,在各个实施例中,金属层164基本上与上述的栅电极108相同。在一些情况下,栅极结构158还可以包括一个或多个阻挡层、填料层和/或其他合适的层。在一些实施例中,侧壁间隔件形成在栅极结构158的侧壁上。侧壁间隔件可以包括介电材料,例如氧化硅、氮化硅、碳化硅、氮氧化硅或其组合。
如上所述,晶体管100和FinFET器件150中的每一个可以包括一个或多个金属栅极通孔,其实施例将在下文更详细地描述。在一些实例中,本文描述的金属栅极通孔可以是局部互连结构的部分。如本文所使用的,术语“局部互连”用于描述最低水平的金属互连,并且与中间和/或全局互连有所区别。局部互连跨越相对短的距离,并且有时用于例如电连接给定器件或附近器件的源极、漏极、主体和/或栅极。另外,例如,局部互连可用于通过一个或多个通孔来促进一个或多个器件垂直连接到上面的金属化层(例如,到中间互连层)。互连(例如,包括局部、中间、或全局互连)一般可以形成为部分的后道工序(BEOL)的制造工艺并且包括多级网络的金属布线。此外,多个IC电路和/或装置(例如,晶体管100或FinFET150)中的任何一个可以通过这样的互连来连接。
随着高级IC器件和电路的不断缩小和复杂性的不断提高,接触件和局部互连设计已证明是一项艰巨的挑战。举例来说,形成到金属栅电极(例如,上述的栅电极108或金属层164)的可靠接触需要可靠且低电阻的金属栅极通孔。但是,随着IC器件继续缩小,金属栅极通孔的底部尺寸(例如,金属栅极通孔的位于金属栅极通孔的底部的宽度)变得更小,金属栅极通孔和下面的金属栅电极之间的界面处的电阻变得更加重要。结果,器件性能(例如,器件速度)降低。此外,由于高度缩小的金属栅极通孔,金属栅极通孔蚀刻和金属间隙填充能力变得更加困难。在至少一些情况下,这可能导致金属栅极通孔蚀刻工艺的过早停止(例如,导致不完全形成金属栅极通孔)或在金属栅极通孔中形成严重的空隙,从而降低器件性能。在一些情况下,由于粘合层的高电阻,沿着金属栅极通孔的侧壁设置的粘合层也可能严重降低器件性能。随着器件尺寸不断缩小,这个问题变得更加明显。因此,现有方法并不是在所有方面都完全令人满意。
本发明的实施例提供了优于现有技术的优点,尽管应当理解,其他实施例可以提供不同的优点,在本文中不必讨论所有优点,并且所有实施例都不需要特定的优点。例如,本文讨论的实施例包括针对用于接触件结构(包括金属栅极通孔)的制造工艺的方法和结构。在一些实施例中公开了用于形成金属栅极通孔的切割金属法,用来提供到下面的金属栅电极的连接。所公开的金属栅极通孔有时可以用术语“VG”(通孔栅极)来指代。因此,在一些情况下,本文公开的切割金属方法也可以称为VG切割金属方法。一般地,并且在各个实施例中,本文公开的切割金属方法通过如下的步骤来提供金属栅极通孔:在栅极堆叠件的上方形成金属层;进行切割金属光刻工艺;以及进行切割金属蚀刻工艺,由此形成金属栅极通孔。这样的工艺与至少一些形成金属栅极通孔的传统方法形成对比,传统方法包括:进行图案化和蚀刻,以形成金属栅极通孔开口(由于高度缩小的器件尺寸,在一些情况下可能形成得不完全),然后进行金属沉积(容易出现金属间隙填充问题)以形成金属栅极通孔,这可能导致金属栅极通孔形成得不完全和/或在金属栅极通孔内形成空隙。
根据一些实施例,所公开的切割金属方法提供了锥形的金属栅极通孔结构,其具有较小的顶部尺寸(例如,金属栅极通孔在其顶部的宽度)以及较大的底部尺寸(例如,金属栅极通孔在其底部的宽度)。与传统金属栅极通孔结构的顶部尺寸(例如,宽度)相比,该金属栅极通孔的顶部尺寸(例如,宽度)小于底部尺寸(例如,宽度),但在一些实施例中可以在尺寸上相似。此外,并且根据一些实施例,沿着金属栅极通孔的侧壁没有粘合层,从而消除寄生粘合层电阻以提供更好的器件性能。在一些实施例中,较大的底部尺寸(例如,为锥形金属栅极通孔结构所具有)在金属栅极通孔和下面的金属栅电极之间提供了较大的界面面积,从而使得界面电阻大大降低并且器件性能增强(例如,包括器件速度提高)。另外,在各个实例中,所公开的切割金属方法不需要通过蚀刻来形成金属栅极通孔开口和金属沉积(金属间隙填充),因而避免了至少一些现有实施方式所面临的挑战。结果,所公开的切割金属方法能够实现更好的工艺可行性,尤其是对于高度缩小的器件。因此,本发明的实施例用于减小金属栅极通孔和下面的金属栅电极之间的界面电阻(例如,通过提供更大的接触面积)。此外,本发明的各方面解决了与至少一些传统的超小金属栅极通孔结构相关的金属栅极通孔蚀刻和金属间隙填充问题。以下将提供本发明的实施例的更多细节,并且其他益处和/或其他优点对于受益于本发明的本领域技术人员来说是显而易见的。
现参考图2,所示出的是根据一些实施例的形成包括金属栅极通孔的接触件结构的方法200。下面参考图3A/图3B–图9A/图9B更详细地说明方法200。图3A-图9A提供了沿着一平面的器件300的截面图,该平面基本上平行于图1B的BB’截面所限定的平面(平行于栅极结构158的方向),图3B-图9B提供了沿着一平面的器件300的截面图,该平面基本上平行于图1B的AA’截面所限定的平面(垂直于栅极结构158的方向)。方法200以及本文讨论的其他方法可以在单栅极平面器件(例如以上参考图1A所述的示例性晶体管100)上、以及在多栅极器件(例如以上参考图1B所述的FinFET器件150)上实施。因此,以上参考晶体管100和/或FinFET150所述的一个或多个方面也可应用于方法200。可以肯定,在各个实施例中,该方法200以及本文所讨论的其他方法可以在其他器件上实施,例如GAA器件、Ω栅极器件、或Π栅极器件、以及应变半导体器件、SOI器件、PD-SOI器件、FD-SOI器件、或本领域已知的其他器件。
应当理解,方法200的各部分以及本文讨论的其他方法、和/或参考方法200讨论的任何示例性晶体管器件、或本文讨论的其他方法,可通过公知的互补金属氧化物半导体(CMOS)技术的工艺流程来构建,因此一些工艺在本文中仅简要描述。此外,应当理解,本文所讨论的任何示例性晶体管器件可包括各种其他器件和部件,例如附加的晶体管、双极结型晶体管、电阻器、电容器、二极管、熔丝等,但进行了简化以便更好地理解本发明的发明构思。此外,在一些实施例中,本文所公开的示例性晶体管器件(一个或多个)可包括多个半导体器件(例如,晶体管),其可以互连。另外,在一些实施例中,本发明的各个方面可以应用于后栅极工艺或先栅极工艺中的任一个。
此外,在一些实施例中,本文所示的示例性晶体管器件可以包括可在集成电路加工期间制造的处于加工中间阶段的器件或其部分,可包括静态随机存取存储器(SRAM)和/或其他逻辑电路、无源元件(例如电阻器、电容器和电感器)、以及有源元件(例如P型场效应晶体管(PFET)、N型FET(NFET)、MOSFET、CMOS晶体管、双极晶体管、高电压晶体管、高频晶体管、其他存储单元、和/或其组合。
该方法200开始于框202,其中提供了具有栅极结构以及一个或多个介电层的衬底,并且进行CMP工艺。参考图3A/图3B,并且在框202的实施例中,提供了具有衬底302且包括栅极结构304的器件300。在一些实施例中,衬底302可以与上述衬底102、152中的任一个基本相同。衬底302的在其上形成栅极结构304的区域,并且包括衬底302的在相邻栅极结构之间的区域,可以包括衬底302的有源区域。在一些实施例中,与栅极结构304相邻的区域(平行于图1B的截面AA'所限定的平面)可以包括源极区域、漏极区域或主体区域。在各个实施例中,栅极结构304可以包括形成在衬底302的上方的界面层、形成在界面层的上方的栅极介电层、以及形成在栅极介电层的上方的金属栅极(MG)层314。在一些实施例中,栅极结构304的界面层、介电层、以及金属栅极层314中的每一个可以与上述的有关晶体管100和FinFET150的内容基本相同。此外,栅极结构304可以包括侧壁间隔层316。在各个实施例中,该侧壁间隔层316包括SiOx、SiN、SiOxNy、SiCxNy、SiOxCyNz、AlOx、AlOxNy、AlN、HfO、ZrO、HfZrO、CN、poly-Si、其组合,或其它合适的介电材料。在一些实施例中,侧壁间隔层316包括多个层,例如主间隔壁、衬层等。举例来说,可通过在器件300的上方沉积介电材料并且各向异性地对介电材料进行回蚀刻来形成侧壁间隔层316。在一些实施例中,回蚀刻工艺(例如,用于间隔件的形成)可以包括多步蚀刻工艺,以提高蚀刻选择比并提供过蚀刻控制。
在框202的另一实施例中,如图3A所示,介电层310可以形成(例如,平行于图1B的BB’截面所限定的平面)在栅极结构304的金属栅极层314的相对的端部)。在一些情况下,介电层310可以在相邻器件的金属栅极层之间提供隔离。在一些实施例中,介电层310可以用切割金属栅极工艺来形成,其中,在切割金属区域内去除(例如,蚀刻)金属栅极层314的部分以形成凹槽,并且使介电层310沉积以填充凹槽并提供隔离。在各个实例中,介电层310可以包括SiC、LaO、AlO、AlON、ZrO、HfO、SiN、Si、ZnO、ZrN、ZrAlO、TiO、TaO、YO、TaCN、ZrSi、SiOCN、SiOC、SiCN、HfSi、LaO、SiO,或其组合。在一些实施例中,介电层310可以通过CVD、ALD、PVD或其他合适的工艺来沉积。
此外,如图3B所示,介电层320可以形成在衬底302的上方并且形成在栅极结构304的与侧壁间隔层316接触的任一侧上。举例来说,介电层320可以包括层间介电(ILD)层,其可包括例如以下的材料:正硅酸四乙酯(TEOS)氧化物、未经掺杂的硅酸盐玻璃、或经掺杂的硅氧化物(如硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、磷硅酸盐玻璃(PSG)、掺杂硼的硅玻璃(BSG))、和/或其他合适的介电材料。介电层320可以通过低于大气压的CVD(SACVD)工艺、可流动的CVD工艺或其他合适的沉积技术来沉积。在一些实施例中,介电层320的部分可以在处理的后续阶段除去,以形成与源极区域、漏极区域、或本体区域接触的金属层,其可设置为与栅极结构304相邻。在形成栅极结构304、侧壁间隔层316、介电层310以及介电层320后,可进行CMP工艺以去除多余的材料并使器件300的顶面平坦化。在一些实施例中,CMP工艺可以包括金属栅极CMP工艺。
方法200进行到框204,在框204进行金属栅极回蚀刻工艺。参考图3A/图3B和图4A/图4B,在框204的一实施例中,进行金属栅极回蚀刻工艺来对栅极结构304的金属栅极层314进行蚀刻并形成凹槽402。在一些实施例中,框204的回蚀刻工艺可以包括湿蚀刻工艺、干蚀刻工艺,或其组合。在一些实例中,框204的回蚀刻工艺还可以对侧壁间隔层316进行蚀刻,如图4B所示。在回蚀刻工艺之后,并且在至少一些实施例中,金属栅极层314的顶面相对于侧壁间隔层316的顶面凹进。换句话说,在回蚀刻工艺之后,金属栅极层314的顶面所限定的平面可以设置在侧壁间隔层316的顶面所限定的平面的下方。举例来说,如被回蚀刻的金属栅极层314和被回蚀刻的侧壁间隔层316所共同限定,凹槽402一般可提供T形凹槽,如图4B所示。
方法200进行到框206,在框206沉积金属覆盖层,并进行CMP工艺。参考图4A/图4B和图5A/图5B,并且在框206的实施例中,金属覆盖层502沉积在器件300的上方,包括在凹槽402内、以及在被回蚀刻的金属栅极层314和被回蚀刻的侧壁间隔层316的上方。在沉积金属覆盖层502之后,并且在一些实施例中,进行CMP工艺以去除多余的材料并使器件300的顶面平坦化。在一些实施例中,金属覆盖层502可以包括Co、W、Ru、Al、Mo、Ti、TiN、TiSi、CoSi、NiSi、Cu、TaN,或其组合。在各个实例中,金属覆盖层502可以通过PVD、CVD、ALD、电子束蒸发或其他合适的工艺来沉积。在一些情况下,金属覆盖层502的高度“H1”在约0.5nm至30nm的范围内。在一些实施例中,可选地,粘合层可形成在金属覆盖层502的下方,介于金属覆盖层502和下面的金属栅极层314之间。如果存在,则粘合层可包括Co、W、Ru、Al、Mo、Ti、TiN、TiSi、CoSi、NiSi、Cu、TaN,或其组合。但是,即使粘合层存在于金属栅极层314和金属覆盖层502之间,沿着在加工过程的后续阶段形成的图案化的金属覆盖层502(其限定器件300的金属栅极通孔)的侧壁也不会有粘合层,如下所述。另外,因为凹槽402一般限定T形凹槽,所以形成在凹槽402内的金属覆盖层502一般可限定T形金属覆盖层,如图5B所示。
方法200进行到框208,在框208形成一个或多个硬掩模层。参考图5A/图5B和图6A/图6B,在框208的实施例中,第一硬掩模层602形成在器件300的上方,第二硬掩模层604形成在第一硬掩模层602的上方。在一些实施例中,第一硬掩模层602和第二硬掩模层604可以包括蚀刻停止层。在一些情况下,硬掩模层602、604提供金属栅极通孔硬掩模,用于金属栅极通孔的图案化,以下将更详细地描述。举例来说,硬掩模层602、604可以包括Ti、TiN、TiC、TiCN、Ta、TaN、TaC、TaCN、W、WN、WC、WCN、TiAl、TiAlN、TiAlC、TiAlCN,或其组合。在各个实施例中,硬掩模层602、604可以通过SACVD工艺、可流动CVD工艺、ALD工艺、PVD工艺或其他合适的沉积技术来沉积。
方法200进行到框210,在框210进行切割金属光刻工艺。参考图6A/图6B和图7A/图7B,在框210的实施例中,切割金属光刻工艺包括:(例如,通过旋转涂布)使抗蚀剂层沉积;使抗蚀剂层曝光;以及使曝光的抗蚀剂层显影以形成图案化的抗蚀剂层702。在一些实施例中,图案化的抗蚀剂层702可用作掩模层,以限定随后形成的金属栅极通孔,如下所述。在一些实施例中,如图7A/图7B所示,图案化的抗蚀剂层702可包括锥形轮廓,其相比于较大的底部尺寸(例如,图案化的抗蚀剂层702的位于其底部的宽度),具有较小的顶部尺寸(例如,在图案化的抗蚀剂层702的位于其顶部的宽度)。在一些实施例中,锥形的图案化的抗蚀剂层702可以提供至少一部分随后形成的金属栅极通孔结构的锥形轮廓,如下所述。
方法200进行到框212,在框212进行切割金属蚀刻工艺。参考图7A/图7B和图8A/图8B,在框212的实施例中,进行切割金属蚀刻工艺,以去除硬掩模层602、604的部分、金属覆盖层502的部分、以及粘合层(如存在)的部分,其设置在被图案化的抗蚀剂层702保护的区域的外部以形成凹槽802,其使被回蚀刻的金属栅极层314以及被回蚀刻的侧壁间隔层316的部分暴露。框212的切割金属蚀刻工艺可以包括湿蚀刻工艺、干蚀刻工艺,或其组合。在一些实施例中,切割金属蚀刻工艺对硬掩模层602、604和金属覆盖层502而言是选择性的,从而切割金属蚀刻工艺对部分的硬掩模层602、604和金属覆盖层的部分502(设置在被图案化的抗蚀剂层702保护的区域的外部)进行蚀刻,而基本上不蚀刻其它附近的层(例如,介电层310、320,侧壁间隔层316,或金属栅极层314)。切割金属蚀刻工艺因此可以使部分的被回蚀刻的金属栅极层314和被回蚀刻的侧壁间隔层316暴露。在各个实施例中,在切割金属蚀刻工艺之后,图案化的抗蚀剂层702以及剩余部分的硬掩模层602、604可以去除。例如,可以使用灰化工艺、溶剂或其他合适的光刻胶剥离技术来去除图案化的抗蚀剂层702,并且可以使用湿蚀刻工艺、干蚀刻工艺,或其组合来去除剩余部分的硬掩模层602、604。
在各个实施例中,在切割金属蚀刻工艺后剩余的金属覆盖层的部分502A(例如,设置在凹槽802之间)可以限定器件300的金属栅极通孔,其提供到下面的栅极结构304的金属栅极层314的导电性。因此,金属覆盖层的部分502A可以等效地称为通孔部件。另外,在一些实施例中,金属覆盖层的部分502A可以与金属栅极层314基本对齐(例如,居中)。还应注意,尽管在金属栅极层314和金属覆盖层的部分502A之间可能存在粘合层,但如上所述,沿着金属覆盖层的部分502A的侧壁没有粘合层。同样,如图8A/图8B所示,金属覆盖层部分502A具有锥形轮廓,与其较大的底部尺寸“W2”(例如,金属覆盖层的部分502A的位于其底部的宽度)相比,其顶部尺寸“W1”(例如,金属覆盖层的部分502A的位于其顶部的宽度)较小。在一些实施例中,金属覆盖层的部分502A的顶部尺寸“W1”在约0.5nm至30nm的范围内,并且金属覆盖层的部分502A的底部尺寸“W2”在约0.5nm至40nm的范围内。关于金属覆盖层的部分502A(金属栅极通孔)以及包括金属栅极通孔的器件300的各个部件的结构和尺寸的更多细节,将在下面参考图10A/图10B来说明。
方法200进行到框214,在框214进行电介质填充和CMP工艺。参考图8A/图8B和图9A/图9B,在框214的实施例中,介电层902沉积在器件300的上方,包括在凹槽802内、在被回蚀刻的金属栅极层314的暴露部分的上方、以及在被回蚀刻的侧壁间隔层316的上方。在沉积介电层902之后,在一些实施例中,进行CMP工艺以去除多余的材料并使器件300的顶面平坦化。因此,介电层902可以在金属覆盖层的部分502A的任一侧上提供隔离部件(例如,器件300的金属栅极通孔)。在一些实施例中,介电层902可以包括SiC、LaO、AlO、AlON、ZrO、HfO、SiN、Si、ZnO、ZrN、ZrAlO、TiO、TaO、YO、TaCN、ZrSi、SiOCN、SiOC、SiCN、HfSi、LaO、SiO,或其组合。在各个实例中,介电层902可以通过CVD、ALD、PVD或其他合适的工艺来沉积。在一些实施例中,在框214的电介质填充和CMP工艺之后,金属覆盖层的部分502A、介电层902、介电层310、以及介电层320的顶面可以是基本上彼此齐平(共面)。
器件300可进行进一步的处理以形成本领域已知的各个部件和区域。例如,后续处理可以在衬底302上形成各种接触件/通孔/线和多层互连部件(例如,金属层和层间电介质),配置为连接各个部件(例如,包括金属栅极通孔)以形成可包括一个或多个器件的功能电路。在又一实例中,多层互连可以包括垂直互连(例如通孔或接触件)和水平互连(例如金属线)。各种互连部件可以采用各种导电材料,包括铜、钨和/或硅化物。在一实例中,镶嵌和/或双镶嵌工艺用于形成与铜相关的多层互连结构。而且,可以在方法200之前、之中和之后实施附加的处理步骤,并且可根据方法200的各个实施例替换或去掉上述的一些处理步骤。
现参考图10A/图10B,提供了关于金属覆盖层的部分502A(金属栅极通孔)以及包括金属栅极通孔的器件300的各种部件的结构和尺寸的更多细节。在各个实施例中,图10A提供了图9A所示的器件300的放大图,图10B提供了图9B所示的器件300的放大图。但是,图10A/10B还示出了可选的粘合层1002,其可以设置在金属栅极层314和金属覆盖层的部分502A(金属栅极通孔)之间,如上所述。图10A还示出了介电层310的横向凹槽“LR1”和金属栅极层314的垂直凹槽“VR1”,其可在例如框212的切割金属蚀刻工艺期间形成。在一些实施例中,横向凹槽“LR1”可以在约0.5nm至30nm的范围内,而垂直凹槽“VR1”可以在约0.5nm至30nm的范围内。但是,在一些情况下,可能没有横向凹槽“LR1”或垂直凹槽“VR1”。
参考图10B,在一些实施例中,可以在介电层902中形成空隙1004。如果空隙1004存在(并非总是这样),则空隙1004与介电层902的顶面之间的距离“D1”可以在约1nm至30nm的范围内。如果空隙1004存在,则其宽度尺寸“W3”可以在约0.5nm至30nm的范围内,而高度尺寸“H2”可以在约0.5nm至30nm的范围内。在一些情况下,可以在介电层902沉积期间形成空隙1004,尤其是对于间隙填充尺寸小的高度缩小的器件。但不管空隙(例如,空隙1004)是否存在于介电层902内,本发明的实施例都可以有效地防止空隙在金属栅极通孔内形成(例如,金属覆盖层部分502A)。在一些实例中,金属覆盖层502的高度“H1”可以在约0.5nm至30nm的范围内,如前所述。在一些实施例中,金属覆盖层的部分502A的顶部尺寸“W1”在约0.5nm至30nm的范围内,金属覆盖层的部分502A的底部尺寸“W2”在约0.5nm至40nm的范围内,也如前所述。在一些情况下,角度“θ1”被限定在金属覆盖层的部分502A的底部,其中角度“θ1”可以在约90度至150度的范围内。如果存在,粘合层1002的厚度“T1”可以在约0.5nm至30nm的范围内。另外,如果存在,则粘合层1002可以延伸超过金属覆盖层的部分502A约10nm的距离“D3”。另外,在一些实施例中,粘合层1002(如果存在)的尺寸“W4”在约0.5nm至50nm的范围内。在一些情况下,尺寸“W4”可以与金属覆盖层的部分502A的底部尺寸“W2”基本相同(例如,如图23所示)。在包括粘合层1002的实施例中,距离“D4”可以限定在粘合层1002的一端与相邻的侧壁间隔层316之间,其中距离“D4”约为10nm。在一些实施例中,角度“θ2”也可以限定在粘合层1002(如果存在)的底部,其中角度“θ2”可以在约90度至150度的范围内。
现参考图11,所示出的是根据一些实施例的形成包括金属栅极通孔的接触件结构的方法1100。下面参考图12A/图12B–图16A/图16B,更详细地说明方法1100。图12A-图16A提供了沿着一平面的器件1200的截面图,该平面基本上平行于图1B的BB’截面所限定的平面(平行于栅极结构158的方向),图12B-图16B提供了沿着一平面的器件1200的截面图,该平面基本上平行于图1B的AA’截面所限定的平面(垂直于栅极结构158的方向)。在各个实例中,方法1100可以类似于以上讨论的方法200。因此,以上参考方法200(和相关的器件300)讨论的一个或多个方面也可以应用于方法1100(和相关的器件1200)。另外,为了讨论的清楚,方法1100的与方法200重叠的各方面可以仅简要讨论,同时重点讨论方法1100的不同方面。
该方法1100开始于框1102,在框1102提供了具有栅极结构以及一个或多个介电层的衬底,并进行CMP工艺。参考图12A/图12B,并且在框1102的实施例中,提供了具有衬底1202且包括栅极结构1204的器件1200。在一些实施例中,衬底1202可以和衬底102、152、302基本相同,如上所述。在各个实施例中,栅极结构1204可以包括形成在衬底1202的上方的界面层、形成在界面层的上方的栅极介电层、以及形成在栅极介电层的上方的金属栅极(MG)层1214。在一些实施例中,栅极结构1204的界面层、介电层和金属栅极层1214中的每一个可以与以上关于晶体管100、FinFET150和器件300所描述的内容基本相同。在至少一些实施例中,金属栅极层1214包括Co、W、Ru、Al、Mo、Ti、TiN、TiSi、CoSi、NiSi、Cu、TaN,或其组合。另外,栅极结构1204可以包括侧壁间隔层1216,其可以与以上讨论的侧壁间隔层316基本相同。
在框1102的另一实施例中,如图12A所示,介电层1210可以形成(例如,平行于图1B的BB’截面所限定的平面)在栅极结构1204的金属栅极层1214的相对的端部)。在一些情况下,介电层1210可以在相邻器件的金属栅极层之间提供隔离,并且可以与上述介电层310基本相同。此外,如图12B所示,介电层1220可以形成在衬底1202的上方并且形成在栅极结构1204的与侧壁间隔层1216接触的任一侧上。举例来说,介电层1220可以与以上讨论的介电层320基本相同。在形成栅极结构1204、侧壁间隔层1216、介电层1210以及介电层1220后,可进行CMP工艺以去除多余的材料并使器件1200的顶面平坦化。
方法1100进行到框1104,在框208形成一个或多个硬掩模层。参考图12A/图12B和图13A/图13B,在框1104的实施例中,第一硬掩模层1302形成在器件1200的上方,第二硬掩模层1304形成在第一硬掩模层1302的上方。在一些实施例中,第一硬掩模层1302和第二硬掩模层1304可以包括蚀刻停止层。在一些情况下,硬掩模层1302、1304提供金属栅极通孔硬掩模,用于使金属栅极通孔图案化,如本文所述。在一些实施例中,硬掩模层1302、1304可以与以上讨论的硬掩模层602、604基本相同。因此,如参考方法200所讨论的,方法1100不是在硬掩模层的沉积之前进行金属栅极回蚀刻工艺并使金属覆盖层沉积,而是直接在栅极结构1204的金属栅极层1214的上方形成硬掩模层1302、1304。结果,不是用金属覆盖层来限定金属栅极通孔(如方法200中的进行),而是可以在处理的后续阶段中使金属栅极层1214的顶部图案化,以限定器件1200的金属栅极通孔,如下所述。同样,通过不进行金属栅极回蚀刻工艺和金属覆盖层沉积工艺,侧壁间隔层1216可以保持未被蚀刻。
方法1100进行到框1106,在框210进行切割金属光刻工艺。参考图13A/图13B和图14A/图14B,在框1106的实施例中,切割金属光刻工艺包括:(例如,通过旋转涂布)使抗蚀剂层沉积;使抗蚀剂层曝光;以及使曝光的抗蚀剂层显影以形成图案化的抗蚀剂层1402。在一些实施例中,图案化的抗蚀剂层1402可用作掩模层,以限定随后形成的金属栅极通孔,如本文所述。在一些实施例中,如图14A/图14B所示,图案化的抗蚀剂层1402可以包括锥形轮廓,其顶部尺寸(例如,图案化的抗蚀剂层1402的位于其顶部的宽度)较小,其底部尺寸(例如,图案化的抗蚀剂层1402的位于其底部的宽度)较大。在一些实施例中,锥形的图案化的抗蚀剂层1402可提供至少一部分随后形成的金属栅极通孔结构的锥形轮廓,如本文所述。
方法1100进行到框1108,在框212进行切割金属蚀刻工艺。参考图14A/图14B和图15A/图15B,在框1108的实施例中,进行切割金属蚀刻工艺,以去除硬掩模层1302、1304的部分以及金属栅极层1214的顶部的部分,其设置在被图案化的抗蚀剂层1402保护的区域的外部,以形成凹槽1502,其使金属栅极层1214的底部暴露。框1108的切割金属蚀刻工艺可以包括湿蚀刻工艺、干蚀刻工艺,或其组合。在一些实施例中,切割金属蚀刻工艺对硬掩模层1302、1304和金属栅极层1214而言可以是选择性的,从而切割金属蚀刻工艺对硬掩模层602、604的部分以及金属栅极层1214的顶部进行蚀刻(设置在被图案化的抗蚀剂层1402保护的区域的外部),而基本上不蚀刻其它附近的层(例如,介电层1210、1220,或侧壁间隔层1216)。在各个实施例中,在切割金属蚀刻工艺之后,例如,如上所述,可以去除图案化的抗蚀剂层1402以及硬掩模层1302、1304的剩余部分。
在各个实施例中,切割金属蚀刻工艺后剩下的金属栅极层的顶部1214A(例如,设置在凹槽1502之间)可限定器件1200的金属栅极通孔,其提供到下面的栅极结构1204的金属栅极层1214的底部的导电性。因此,金属栅极层的顶部1214A可以等效地称为通孔部件。在一些实施例中,类似于金属栅极层1214的底部,通孔部件(例如,金属栅极层的顶部1214A)可以包括多个材料层,例如一个或多个阻挡层、填充层和/或其他合适的层(例如,以上参考栅极堆叠件104或栅极结构158讨论的层)。在一些实例中,为了避免蚀刻所有的金属栅极层1214并提供所需尺寸的金属栅极层1214的顶部,可以小心地控制切割金属蚀刻工艺的参数(例如,蚀刻时间、蚀刻温度、蚀刻压力、蚀刻化学性质等)。此外,器件1200的金属栅极通孔(金属栅极层的顶部1214A)以及下面的金属栅极层1214由单个连续的金属层形成。结果,金属栅极层的顶部1214A与下面的金属栅极层1214之间的界面是连续的。这样,在金属栅极层的顶部1214A与下面的金属栅极层1214之间的界面没有粘合层。此外,与上述器件300一样,沿着金属栅极通孔的侧壁(金属栅极层的顶部1214A)也没有粘合层。在一些实施例中,金属栅极层的顶部1214A也可以与下面的金属栅极层1214的底部基本对齐(例如,居中)。
同样,如图15A/图15B,金属栅极层的顶部1214A具有锥形轮廓,其顶部尺寸“W5”(例如,金属栅极层的顶部1214A的位于其顶部的宽度)较小,其底部尺寸“W6”(例如,金属栅极层的顶部1214A的位于其底部的宽度)较大。在一些实施例中,金属栅极层的顶部1214A的顶部尺寸“W5”在约0.5nm至30nm的范围内,金属栅极层的顶部1214A的底部尺寸“W6”在约0.5nm至40nm的范围内。还应注意,(金属栅极层的顶部1214A的)底部尺寸“W6”小于(金属栅极层1214的底部的)宽度“W8”。下面参考图17A/图17B来说明关于金属栅极层的顶部1214A(金属栅极通孔)以及包括金属栅极通孔的器件1200的各种部件的结构和尺寸的更多细节。
方法1100进行到框1110,在框214进行电介质填充和CMP工艺。参考图15A/图15B和图16A/图16B,在框1110的实施例中,介电层1602沉积在器件1200的上方,包括在凹槽1502内以及在金属栅极层1214的所暴露的底部的上方。在介电层1602的沉积之后,在一些实施例中,进行CMP工艺以去除多余的材料并使器件1200的顶面平坦化。因此,介电层1602可以在金属栅极层的顶部1214A(例如,器件1200的金属栅极通孔)的任一侧上提供隔离部件。在一些实施例中,介电层1602可以与上述的介电层902基本相同。在一些实施例中,在框1110的电介质填充和CMP工艺之后,金属栅极层的顶部1214A、介电层1602、侧壁间隔层1216、介电层1210、以及介电层1220的顶面可以基本上彼此齐平(共面)。
器件1200可进行进一步的处理以形成本领域已知的各个部件和区域。例如,后续处理可以在衬底1202上形成各种接触件/通孔/线和多层互连部件(例如,金属层和层间电介质),配置为连接各个部件(例如,包括金属栅极通孔)以形成可包括一个或多个器件的功能电路。在又一实例中,多层互连可以包括垂直互连(例如通孔或接触件)和水平互连(例如金属线)。各种互连部件可以采用各种导电材料,包括铜、钨和/或硅化物。在一实例中,镶嵌和/或双镶嵌工艺用于形成与铜相关的多层互连结构。而且,可以在方法1100之前、之中和之后实施附加的处理步骤,并且可根据方法1100的各个实施例替换或去掉上述的一些处理步骤。
参考图17A/图17B,提供了关于金属栅极层的顶部1214A(金属栅极通孔)以及包括金属栅极通孔的器件1200的各个部件的结构和尺寸的更多细节。在各个实施例中,图17A所示的器件1200提供了图16A所示的器件1200的放大图,图17B所示的器件1200提供了图16B所示的器件1200的放大图。图17A还示出了介电层1210的横向凹槽“LR2”和金属栅极层1214的垂直凹槽“VR2”,其可在例如框1108的切割金属蚀刻工艺期间形成。在一些实施例中,横向凹槽“LR2”可以在约0.5nm至30nm的范围内,而垂直凹槽“VR2”可以在约0.5nm至30nm的范围内。但是,在一些情况下,可能没有横向凹槽“LR2”或垂直凹槽“VR2”。
参考图17B,在一些实施例中,可以在介电层1602中形成空隙1704。如果空隙1704存在(并非总是这样),则空隙1704与介电层1602的顶面之间的距离“D5”可以在约1nm至30nm的范围内。如果空隙1704存在,则其宽度尺寸“W7”可以在约0.5nm至30nm的范围内,而高度尺寸“H3”可以在约0.5nm至30nm的范围内。在一些情况下,可以在介电层1602沉积期间形成空隙1704,尤其是对于间隙填充尺寸小的高度缩小的器件。但不管空隙(例如,空隙1704)是否存在于介电层1602内,本发明的实施例都可以有效地防止空隙在金属栅极通孔(例如,金属栅极层的顶部1214A)内形成。在一些实例中,金属栅极层的顶部1214A的高度“H4”可以在约0.5nm至30nm的范围内。在一些实施例中,金属栅极层的顶部1214A的顶部尺寸“W5”在约0.5nm至30nm的范围内,金属栅极层的顶部1214A的底部尺寸“W6”在约0.5nm至40nm的范围内,如前所述。在一些情况下,角度“θ3”被限定在金属栅极层的顶部1214A的底部,其中角度“θ3”可以在约90度至150度的范围内。在一些实施例中,距离“D6”可以限定在金属栅极层的顶部1214A的底部边缘与相邻的侧壁间隔层1216之间,其中该距离“D6”约为10nm。
现参考图18,所示出的是根据一些实施例的形成包括金属栅极通孔的接触件结构的方法1800。下面参考图19A/图19B–图21A/图21B,更详细地说明方法1800。图19A-图21A提供了沿着一平面的器件1900的截面图,该平面基本上平行于图1B的BB’截面所限定的平面(平行于栅极结构158的方向),图19B-图21B提供了沿着一平面的器件1900的截面图,该平面基本上平行于图1B的AA’截面所限定的平面(垂直于栅极结构158的方向)。该方法1800与上述方法200基本相同,但在方法200的切割金属蚀刻工艺(框212)与电介质填充和CMP工艺(框214)之间增加了一个步骤。因此,为了讨论的清楚,方法1800的与方法200重叠的各方面仅简要地提及,同时重点讨论该方法1800呈现的附加部件。
方法1800开始于步骤1802,其包括方法200的框202-212。因此,在方法1800的步骤1802之后,参考图19A/图19B,器件1900与图8A/图8B所示的器件300基本相同,其示出了紧接在切割金属蚀刻工艺之后的器件300(框212)。这样,器件1900包括凹槽802,其暴露出被回蚀刻的金属栅极层314以及被回蚀刻的侧壁间隔层316的部分。在一些实施例中,该器件还包括切割金属蚀刻工艺后剩余的以及限定器件1900的金属栅极通孔的金属覆盖层的部分502A(例如,设置在凹槽802之间),从而提供到下面的金属栅极层314的导电性。如前所述,尽管在金属栅极层314与金属覆盖层的部分502A之间可能存在粘合层,但沿着金属覆盖层的部分502A的侧壁不存在粘合层。
代替方法200所述的接下来进行电介质填充和CMP工艺,方法1800进行到框1804,在框1804进行选择性金属沉积。参考图19A/图19B和图20A/图20B,在框1804的实施例中,金属层2002选择性地沉积在金属区域的上方,该金属区域包括金属覆盖层的部分502A以及金属覆盖层的部分502A的任一侧上被回蚀刻的金属栅极层314的暴露部分。在一些实施例中,选择性沉积的金属层2002也可以共形地沉积在金属区域的上方。但是,在各个实例中,金属层2002可能不沉积在介电层(例如,被回蚀刻的侧壁间隔层316、介电层310、以及介电层320)的上方。在一些实施例中,金属层2002可以包括Co、W、Ru、Al、Mo、Ti、TiN、TiSi、CoSi、NiSi、Cu、TaN,或其组合。在各个实例中,金属层2002可以通过PVD、CVD、ALD、电子束蒸发或其他合适的工艺来沉积。在一些实例中,金属层2002可以用于进一步减小器件1900的金属栅极通孔(例如,金属覆盖层的部分502A)的电阻。
方法1800进行到框1806,在框214进行电介质填充和CMP工艺。参考图20A/图20B和图21A/图21B,在框1806的实施例中,介电层902沉积在器件1900的上方,包括在凹槽802内、在选择性沉积的金属层2002的上方、以及在被回蚀刻的侧壁间隔层316的上方。在介电层902的沉积之后,在一些实施例中,进行CMP工艺以去除多余的材料并使器件1900的顶面平坦化。在一些实施例中,CMP工艺可以从金属覆盖层的部分502A的顶面去除金属层2002。介电层902因此可在金属覆盖层的部分502A的任一侧上提供隔离部件(例如,器件1900的金属栅极通孔)。在各个实施例中,介电层902可以与以上参考方法200的框214所述的内容基本相同。在一些实施例中,在框1806的电介质填充和CMP工艺之后,金属覆盖层的部分502A、设置在金属覆盖层的部分502A的侧壁上的金属层2002、介电层902、介电层310、以及介电层320的顶面可以基本上彼此齐平(共面)。
器件1900可进行进一步的处理以形成本领域已知的各个部件和区域。例如,后续处理可以在衬底302上形成各种接触件/通孔/线和多层互连部件(例如,金属层和层间电介质),配置为连接各个部件(例如,包括金属栅极通孔)以形成可包括一个或多个器件的功能电路。在又一实例中,多层互连可以包括垂直互连(例如通孔或接触件)和水平互连(例如金属线)。各种互连部件可以采用各种导电材料,包括铜、钨和/或硅化物。在一实例中,镶嵌和/或双镶嵌工艺用于形成与铜相关的多层互连结构。而且,可以在方法1900之前、之中和之后实施附加的处理步骤,并且可根据方法1900的各个实施例替换或去掉上述的一些处理步骤。
参考图22A/图22B,提供了关于金属覆盖层的部分502A(金属栅极通孔)、选择性沉积的金属层2002、以及包括金属栅极通孔的器件1900的各个部件的结构和尺寸的更多细节。在各个实施例中,图22A所示的器件1900提供了图21A所示的器件1900的放大图,图22B所示的器件1900提供了图21B所示的器件1200的放大图。但是,图22A/图22B还示出了可选的粘合层1002,如上所述。图22A还示出了横向凹槽“LR1”和垂直凹槽“VR1”,如上所述它们可以基本相同。例如,在一些实施例中,横向凹槽“LR1”可以在约0.5nm至30nm的范围内,垂直凹槽“VR1”可以在约0.5nm至30nm的范围内。在一些情况下,可能不存在横向凹槽“LR1”或垂直凹槽“VR1”。
图22B示出了多个部件和尺寸,其与以上参考图10B所述的部件和尺寸基本相同。例如,介电层902中的空隙1004(如存在)可以与介电层902的顶面隔开一段距离“D1”,其中“D1”可以在约1nm至30nm的范围内。空隙1004(如存在)也可以具有在约0.5nm至30nm范围内的宽度尺寸“W3”以及在约0.5nm至30nm范围内的高度尺寸“H2”。如前所述,不管空隙(例如,空隙1004)是否存在于介电层902内,本发明的实施例都可以有效地防止空隙在金属栅极通孔内形成(例如,金属覆盖层的部分502A)。如前所述,金属覆盖层502可以具有在约0.5nm至30nm范围内的高度“H1”。在一些实施例中,金属覆盖层的部分502A的顶部尺寸“W1”在约0.5nm至30nm的范围内,金属覆盖层的部分502A的底部尺寸“W2”在约0.5nm至40nm的范围内,也如前所述。在一些情况下,角度“θ1”被限定在金属覆盖层的部分502A的底部,其中角度“θ1”可以在约90度至150度的范围内。如果存在,粘合层1002的厚度“T1”可以在约0.5nm至30nm的范围内。另外,如果存在,则粘合层1002可以延伸超过金属覆盖层的部分502A约10nm的距离“D3”。另外,在一些实施例中,粘合层1002(如果存在)的尺寸“W4”在约0.5nm至50nm的范围内。在一些情况下,尺寸“W4”可以与金属覆盖层的部分502A的底部尺寸“W2”基本相同(例如,如图23所示)。在包括粘合层1002的实施例中,距离“D4”可以限定在粘合层1002的一端与相邻的侧壁间隔层316之间,其中距离“D4”约为10nm。在一些实施例中,角度“θ2”也可以限定在粘合层1002(如果存在)的底部,其中角度“θ2”可以在约90度至150度的范围内。此外,图22B示出了选择性沉积的金属层2002,其厚度“T2”在约0.5nm至30nm的范围内。
参考图24,其中示出了根据一些实施例的器件2400。在各个实例中,器件2400可以类似于器件300,并且可以根据上述的方法200来制造。但是,器件2400的不同之处在于,金属栅极层314的顶面与侧壁间隔层316的顶面基本齐平(共面)。在一些实施例中,金属栅极层314和侧壁间隔层316的共面的顶面可以在回蚀刻过程(例如,方法200的框204)中形成。在一些情况下,也可作为方法1800的部分,对金属栅极层314和侧壁间隔层316进行相似的回蚀刻工艺并形成共面的顶面(例如,在方法1800的步骤1802)。
参考图25,其中示出了根据一些实施例的器件2500。在一些实例中,器件2500可以类似于器件300,并且可以根据上述的方法200来制造。但器件2500的不同之处在于,侧壁间隔层316的顶面与金属覆盖层的部分502A的顶面、介电层902的顶面、以及介电层320的顶面基本齐平(共面)。换句话说,侧壁间隔层316延伸超出金属栅极层314的顶面,从而该金属栅极层314的顶面相对于侧壁间隔层316的顶面凹进,或者从而金属栅极层314的顶面所限定的平面设置在侧壁间隔层316的顶面所限定的平面的下方。器件2500的侧壁间隔件316可通过介电层902与金属覆盖层的部分502A分离。此外,如图所示,器件2500的侧壁间隔层316可以设置在介电层902与介电层320(例如,ILD层)之间。在一些实施例中,器件2500的制造可以包括进行回蚀刻工艺(方法200的框204),其中回蚀刻工艺对金属栅极层314进行蚀刻,而基本上没有对侧壁间隔层316进行蚀刻。在一些情况下,也可作为方法1800的部分,对侧壁间隔层316、金属覆盖层的部分502A、介电层902、以及介电层320进行相似的回蚀刻工艺并形成共面的顶面(例如,在方法1800的步骤1802)。
本文说明的各个实施例提供了几个优于现有技术的优势。应该理解,本文不一定论述了所有的优势,对所有的实施例不要求特定的优势,并且其它实施例可提供不同的优势。例如,本文讨论的实施例包括针对用于接触件结构(包括金属栅极通孔)的制造工艺的方法和结构。在一些实施例中公开了用于形成金属栅极通孔的切割金属法,用来提供到下面的金属栅电极的电接触。所公开的切割金属方法提供了锥形的金属栅极通孔结构,其具有较小的顶部尺寸(例如,金属栅极通孔在其顶部的宽度)以及较大的底部尺寸(例如,金属栅极通孔在其底部的宽度)。此外,并且根据一些实施例,沿着金属栅极通孔的侧壁没有粘合层,从而消除寄生粘合层电阻以提供更好的器件性能。在一些实施例中,较大的底部尺寸(例如,为锥形金属栅极通孔结构所具有)在金属栅极通孔和下面的金属栅电极之间也提供了较大的界面面积,从而导致界面电阻大大降低并且器件性能增强(例如,包括器件速度提高)。所公开的切割金属方法不需要通过蚀刻来形成金属栅极通孔开口和金属沉积(金属间隙填充),因而避免了至少一些现有实施方式所面临的挑战。结果,所公开的切割金属方法能够实现更好的工艺可行性,尤其是对于高度缩小的器件。因此,本发明的实施例用于减小金属栅极通孔和下面的金属栅电极之间的界面电阻(例如,通过提供更大的接触面积)。此外,本发明的各方面解决了与至少一些传统的超小金属栅极通孔结构相关的金属栅极通孔蚀刻和金属间隙填充问题。
因此,本发明的一实施例描述了包括金属栅极结构的半导体器件,该金属栅极结构具有设置在金属栅极结构的侧壁上的侧壁间隔件。在一些实施例中,金属栅极结构的顶面相对于侧壁间隔件的顶面凹进。半导体器件可进一步包括设置在金属栅极结构的上方并与金属栅极结构接触的金属覆盖层,其中金属覆盖层的底部的第一宽度大于金属覆盖层的顶部的第二宽度。在一些实施例中,半导体器件可进一步包括设置在金属覆盖层的任一侧上的介电材料,其中侧壁间隔件和金属栅极结构的部分设置在介电材料的下方。
在一些实施例中,半导体器件还包括:层间介电(ILD)层,设置为与所述金属栅极结构相邻,其中,所述层间介电层的第一侧面与侧壁间隔件的第二侧面接触,所述侧壁间隔件沿着所述金属栅极结构的侧壁设置。在一些实施例中,所述金属栅极结构的顶面和所述侧壁间隔件的顶面都相对于所述层间介电层的顶面凹进。在一些实施例中,所述金属覆盖层、所述介电材料以及所述层间介电层的顶面基本上彼此齐平。在一些实施例中,所述金属覆盖层的侧壁没有粘合层。在一些实施例中,所述金属覆盖层限定金属栅极通孔。在一些实施例中,所述金属覆盖层具有锥形轮廓。在一些实施例中,半导体器件还包括:粘合层,介于所述金属覆盖层和所述金属栅极结构之间。在一些实施例中,所述金属覆盖层的任一侧上的所述金属栅极结构的顶面相对于所述金属覆盖层的底面凹进。在一些实施例中,半导体器件还包括:选择性沉积的金属层,介于所述介电材料和所述金属覆盖层的侧壁之间,所述选择性沉积的金属层还介于所述介电材料和所述介电材料下方的所述金属栅极结构的部分之间。
在另一实施例中,讨论了包括金属栅极结构的半导体器件,该金属栅极结构具有顶部和底部。在一些实施例中,金属栅极结构的顶部具有锥形轮廓。举例来说,锥形轮廓的底面具有比锥形轮廓的顶面更大的宽度。在一些情况下,锥形轮廓的底面具有比金属栅极结构的底部的顶面小的宽度。半导体器件可以进一步包括设置在金属栅极结构的侧壁上的侧壁间隔件,其中侧壁间隔件接触金属栅极结构的底部。在一些实施例中,侧壁间隔件通过介电材料与金属栅极结构的顶部分离。在一些情况下,金属栅极结构的底部的部分设置在介电材料的下方。
在一些实施例中,半导体器件还包括:层间介电(ILD)层,设置为与所述金属栅极结构相邻,其中,所述层间介电层的第一侧面与侧壁间隔件的第二侧面接触,所述侧壁间隔件沿着所述金属栅极结构的侧壁设置。在一些实施例中,所述金属栅极结构的顶部的顶面、所述介电材料的顶面、所述侧壁间隔件的顶面以及所述层间介电层的顶面基本上彼此齐平。在一些实施例中,所述金属栅极结构的顶部的侧壁没有粘合层。在一些实施例中,所述金属栅极结构的顶部限定金属栅极通孔。
在又一实施例中,讨论了制造半导体器件的方法,该方法包括提供具有金属栅极结构的衬底,侧壁间隔件设置在金属栅极结构的侧壁上。在一些实施例中,该方法还包括对金属栅极结构和侧壁间隔件进行回蚀刻,其中金属栅极结构的顶面在回蚀刻后相对于侧壁间隔件的顶面凹进。在一些实例中,该方法还包括在被回蚀刻的金属栅极结构和被回蚀刻的侧壁间隔件的上方沉积金属覆盖层。在各个实施例中,该方法还包括通过去除金属覆盖层的部分来使金属覆盖层图案化,以暴露被回蚀刻的侧壁间隔件和至少被回蚀刻的金属栅极结构的部分。在一些实施例中,图案化的金属覆盖层提供金属栅极通孔,并且图案化的金属覆盖层的底部的第一宽度大于图案化的金属覆盖层的顶部的第二宽度。
在一些实施例中,方法还包括:在所述图案化的金属覆盖层的任一侧上以及在所暴露的被回蚀刻的侧壁间隔件和至少所述被回蚀刻的金属栅极结构的部分的上方形成介电材料。在一些实施例中,方法还包括:在所述图案化的金属覆盖层的顶面和侧壁表面上以及在至少所述被回蚀刻的金属栅极结构的部分的暴露表面上选择性地沉积金属层;以及在所述图案化的金属覆盖层的任一侧上、在所述选择性沉积的金属层的上方、以及在所暴露的被回蚀刻的侧壁间隔件的上方形成介电材料。在一些实施例中,所述使金属覆盖层图案化包括形成具有锥形侧壁轮廓的图案化的金属覆盖层,并且其中,所述锥形侧壁轮廓没有粘合层。在一些实施例中,所述使金属覆盖层图案化包括:在所述金属覆盖层的上方形成硬掩模层;在所述硬掩模层的上方形成图案化的抗蚀剂层;以及对所述硬掩模层的部分和所述金属覆盖层的部分进行蚀刻,以暴露所述被回蚀刻的侧壁间隔件和所述至少被回蚀刻的金属栅极结构的部分。
上面论述了几个实施例的特征,使得本领域技术人员可以更好地理解本发明的各个方面。本领域技术人员应当理解,他们能够容易地使用本公开作为基础来设计或修改其他工艺和结构以实现本文介绍的实施例的相同目的和/或实现本文介绍的实施例的相同优点。本领域技术人员还应该认识到,这种等效结构不脱离本公开的精神和范围,并且它们可以在不脱离本公开的精神和范围的情况下在此作出多种改变、替换和更改。
Claims (10)
1.一种半导体器件,包括:
金属栅极结构,具有设置在所述金属栅极结构的侧壁上的侧壁间隔件,其中,所述金属栅极结构的顶面相对于所述侧壁间隔件的顶面凹进;
金属覆盖层,设置在所述金属栅极结构的上方并与金属栅极结构接触,其中,所述金属覆盖层的底部的第一宽度大于金属覆盖层的顶部的第二宽度;以及
介电材料,设置在所述金属覆盖层的任一侧上,其中,所述侧壁间隔件和所述金属栅极结构的部分设置在所述介电材料的下方。
2.根据权利要求1所述的半导体器件,还包括:
层间介电(ILD)层,设置为与所述金属栅极结构相邻,其中,所述层间介电层的第一侧面与侧壁间隔件的第二侧面接触,所述侧壁间隔件沿着所述金属栅极结构的侧壁设置。
3.根据权利要求2所述的半导体器件,其中,所述金属栅极结构的顶面和所述侧壁间隔件的顶面都相对于所述层间介电层的顶面凹进。
4.根据权利要求2所述的半导体器件,其中,所述金属覆盖层、所述介电材料以及所述层间介电层的顶面基本上彼此齐平。
5.根据权利要求1所述的半导体器件,其中,所述金属覆盖层的侧壁没有粘合层。
6.根据权利要求1所述的半导体器件,其中,所述金属覆盖层限定金属栅极通孔。
7.根据权利要求1所述的半导体器件,其中,所述金属覆盖层具有锥形轮廓。
8.根据权利要求1所述的半导体器件,还包括:粘合层,介于所述金属覆盖层和所述金属栅极结构之间。
9.一种半导体器件,包括:
金属栅极结构,具有顶部和底部,其中,所述金属栅极结构的顶部具有锥形轮廓,其中,所述锥形轮廓的底面的宽度大于所述锥形轮廓的顶面的宽度,并且其中所述锥形轮廓的底面的宽度小于所述金属栅极结构的底部的顶面的宽度;以及
侧壁间隔件,设置在所述金属栅极结构的侧壁上,其中,所述侧壁间隔件与所述金属栅极结构的底部接触,其中,所述侧壁间隔件通过介电材料与所述金属栅极结构的顶部分离,并且其中,所述金属栅极结构的底部的部分设置在所述介电材料的下方。
10.一种制造半导体器件的方法,包括:
提供包括金属栅极结构的衬底,所述金属栅极结构具有设置在所述金属栅极结构的侧壁上的侧壁间隔件;
对所述金属栅极结构和所述侧壁间隔件进行回蚀刻,其中,在所述回蚀刻后,所述金属栅极结构的顶面相对于所述侧壁间隔件的顶面凹进;
在被回蚀刻的金属栅极结构和被回蚀刻的侧壁间隔件的上方沉积金属覆盖层;以及
通过去除所述金属覆盖层的部分来使所述金属覆盖层图案化,以暴露所述被回蚀刻的侧壁间隔件和至少所述被回蚀刻的金属栅极结构的部分;
其中,所述图案化的金属覆盖层提供金属栅极通孔,并且其中,所述图案化的金属覆盖层的底部的第一宽度大于所述图案化的金属覆盖层的顶部的第二宽度。
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