CN113053829A - Reconfigurable three-dimensional integrated chip structure - Google Patents
Reconfigurable three-dimensional integrated chip structure Download PDFInfo
- Publication number
- CN113053829A CN113053829A CN202110288802.7A CN202110288802A CN113053829A CN 113053829 A CN113053829 A CN 113053829A CN 202110288802 A CN202110288802 A CN 202110288802A CN 113053829 A CN113053829 A CN 113053829A
- Authority
- CN
- China
- Prior art keywords
- silicon
- chip
- packaging substrate
- adapter plate
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 184
- 239000010703 silicon Substances 0.000 claims abstract description 184
- 239000000758 substrate Substances 0.000 claims abstract description 181
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 167
- 239000011229 interlayer Substances 0.000 claims abstract description 103
- 239000010410 layer Substances 0.000 claims abstract description 65
- 238000004806 packaging method and process Methods 0.000 claims abstract description 65
- 239000003990 capacitor Substances 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 241000724291 Tobacco streak virus Species 0.000 abstract description 51
- 230000006870 function Effects 0.000 abstract description 16
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 9
- 229910000679 solder Inorganic materials 0.000 description 9
- 230000010354 integration Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000003860 storage Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000036541 health Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 150000003376 silicon Chemical class 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application relates to a reconfigurable three-dimensional integrated chip structure, in particular to the technical field of semiconductor packaging. The application provides a three-dimensional integrated chip structure of reconfigurable, the structure includes: the device comprises a shell, a silicon adapter plate, a packaging substrate and an interlayer selection chip; the packaging substrate and the silicon adapter plate are provided with silicon through holes, the packaging substrate is electrically connected with the silicon adapter plate through bumps, redistribution layers are arranged on the surfaces of the packaging substrate and the silicon adapter plate, the packaging substrate is electrically connected with the interlayer selection chip, the interlayer selection chip is used for controlling the on-off of electric signals of the silicon through holes in the packaging substrate, namely, the on-off of circuits on the redistribution layers on the surfaces of the packaging substrate and the silicon adapter plate can be controlled through the interlayer selection chip, namely, the circuits of the packaging substrate and the silicon adapter plate can be modified through the interlayer selection chip, so that the problem of modifying the performance and functions of manufactured products is solved, and the problem of failure of the whole chip caused by damage of manufactured TSVs or failure of partial devices can be solved.
Description
Technical Field
The application relates to the technical field of semiconductor packaging, in particular to a reconfigurable three-dimensional integrated chip structure.
Background
With the increasing scale of the integrated chip, the area occupied by the chip in the horizontal direction can be effectively reduced by adopting a three-dimensional integration technology, and the three-dimensional integration technology in the prior art adopts a silicon through hole to connect and stack a plurality of chips together so as to shorten the length of the chip interconnection line, increase the I/O number, reduce the interconnection line delay and ensure that the system has the advantages of small size, high performance and low power consumption. For a system packaged by adopting a three-dimensional integration technology, for example, a plurality of chips such as a CPU, an FPGA, a DRAM, and an SRAM are vertically stacked by adopting a three-dimensional integration technology based on a TSV, although the number of input/output interfaces can be increased, and an information transmission rate can be improved, thereby improving the performance of the system.
In the three-dimensional integration technology based on the TSV in the prior art, the electrical connection relation between the chip and between the chip and the substrate is realized by etching the silicon through hole on the silicon and filling the conductive material, so that the performance and the function of the manufactured product are difficult to modify, and the whole chip is failed due to the damage of the TSV or the failure of part of devices in the prior silicon through hole manufacturing technology.
Disclosure of Invention
The invention aims to provide a reconfigurable three-dimensional integrated chip structure aiming at the defects in the prior art, and aims to solve the problems that in the three-dimensional integrated technology based on TSV in the prior art, through etching silicon through holes on silicon and filling conductive substances to realize the electrical connection relationship between chips and between the chips and a substrate, the performance and the function of manufactured products are difficult to modify, and the whole chip fails due to TSV damage or partial device failure in the prior silicon through hole manufacturing technology.
In order to achieve the above purpose, the embodiment of the present invention adopts the following technical solutions:
in a first aspect, the present application provides a reconfigurable three-dimensional integrated chip structure, the structure comprising: the device comprises a shell, a silicon adapter plate, a packaging substrate and an interlayer selection chip; the packaging substrate, the silicon adapter plate and the interlayer selection chip are all arranged in the shell, redistribution layers are arranged on the surfaces of the packaging substrate and the silicon adapter plate, a plurality of silicon through holes are vertically arranged in the packaging substrate and the silicon adapter plate, the silicon adapter plate is electrically connected with the packaging substrate through bumps, and there is a gap between the package substrate and the interlayer selection chip, the interlayer selection chip is disposed in the gap, the interlayer selection chip is electrically connected with the packaging substrate and used for controlling the on-off of an electric signal of a silicon through hole in the packaging substrate, the redistribution layer of the packaging substrate is electrically connected with the silicon through hole in the packaging substrate, the redistribution layer of the silicon adapter plate is electrically connected with the silicon through hole in the packaging substrate, the redistribution layers of the packaging substrate and the silicon adapter plate are both used for being connected with an external circuit, a plurality of pins are arranged outside the shell, and the pins are connected with the packaging substrate through bumps.
Optionally, the structure further includes a plurality of substrates, the plurality of substrates are electrically connected to each other, a through-silicon via is disposed inside each substrate, and the interlayer selection chip is used for controlling on/off of an electrical signal of the substrate.
Optionally, the height of the bump between the silicon interposer and the package substrate is greater than the thickness of the interlayer selection chip.
Optionally, the aspect ratio of the through silicon via is greater than 10.
Optionally, a metal frame is further disposed outside the housing, and the pins pass through the metal frame.
Optionally, a package cover plate is disposed on a side of the housing close to the silicon interposer.
Optionally, a resistor and a capacitor are disposed on the redistribution layer on the package substrate.
Optionally, a redistribution layer on the silicon interposer is provided with a CPU, an FPGA, a resistor, and a capacitor.
The invention has the beneficial effects that:
the application provides a three-dimensional integrated chip structure of reconfigurable, the structure includes: the device comprises a shell, a silicon adapter plate, a packaging substrate and an interlayer selection chip; the packaging substrate, the silicon adapter plate and the interlayer selection chip are all arranged in the shell, redistribution layers are arranged on the surfaces of the packaging substrate and the silicon adapter plate, a plurality of silicon through holes are vertically arranged in the packaging substrate and the silicon adapter plate, the silicon adapter plate is electrically connected with the packaging substrate through bumps, and there is a gap between the package substrate and the interlayer selection chip, the interlayer selection chip is disposed in the gap, the interlayer selection chip is electrically connected with the packaging substrate and used for controlling the on-off of an electric signal of a silicon through hole in the packaging substrate, a redistribution layer of the packaging substrate is electrically connected with the silicon through hole in the packaging substrate, a redistribution layer of the silicon adapter plate is electrically connected with the silicon through hole in the packaging substrate, the redistribution layers of the packaging substrate and the silicon adapter plate are both used for being connected with an external circuit, a plurality of pins are arranged outside the shell, and the pins are connected with the packaging substrate through bumps; the packaging substrate and the silicon adapter plate are provided with silicon through holes, the packaging substrate is electrically connected with the silicon adapter plate through bumps, redistribution layers are arranged on the surfaces of the packaging substrate and the silicon adapter plate, the packaging substrate is electrically connected with the interlayer selection chip, the interlayer selection chip is used for controlling the on-off of electric signals of the silicon through holes in the packaging substrate, namely the on-off of circuits on the redistribution layers on the surfaces of the packaging substrate and the silicon adapter plate can be controlled through the interlayer selection chip, namely the circuits of the packaging substrate and the silicon adapter plate can be modified through the interlayer selection chip, and further the problem of modifying the performance and functions of manufactured products can be solved, and the problem that the whole chip fails due to TSV damage or failure of partial devices can be solved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a reconfigurable three-dimensional integrated chip structure according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an interlayer selection chip of a reconfigurable three-dimensional integrated chip structure according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another reconfigurable three-dimensional integrated chip structure according to an embodiment of the present invention.
Icon: 10-a housing; 20-a package substrate; a 30-silicon interposer; 31-a redistribution layer; a 32-through silicon via; 40-salient points; 50-selecting a chip between layers; 60-pin; 70-a metal frame; 80-encapsulating the cover plate.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are one embodiment of the present invention, and not all embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In order to make the implementation of the present invention clearer, the following detailed description is made with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a reconfigurable three-dimensional integrated chip structure according to an embodiment of the present invention; as shown in fig. 1, the present application provides a reconfigurable three-dimensional integrated chip structure, which includes: the package comprises a shell 10, a silicon adapter plate 30, a packaging substrate 20 and an interlayer selection chip 50; the package substrate 20, the silicon interposer 30 and the interlayer selection chip 50 are all disposed inside the housing 10, redistribution layers 31 are disposed on the surfaces of the package substrate 20 and the silicon interposer 30, a plurality of through silicon vias 32 are vertically disposed inside the package substrate 20 and the silicon interposer 30, the silicon interposer 30 is electrically connected to the package substrate 20 through bumps 40, a gap exists between the package substrate 20 and the interlayer selection chip 50, the interlayer selection chip 50 is disposed inside the gap, the interlayer selection chip 50 is electrically connected to the package substrate 20, the interlayer selection chip 50 is used for controlling the electrical signals of the through silicon vias 32 in the package substrate 20 to be turned on or off, the redistribution layer 31 of the package substrate 20 is electrically connected to the through silicon vias 32 in the package substrate 20, the redistribution layer 31 of the silicon interposer 30 is electrically connected to the through silicon vias 32 in the package substrate 20, and the redistribution layers 31 of the package substrate 20 and the silicon interposer 30 are both used for connecting to external circuits, a plurality of pins 60 are provided outside the housing 10, and the plurality of pins 60 are connected to the package substrate 20 through bumps 40.
The housing 10 is used to protect and wrap the silicon interposer 30, the package substrate 20 and the interlayer selection chip 50, the size and dimension of the housing 10 are determined according to actual needs, and are not specifically limited herein, a through silicon via 32 parallel to the surface of the silicon interposer 30 is disposed inside the silicon interposer 30, the through silicon via 32 is used to connect circuits on the silicon interposer 30, and the on/off of the circuits on the silicon interposer 30 is controlled by controlling the through silicon via 32 of the through silicon via 32, a redistribution layer 31 is disposed on the surface of the silicon interposer 30, the redistribution layer 31 is a surface circuit of the silicon interposer 30, generally, the redistribution layer 31 is equivalent to the wiring on the surface of the silicon interposer 30, the circuits inside the silicon interposer 30 are connected through the redistribution layer 31 and the through silicon via 32, generally, the redistribution layer is further divided into a plurality of wiring layers or a plurality of wiring layers, and a row or a column of wiring layers are electrically connected with each other, the redistribution layer on one side of the silicon interposer 30 is electrically connected through the through-silicon via 32, so that a plurality of circuits are formed in the silicon interposer 30, the package substrate 20 is electrically connected with the silicon interposer 30 through bumps 40, the bumps 40 are used for supporting and electrically connecting the package substrate 20 and the silicon interposer 30, the bumps 40 connecting the package substrate 20 and the silicon interposer 30 are generally arranged longer, so that a certain gap exists between the package substrate 20 and the silicon interposer 30, the package substrate 20 is connected with the silicon interposer 30 through the bumps 40, so that the structure of the present application is folded, the space is saved, the through-silicon via 32 parallel to the surface of the silicon interposer 30 is arranged inside the package substrate 20, the through-silicon via 32 is used for connecting the circuits on the package substrate 20, and the on-off of the circuits on the package substrate 20 is further controlled by controlling the through-silicon via 32 of the through-silicon via 32, the redistribution layer 31 is disposed on the surface of the package substrate 20, the redistribution layer 31 is a surface circuit of the package substrate 20, generally, the redistribution layer 31 is equivalent to a wiring on the surface of the package substrate 20, the circuit inside the package substrate 20 is connected through the redistribution layer 31 and the through silicon vias 32, generally, the redistribution layer is divided into a plurality of rows or a plurality of columns, the redistribution layers in one row or one column are electrically connected with each other, the interlayer selection chip 50 is electrically connected with the package substrate 20 for controlling the on/off of the electrical signals of the through silicon vias 32 in the package substrate 20, the number of the through silicon vias 32 in the package substrate 20 is plural, the interlayer selection chip 50 controls the on/off of different through silicon vias 32 in the package substrate 20, so that the circuit on the package substrate 20 is changed, that the interlayer selection chip 50 can control the on/off of the circuits on the redistribution layers 31 on the surfaces of the package substrate 20 and the silicon interposer 30, that is, the circuits of the package substrate 20 and the silicon interposer 30 can be modified by the interlayer selection chip 50, so as to achieve the purpose of modifying the performance and function of the manufactured product; and when the package substrate 20 is manufactured, if the through-silicon vias 32 on the package substrate 20 are damaged, the circuits on the package substrate 20 can be modified through the interlayer selection chip 50, so that the circuits on the package substrate 20 bypass the damaged through-silicon vias 32, and the purpose of changing the circuits on the package substrate 20 without changing the functions required to be realized by the package substrate 20 is realized through the built-in program of the interlayer selection chip 50, thereby solving the problem of failure of the whole chip caused by damage of manufactured TSVs or failure of partial devices.
In practical application, the package substrate 20 is electrically connected to the corresponding pins 60 of the housing 10 by using the bumps 40, and the bumps 40 are used to electrically interconnect the silicon interposer 30, so as to transfer the corresponding signal lines in the silicon interposer 30 to the corresponding pins 60 of the housing 10, so that the arrangement of the pins 60 of the three-dimensional integrated circuit meets the requirements of practical application; meanwhile, the package substrate 20 is electrically interconnected with the interlayer selection chip 50 by using solder balls, the package substrate 20 is simultaneously connected with the interlayer selection chip 50 and the silicon adapter plate 30, and the RDL redistribution layer 31 and the bumps 40 on the package substrate 20 provide an electrical connection path between the interlayer selection chip 50 and the silicon adapter plate 30 for exchanging signals between the interlayer selection chip 50 and the silicon adapter plate 30; the silicon adapter plate 30 is electrically interconnected with the module of the packaging substrate 20 by using the salient points 40, an electrical path between an upper interface and a lower interface of the silicon adapter plate 30 is formed by using the TSV, and the silicon adapter plate 30 is mainly used for bearing relevant processing and storage chips (such as a CPU, an HBM, an FPGA, a memory and the like) and corresponding resistance-capacitance components, so that a power supply channel is provided between the processing and storage chips in the three-dimensional integrated circuit, the length of a lead is shortened, and the signal transmission delay and loss are reduced; the interlayer selection chip 50 is electrically connected to the chip on the silicon interposer 30 through solder balls, a redistribution layer on the package substrate 20, the bumps 40 between the package substrate 20 and the silicon interposer 30, and TSVs, and the interlayer selection chip 50 is mainly used for receiving other chips or external signals and selecting a specific line to output. Because the interlayer selection chip 50 is positioned between the substrate and the silicon adapter plate 30, the special position enables the interlayer selection chip 50 to achieve the function of selecting a specific TSV from a plurality of TSVs to output signals by using the shortest connecting line length, so that the configurability of the three-dimensional integrated chip is improved, and the chip can be subjected to health management; it should be noted that the interlayer selection chip 50 may be disposed between the substrate and the silicon interposer 30, between the silicon interposer 30 and the chip, or between the chip and the chip, and this embodiment only exemplifies the case where the interlayer selection chip is disposed between the substrate and the silicon interposer 30.
In the present embodiment, the housing 10 may adopt any currently available housing 10 and corresponding packaging form that meet the quality requirement, and only a pin grid array Package (PGA) is taken as an example for description herein. The housing 10 includes pins 60, a metal frame 70, the housing 10, and an encapsulation cover 80. One end of the pin 60 is electrically connected to the corresponding bump 40 in the module of the package substrate 20, and the other end serves as a terminal. The metal frame 70, the case 10 and the package cover 80 are assembled as required.
In this embodiment, the package substrate 20 module mainly includes a package substrate 20, bumps 40, a redistribution layer, solder balls, bumps 40, devices, and an interlayer selection chip 50. The package substrate 20 is fixed to the inner case 10 of the case 10 and supports the other modules. The bumps 40 are electrically connected to corresponding pins 60 of the housing 10 on the package substrate 20. The rewiring layer is arranged on the packaging substrate 20 and is electrically connected with the salient point 40, the corresponding silicon through hole 32, the salient point 40, the interlayer selection chip 50 and the silicon adapter plate 30, and is used for switching corresponding signal lines in the silicon adapter plate 30 to corresponding pins 60 of the packaging substrate 20 and forming electrical connection between the interlayer selection chip 50 and the silicon adapter plate 30, so that the pins 60 of the three-dimensional integrated circuit are arranged to meet the requirements of practical application, and the selection function of the interlayer selection chip 50 on different TSVs is met; the solder balls are used for welding a chip (such as the interlayer selection chip 50) and a device (such as a resistor, a capacitor and the like) on the rewiring layer of the packaging substrate 20 to form interconnection of the chip and the device; the bumps 40 on the package substrate 20 are connected to the TSVs of the silicon interposer 30, which not only functions to electrically connect but also supports the modules on the package substrate 20. The interlayer selection chip 50 and the devices are on top of the corresponding solder balls and RDLs and form corresponding electrical connections. The package substrate 20 module is located at the bottom layer of the three-dimensional integrated circuit, and components such as resistors and capacitors can be mounted on the package substrate, which is beneficial to saving chip area.
In the present embodiment, the silicon interposer 30 module mainly includes a silicon interposer 30, a resistance-capacitance element, a TSV, a redistribution layer, a solder ball, a micro bump 40, and a chip. The silicon interposer 30 is fixed to the package substrate 20 and supports the rest of the module. The silicon adapter plate 30 module is mainly used for bearing high-density chips, and the chips can quickly transmit signals through TSV, so that a quick communication channel is provided between processing and storage chips in the three-dimensional integrated circuit; the resistor and the capacitor are directly manufactured on the silicon adapter plate 30, so that the utilization rate of the silicon adapter plate 30 is improved, and the integration level is improved; the TSVs are electrically connected to the corresponding bumps 40 on the package substrate 20 on the corresponding bumps 40 on the silicon interposer 30; the rewiring RDL layer is arranged on the silicon adapter plate 30, is electrically connected with the corresponding TSV, the salient point 40, the chip and the device, and is used for forming interconnection among the chip and the device in the silicon adapter plate 30, the corresponding signal line, the power line, the packaging substrate 20 module and the like; the solder balls are used for welding a chip (such as a CPU, an FPGA, an HBM and the like) and a device on the rewiring layer of the silicon adapter plate 30 to form interconnection of the chip and the device; the micro-bumps 40 on the HBM connect the multiple layers of HBMs, so that the electrical connection effect is realized, and the storage chips on the silicon adapter plate 30 are supported, so that the chip area is saved, and the information transmission rate is improved; the chips are over the corresponding solder balls, microbumps 40 and RDLs and form corresponding electrical connections. The resistor and the capacitor are directly manufactured on the silicon adapter plate 30, so that the utilization rate of the silicon adapter plate 30 is improved, and the integration level is improved.
In this embodiment, the interlayer selection chip 50 is bonded to the RDL layer of the package substrate by solder balls, and is electrically connected to the chip by the bumps 40, the redistribution layer on the package substrate 20, the bumps 40 between the package substrate 20 and the silicon interposer 30, and the TSVs. The interlayer selection chip 50 has four types of ports: the device comprises an enabling end, a selecting end, a data input end and a data output end. The enable terminal is used for controlling the working state of the interlayer selection chip 50, and in the working mode, the interlayer selection chip 50 transmits a signal to a designated TSV; the selection end controls the port state of the data output end by receiving the selection signal, and can control the signal of the data input end to be transmitted to the designated TSV; the data input end is used for receiving signals from the outside of the interlayer selection chip 50, and data are transmitted to the designated TSV through the interlayer selection chip 50, so that flexible configuration of the TSV can be achieved; the data output end is used for outputting data, and the working state of the port of the data output end is controlled by the selection end. When enabled, the port will transmit a signal from the data input; when enabled is disabled, the port will remain at a certain potential (high or low) and will not change. Placing the interlayer selection chip 50 between the substrate and the silicon interposer 30 can reduce the chip area while accomplishing optimization of conventional three-dimensional integrated chips. It should be noted that the interlayer selection chip 50 may be disposed between the substrate and the silicon interposer 30, between the silicon interposer 30 and the chip, or between the chip and the chip, and this embodiment only exemplifies the case where the interlayer selection chip is disposed between the substrate and the silicon interposer 30. The interlayer selection chip 50 is characterized in that the interlayer selection chip 50 is located between layers, the interlayer selection chip 50 is connected to a plurality of TSVs, and data can be selectively transmitted to some of the TSVs to realize the function of selecting the TSVs. Because the silicon through hole 32 is etched on the silicon and conductive substances are filled in the silicon through hole to form the through silicon electrical connection in the conventional TSV manufacturing process, the TSV manufacturing process is not mature, the TSV yield is not high, and the problem that the residual TSV is difficult to repair by reworking in the chip manufacturing process is caused. According to the method, the TSV selection characteristics of the interlayer selection chip 50 are utilized, the data output end of the interlayer selection chip 50 is connected to the reserved redundant TSV, signals are applied to the selection end, the data channel skips over the residual TSV channel, and the data channel is switched to the spare redundant TSV channel. The interlayer selection chip 50 of the present invention can greatly solve the problem of difficulty in reworking the TSV, and can solve the problem of chip failure caused by the incomplete TSV. According to the invention, by utilizing the TSV selection characteristic of the interlayer selection chip 50, the data output end of the interlayer selection chip 50 is connected to chip selection ports of different chips through the TSV, and signals are applied to the selection end and the data input end so that part of the chips can be selectively started or shielded, and the flexible configuration of the chips is realized. For example, a three-dimensional memory chip (e.g., 3D-SRAM) manufactured by using a three-dimensional integration technology, the interlayer selection chip 50 of the present invention can realize chip selection control on each layer of memory die, and close an idle memory die, thereby reducing chip power consumption and improving chip configurability. In addition, the data output end of the interlayer selection chip 50 is connected to the chip selection ports of different chips through TSVs, and may also be used to shield fault units, so as to achieve flexible configuration of the chips (for example, an original chip includes 8 CPU DIEs, but fails 2, the interlayer selection chip 50 shields the failed 2 CPU DIEs, and encapsulates the remaining 6 CPU DIEs and other components into a low-performance chip), thereby reducing cost loss caused by the defective chips. According to the invention, by utilizing the TSV selection characteristic of the interlayer selection chip 50, the data output end of the interlayer selection chip 50 is connected to the reserved redundant TSV through the TSV, the selection end monitors the resistance R change of the TSV, if the resistance value change delta R of the monitored TSV exceeds the threshold value, the selection end controls the data output end to be switched to the spare redundant TSV, the fault TSV can be automatically detected in the chip, the TSV switching is realized, and the health management function of the chip is realized.
In conclusion, by adopting a reconfigurable three-dimensional integrated structure, the problems of difficult rework, difficult configuration and low yield of the traditional three-dimensional integrated chip can be solved; and the reliability of the chip can be greatly improved.
To explain the interlayer selection chip 50 more specifically, fig. 2 is a schematic structural diagram of an interlayer selection chip of a reconfigurable three-dimensional integrated chip structure according to an embodiment of the present invention; as shown in fig. 2, the present embodiment uses an 8-way TSV interlayer selection chip 50 as an example to explain the operation principle of the interlayer selection chip 50, and the function of the interlayer selection chip 50 can be used to explain the function of the interlayer selection chip.
In this embodiment, the ports a, B, and C are used as control ports, and each of the different combinations corresponds to an output port Y; the port G1 serves as a data input, the data of which is transmitted to the corresponding output Y; port(s)
As a result of the selection terminal, the terminal,
and
low, the chip 50 is selected between layersThe operation is normal. In this embodiment, the interlayer selection chip 50 may transmit the substrate signal to the designated TSV through RDL rewiring, so as to implement the gating function of the interlayer selection chip 50 on multiple TSVs.
Optionally, the structure further includes a plurality of substrates, the plurality of substrates are electrically connected to each other, a through-silicon via 32 is disposed inside each substrate, and the interlayer selection chip 50 is used for controlling on/off of an electrical signal of the substrate.
The structure of the present application further includes a plurality of substrates, the specific functions of the plurality of substrates are determined according to actual needs, and are not specifically limited herein, the specific structure of the substrate is the same as the structural substrate of the package substrate 20, and the plurality of substrates are electrically connected to each other and to the package substrate 20, and then the interlayer selection chip 50 can also control the package substrate 20 and the plurality of substrates, if the calculation force of the interlayer selection chip 50 is insufficient, the plurality of interlayer selection chips 50 can be set to respectively control the on-off of the through silicon vias 32 in the substrate, and further control the circuit in the substrate.
Optionally, the height of the bump 40 between the silicon interposer 30 and the package substrate 20 is greater than the thickness of the interlayer selection chip 50.
When the bump 40 between this silicon interposer 30 and the packaging substrate 20 supports this silicon interposer 30, form the clearance between silicon interposer 30 and packaging substrate 20 for this layer is selected chip 50 and can be set up in this clearance between the layer, has reduced the whole volume of the structure of this application, makes the structure of this application integrate more.
Optionally, the aspect ratio of the through silicon via 32 is greater than 10.
Typically, the through-silicon via 32 is filled with copper plating, and the through-silicon via 32 has a pore diameter smaller than 20 microns and a pore depth larger than 100 microns, so that the aspect ratio of the through-silicon via 32 is larger than 10.
FIG. 3 is a schematic structural diagram of another reconfigurable three-dimensional integrated chip structure according to an embodiment of the present invention; as shown in fig. 3, a metal frame 70 is optionally further disposed outside the housing 10, and the pins 60 pass through the metal frame 70.
Referring to fig. 3, optionally, a package cover plate 80 is disposed on a side of the housing 10 close to the silicon interposer 30.
The bottom surface of the housing 10 is further provided with a metal frame 70, the plurality of pins 60 pass through the metal frame 70, the upper surface of the case is further provided with a package cover plate 80, one end of each pin 60 is electrically connected with the corresponding bump 40 in the first substrate module, and the other end of each pin is used as a leading-out terminal. The metal frame 70, the case 10 and the package cover 80 are assembled as required.
Optionally, a resistor and a capacitor are disposed on the redistribution layer 31 on the package substrate 20.
The circuit on the package substrate 20 is provided with devices such as resistors and capacitors, and the connection mode, circuit, type and number of the devices are determined according to actual needs, and are not specifically limited herein.
Optionally, a CPU, an FPGA, a resistor, and a capacitor are disposed on the redistribution layer 31 on the silicon interposer 30.
The circuit on the silicon interposer 30 is provided with devices such as a CPU, an FPGA, a resistor, and a capacitor, and the connection mode, the circuit, the kind, and the number of the devices are determined according to actual needs, and are not specifically limited herein.
The application provides a three-dimensional integrated chip structure of reconfigurable, the structure includes: the package comprises a shell 10, a silicon adapter plate 30, a packaging substrate 20 and an interlayer selection chip 50; the package substrate 20, the silicon interposer 30 and the interlayer selection chip 50 are all disposed inside the housing 10, redistribution layers 31 are disposed on the surfaces of the package substrate 20 and the silicon interposer 30, a plurality of through silicon vias 32 are vertically disposed inside the package substrate 20 and the silicon interposer 30, the silicon interposer 30 is electrically connected to the package substrate 20 through bumps 40, a gap exists between the package substrate 20 and the interlayer selection chip 50, the interlayer selection chip 50 is disposed inside the gap, the interlayer selection chip 50 is electrically connected to the package substrate 20, the interlayer selection chip 50 is used for controlling the electrical signals of the through silicon vias 32 in the package substrate 20 to be turned on or off, the redistribution layer 31 of the package substrate 20 is electrically connected to the through silicon vias 32 in the package substrate 20, the redistribution layer 31 of the silicon interposer 30 is electrically connected to the through silicon vias 32 in the package substrate 20, and the redistribution layers 31 of the package substrate 20 and the silicon interposer 30 are both used for connecting to external circuits, a plurality of pins 60 are arranged outside the housing 10, and the plurality of pins 60 are connected with the package substrate 20 through bumps 40; the package substrate 20 and the silicon interposer 30 are both provided with through-silicon vias 32, the package substrate 20 and the silicon interposer 30 are electrically connected through bumps 40, redistribution layers 31 are respectively provided on the surfaces of the package substrate 20 and the silicon interposer 30, the package substrate 20 is electrically connected with the interlayer selection chip 50, the interlayer selection chip 50 is used for controlling the on-off of electrical signals of the through-silicon vias 32 in the package substrate 20, that is, the on-off of circuits on the redistribution layers 31 on the surfaces of the package substrate 20 and the silicon interposer 30 can be controlled through the interlayer selection chip 50, that is, the circuits of the package substrate 20 and the silicon interposer 30 can be modified through the interlayer selection chip 50, so that the problem of modifying the performance and functions of manufactured products is realized, and the problem of failure of manufactured TSVs or partial devices to cause the failure of an integral chip can be solved.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A reconfigurable three-dimensional integrated chip structure, the structure comprising: the device comprises a shell, a silicon adapter plate, a packaging substrate and an interlayer selection chip; the packaging substrate, the silicon adapter plate and the interlayer selection chip are all arranged in the shell, redistribution layers are arranged on the surfaces of the packaging substrate and the silicon adapter plate, a plurality of silicon through holes are vertically arranged in the packaging substrate and the silicon adapter plate, the silicon adapter plate is electrically connected with the packaging substrate through convex points, gaps exist between the packaging substrate and the interlayer selection chip, the interlayer selection chip is arranged in the gaps and is electrically connected with the packaging substrate, the interlayer selection chip is used for controlling the on-off of electric signals of the silicon through holes in the packaging substrate, the redistribution layers of the packaging substrate are electrically connected with the silicon through holes in the packaging substrate, the redistribution layers of the silicon adapter plate are electrically connected with the silicon through holes in the packaging substrate, and the redistribution layers of the packaging substrate and the silicon adapter plate are both used for being connected with an external circuit, the packaging substrate is characterized in that a plurality of pins are arranged outside the shell and connected with the packaging substrate through bumps.
2. The reconfigurable three-dimensional integrated chip structure of claim 1, further comprising a plurality of substrates electrically connected to each other, wherein a through silicon via is disposed in each of the substrates, and the interlayer selection chip is configured to control on/off of an electrical signal of the substrate.
3. The reconfigurable three-dimensional integrated chip structure of claim 1, wherein a height of the bump between the silicon interposer and the package substrate is greater than a thickness of the interlayer selection chip.
4. The reconfigurable three-dimensional integrated chip structure of claim 1, wherein the through-silicon-via has an aspect ratio greater than 10.
5. The reconfigurable three-dimensional integrated chip structure of claim 1, wherein a metal frame is further disposed outside the housing, and the pins pass through the metal frame.
6. The reconfigurable three-dimensional integrated chip structure of claim 1, wherein a side of the housing proximate to the silicon interposer is provided with a package cover plate.
7. The reconfigurable three-dimensional integrated chip structure of claim 1, wherein a resistor and a capacitor are disposed on the redistribution layer on the package substrate.
8. The reconfigurable three-dimensional integrated chip structure of claim 1, wherein a CPU, an FPGA, a resistor, and a capacitor are disposed on the redistribution layer on the silicon interposer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110288802.7A CN113053829B (en) | 2021-03-18 | Reconfigurable three-dimensional integrated chip structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110288802.7A CN113053829B (en) | 2021-03-18 | Reconfigurable three-dimensional integrated chip structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113053829A true CN113053829A (en) | 2021-06-29 |
| CN113053829B CN113053829B (en) | 2024-07-02 |
Family
ID=
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110079923A1 (en) * | 2009-10-07 | 2011-04-07 | Qualcomm Incorporated | Vertically Stackable Dies Having Chip Identifier Structures |
| US20140062587A1 (en) * | 2012-09-06 | 2014-03-06 | Kabushiki Kaisha Toshiba | Semiconductor device having stacked chips |
| CN103780243A (en) * | 2014-01-28 | 2014-05-07 | 合肥工业大学 | Three-dimensional chip redundant TSV fault-tolerant structure with function of transferring signal |
| KR101439191B1 (en) * | 2013-06-10 | 2014-09-12 | 한국과학기술원 | Interposer, method for manufacturing the same, 3-dimensional integrated circuit, 3-dimensional integrated circuit chip package |
| US20160070842A1 (en) * | 2014-09-05 | 2016-03-10 | International Business Machines Corporation | Integrated circuit design changes using through-silicon vias |
| CN110544673A (en) * | 2019-09-12 | 2019-12-06 | 西安电子科技大学 | Multilayer fused three-dimensional system integrated structure |
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110079923A1 (en) * | 2009-10-07 | 2011-04-07 | Qualcomm Incorporated | Vertically Stackable Dies Having Chip Identifier Structures |
| CN102576564A (en) * | 2009-10-07 | 2012-07-11 | 高通股份有限公司 | Vertically stackable dies having chip identifier structures |
| US20140062587A1 (en) * | 2012-09-06 | 2014-03-06 | Kabushiki Kaisha Toshiba | Semiconductor device having stacked chips |
| KR101439191B1 (en) * | 2013-06-10 | 2014-09-12 | 한국과학기술원 | Interposer, method for manufacturing the same, 3-dimensional integrated circuit, 3-dimensional integrated circuit chip package |
| CN103780243A (en) * | 2014-01-28 | 2014-05-07 | 合肥工业大学 | Three-dimensional chip redundant TSV fault-tolerant structure with function of transferring signal |
| US20160070842A1 (en) * | 2014-09-05 | 2016-03-10 | International Business Machines Corporation | Integrated circuit design changes using through-silicon vias |
| CN110544673A (en) * | 2019-09-12 | 2019-12-06 | 西安电子科技大学 | Multilayer fused three-dimensional system integrated structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10445269B2 (en) | Stacked semiconductor device assembly in computer system | |
| CN108155174B (en) | Semiconductor memory device including stacked chips and memory module having the same | |
| US11302674B2 (en) | Modular stacked silicon package assembly | |
| US9349707B1 (en) | Contact arrangements for stackable microelectronic package structures with multiple ranks | |
| KR20180049936A (en) | Semiconductor package and method of manufacturing the semiconductor package | |
| KR20230161526A (en) | High density 3d interconnect configuration | |
| CN113410223B (en) | Chip set and method for manufacturing the same | |
| US20220189934A1 (en) | Backside Interconnection Interface Die For Integrated Circuits Package | |
| KR101251916B1 (en) | Semiconductor integrated circuit | |
| CN116108900A (en) | Accelerator structure, method of generating accelerator structure, and apparatus therefor | |
| US11328997B2 (en) | Through-core via | |
| CN116544206A (en) | Wafer level integrated structure with separated substrate | |
| CN116387260A (en) | Wafer-level integrated structure for heterogeneous chips | |
| US20230230902A1 (en) | Semiconductor package structure and manufacturing method thereof | |
| CN113053829B (en) | Reconfigurable three-dimensional integrated chip structure | |
| CN110544673B (en) | Multilayer fused three-dimensional system integrated structure | |
| CN113053829A (en) | Reconfigurable three-dimensional integrated chip structure | |
| US20210167038A1 (en) | Dual in-line memory module | |
| US9337170B1 (en) | Contact arrangements for stackable microelectronic package structures | |
| US20160079210A1 (en) | Semiconductor packages including through electrodes and methods of manufacturing the same | |
| CN112786529A (en) | High density pillar interconnect conversion with stack-to-substrate connection | |
| CN112397475A (en) | Fan-out type packaging chip structure and unit with fine-pitch through-silicon-via packaging | |
| US20220375900A1 (en) | Stacked semiconductor device | |
| CN215955274U (en) | Three-dimensional heterogeneous integrated programmable chip structure and electronic equipment | |
| CN220306254U (en) | Semiconductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |