CN113053437A - Semiconductor device, semiconductor device assembly, and computing apparatus - Google Patents
Semiconductor device, semiconductor device assembly, and computing apparatus Download PDFInfo
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- CN113053437A CN113053437A CN202110596764.1A CN202110596764A CN113053437A CN 113053437 A CN113053437 A CN 113053437A CN 202110596764 A CN202110596764 A CN 202110596764A CN 113053437 A CN113053437 A CN 113053437A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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Abstract
The application provides a semiconductor device, semiconductor device assembly and computing equipment, the semiconductor device is connected with a memory device, and comprises a processor module and a related circuit module corresponding to the memory device; wherein the related circuit module comprises a comparison circuit and a peripheral circuit corresponding to the memory device. According to the three-dimensional packaging method and device, the related circuit modules corresponding to the processor module and the memory device are arranged in the same semiconductor device, the semiconductor device and the memory device are stacked and arranged, 3D packaging is carried out, the size of a silicon wafer occupied by TCAM is greatly reduced, and the storage capacity is improved.
Description
Technical Field
The present application relates to the field of semiconductor packaging technologies, and in particular, to a semiconductor device, a semiconductor device assembly, and a computing apparatus.
Background
Tcam (ternary content addressable memory) is a ternary content addressable memory, and is mainly used for quickly searching items such as ACL and routing. It is developed from the basis of Content Addressable Memory (CAM).
The general CAM memory has only two states of each bit, 0 or 1, and the TCAM has three states of each bit, except 0 and 1, and a don't care state, so called "tri-state", which is realized by mask, and it is the third state feature of the TCAM that can not only perform exact match search, but also perform fuzzy match search.
In the prior art, a package of a TCAM and a processor corresponding to the TCAM is a 2.5D package, the TCAM and the processor corresponding to the TCAM are disposed on an interposer side by side, and are interconnected by a connector disposed on the interposer, and connected to a package substrate. However, with this structure, the space, cost and heat generated by TCAM are larger than those of a conventional Random Access Memory (RAM), and the storage capacity is affected.
Disclosure of Invention
In view of the above problems, the present application provides a semiconductor device, a semiconductor device assembly, and a computing apparatus, which solve the technical problems of large space occupied by TCAM and influence on storage capacity caused by 2.5D packaging in the prior art.
In a first aspect, the present application provides a semiconductor device, connected to a memory device, including a processor module, and an associated circuit module corresponding to the memory device;
wherein the related circuit module comprises a comparison circuit and a peripheral circuit corresponding to the memory device.
In some embodiments, in the semiconductor device described above, the processor module includes a graphics processor, a central processing unit, or a system on a chip.
In some embodiments, in the semiconductor device described above, the processor module includes a plurality of processing cores, wherein each processing core includes a level one instruction cache and a level one data cache.
In some embodiments, in the above semiconductor device, the comparison circuit includes a look-up line, a match line, and a comparison cell matrix.
In some embodiments, in the above semiconductor device, the peripheral circuit includes an address decoder, a comparison data driver, a bit line data driver, a search line pre-discharger, a match line pre-charger, a match line sense amplifier, and an encoder.
In some embodiments, in the above semiconductor device, the related circuit module further includes a controller unit communicatively connected to the peripheral circuit.
In some embodiments, in the above semiconductor device, the controller unit includes:
a control register for setting the memory device;
the keyword memory is used for caching the data to be searched;
and the query result storage is used for caching the query results of the plurality of processing processes.
In a second aspect, the present application provides a semiconductor device assembly comprising:
the semiconductor device according to any one of the first aspect;
a memory device located over the semiconductor device; wherein the memory device is connected with the processor module in the semiconductor device through a first connecting piece, and the memory device is connected with the relevant circuit module in the semiconductor device through a second connecting piece;
a package substrate positioned under the semiconductor device; wherein the package substrate is connected to the processor module in the semiconductor device through a third connection member.
In some embodiments, in the above semiconductor device assembly, the memory device comprises a tri-state content addressable memory.
In some embodiments, in the above semiconductor device assembly, the memory device comprises at least one memory cell stacked on one another;
and the memory units are interconnected through a fourth connecting piece.
In some embodiments, in the above semiconductor device assembly, each of the memory cells includes at least one bank for storing data.
In a third aspect, the present application provides a computing device comprising:
a semiconductor device assembly as recited in any of the second aspects;
a memory unit communicatively connected to the semiconductor devices in the semiconductor device assembly for running program codes or buffering data;
the program control unit is in communication connection with the memory unit;
the query unit is in communication connection with the program control unit and is used for acquiring a query request;
an I/O interface unit communicatively connected with the semiconductor device and the memory device in the semiconductor device assembly for inputting data and outputting processing results.
In some embodiments, the above computing device further includes:
a read-only memory communicatively connected with the semiconductor devices and the memory devices in the semiconductor device assembly;
a random access memory communicatively connected with the semiconductor devices and the memory devices in the semiconductor device assembly.
Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:
the application provides a semiconductor device, semiconductor device assembly and computing equipment, the semiconductor device is connected with a memory device, and comprises a processor module and a related circuit module corresponding to the memory device; wherein the related circuit module comprises a comparison circuit and a peripheral circuit corresponding to the memory device. According to the three-dimensional packaging method and device, the related circuit modules corresponding to the processor module and the memory device are arranged in the same semiconductor device, the semiconductor device and the memory device are stacked and arranged, 3D packaging is carried out, the size of a silicon wafer occupied by TCAM is greatly reduced, and the storage capacity is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not to limit the application. In the drawings:
FIG. 1 is a connection block diagram of a TCAM;
FIG. 2 is a block diagram of a TCAM memory core connection;
fig. 3 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment of the present application;
FIG. 4 is a block diagram illustrating the connection of a semiconductor device according to an exemplary embodiment of the present application;
FIG. 5 is a schematic diagram illustrating the connection of a comparison circuit according to an exemplary embodiment of the present application;
FIG. 6 is a schematic diagram of a controller unit shown in an exemplary embodiment of the present application;
fig. 7 is a schematic cross-sectional view of a semiconductor device assembly according to an exemplary embodiment of the present application;
FIG. 8 is a connection block diagram of a semiconductor device assembly shown in an exemplary embodiment of the present application;
FIG. 9 is a schematic diagram illustrating a computing device according to an exemplary embodiment of the present application;
in the drawings, like parts are designated with like reference numerals, and the drawings are not drawn to scale.
Detailed Description
The following detailed description will be provided with reference to the accompanying drawings and embodiments, so that how to apply the technical means to solve the technical problems and achieve the corresponding technical effects can be fully understood and implemented. The embodiments and various features in the embodiments of the present application can be combined with each other without conflict, and the formed technical solutions are all within the scope of protection of the present application. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
It will be understood that spatial relationship terms, such as "above", "below", "beneath", and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" other elements would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the present application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing.
In order to provide a thorough understanding of the present application, detailed structures and steps will be provided in the following description in order to explain the technical solutions proposed in the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.
As shown in fig. 1, the TCAM device 10 includes at least one memory cell 11 and peripheral circuits (not labeled).
Peripheral circuits are disposed around the memory cell 11, and include an address decoder (decode circuit) 121, a comparison data driver 122, a bit line data (decode and) driver 123, a search line pre-discharger 124, a match line pre-charger 125, a match line sense amplifier 126, and an encoder 127.
The address decoder 121 is connected to the memory cells 11 via a plurality of word lines (n word lines, WL 0-WLn).
The compare data driver 122 is connected to the look-up line pre-discharger 124 through a plurality of look-up lines (n look-up lines, SL 0-SLn).
The search line pre-discharger 124 is directly connected to the memory cell 11.
The bit line data driver 123 is connected to the memory cells 11 via a plurality of bit lines (n bit lines, BL0 to BLn).
The match line precharger 125 is directly connected to the memory cell 11.
The matchline sense amplifier 126 is connected to the matchline pre-charger 125 via matchlines (n matchlines, ML 0-MLn).
The encoder 127 is connected to the matchline sense amplifier 126 via a number of matchlines (n matchlines, ML 0-MLn). The encoder 127 includes a match line encoder and a priority logic encoder.
The memory cell 11 is mainly responsible for storing and comparing data, the comparison result is represented by a voltage change on a Match Line (ML), a match is represented when ML is high level, a mismatch is represented when ML is low level, the match result is amplified by the match line sense amplifier 126 (SA), the match result is output by the match signal generator, and finally the fault match address with the highest priority is output by the priority address encoder. The matching signal generator gives a matching result by judging a matching signal of each word amplified by the SA, when all the words in all the storage units are not matched, the matching signal is at a low level, otherwise, the matching signal is at a high level to indicate that the matching result exists; the address decoder is used for decoding the address when the TCAM read-write operation is finished; and the Search Line (SL) driver is used for loading search data onto the Search Line (SL).
As shown in fig. 2, a TCAM has a plurality of cells (cells) in a memory core, each cell having two memory circuit components (memory cells 11) and one comparison circuit 13.
The embodiment of the present application provides a semiconductor device 20. Referring to fig. 3 and 4, the semiconductor device 20, which is connected to a memory device (not shown), includes a processor module 21 and an associated circuit module 22 corresponding to the memory device.
The related circuit module 22 includes a comparison circuit 221 corresponding to the memory device, a peripheral circuit 222, and a controller unit 223.
In some embodiments, the processor module 21 includes a Graphics Processing Unit (GPU), a Central Processing Unit (CPU), or a System-on-a-chip (SOC).
The memory device includes a Ternary Content Addressable Memory (TCAM). The memory device includes at least one memory cell.
In some embodiments, the processor module 21 includes multiple processing cores (cores), where each processing Core includes a level one Instruction Cache (IC) and a level one Data Cache (DC).
In some embodiments, the processor module 21 includes a level two cache (not shown) and a memory controller (not shown), among others.
In some embodiments, as shown in fig. 5, the compare circuit 221 includes a look-up line (SL), a Match Line (ML), a matrix of compare cells, and a connection unit 2212 for connecting the matrix of compare cells and the memory device. The comparison circuit 221 is used to obtain data from the memory cells for comparison.
Wherein the comparison unit matrix comprises a plurality of comparison units 2211
Wherein the comparison unit 2211 is disposed at the intersection of the look-up line (SL) and the Match Line (ML).
The look-up line (SL) is also connected to a key memory (i.e., input register) 2232 in the controller unit 223.
The Match Line (ML) is also connected to a match line sense amplifier 2226 in the peripheral circuitry 222.
The connection unit 2212 connects the comparison unit matrix and the storage unit in the memory device to store three kinds of state information of each bit.
In some embodiments, peripheral circuitry 222 includes an address decoder (decode circuitry), a compare data driver, bit lines, bit line data drivers (including write/look-up bit line decode and drivers), a look-up line pre-discharger, a match line pre-charger, a match line sense amplifier, and an encoder.
In some embodiments, peripheral circuitry 222 also includes match sensing circuitry.
In some embodiments, as shown in fig. 6, controller unit 223 includes a control register 2231, a key store 2232, and a query results store 2233.
And the key word memory 2232 is used for caching the data to be searched.
And a query result storage 2233 for caching the query results of the plurality of processes.
The semiconductor device 20 provided by the embodiment of the present application is connected to a memory device, and includes a processor module 21, and a related circuit module 22 corresponding to the memory device; the related circuit module 22 includes a comparison circuit 221 and a peripheral circuit 222 corresponding to the memory device. By providing the processor module 21 and the associated circuit module 22 corresponding to the memory device in the same semiconductor device 20, the size of the package can be greatly reduced.
The present embodiments also provide a semiconductor device assembly. Referring to fig. 7, the semiconductor device assembly includes the semiconductor device 20, the memory device 30, and the package substrate 40 described above.
The memory device 30 is located above the semiconductor device 20. Wherein the memory device 30 is connected to the processor module 21 in the semiconductor device 20 through a first connection 33, and the memory device 30 is connected to the associated circuit module 22 in the semiconductor device 20 through a second connection 34.
The first connection 33 and the second connection 34 include micro bumps and through silicon vias.
The memory device 30 comprises a tri-state content addressable memory.
In some embodiments, memory device 30 includes at least one memory cell 31 stacked on top of each other; wherein the memory cells 31 are interconnected by a fourth connection 32. And each memory unit 31 includes at least one bank for storing data. The memory device 30 does not include peripheral circuits and comparison circuits.
A package substrate 40 positioned below the semiconductor device 20; wherein the package substrate 40 is connected to the processor module 21 in the semiconductor device 20 through a third connection 41.
In some embodiments, the third connectors 41 are micro-bumps.
In some embodiments, the lower portion of the package substrate 40 is provided with a fourth connecting member 42, which may be a solder ball.
The structure is equivalent to 3D packaging, so that the size of the silicon chip occupied by the TCAM is greatly reduced, and the storage capacity is improved.
And the packaging mode reduces the cost of the TCAM, the unit price of the storage space and the energy consumption.
As shown in fig. 8, the controller unit 223 in the semiconductor device 20 is connected with the processor module 21 and the peripheral circuit 222.
The peripheral circuit 222 includes a first portion 222a and a second portion 222 b.
In some embodiments, the first portion 222a includes precharge circuitry (including a look-up line pre-discharger and a match line pre-charger), sense amplifiers (i.e., match line sense amplifiers), bit lines (not shown), and data drivers (including a compare data driver and a bit line data driver).
In some embodiments, the bit line driver further comprises a write/lookup bit line decode and driver.
In some embodiments, the second portion 222b includes an encoder (match line encoding and priority logic encoder) and an address decoder (i.e., decoding circuitry).
In some embodiments, the second portion 222b may also include matching sensing circuitry.
A second portion 222b of the peripheral circuitry 222 is connected with the memory cells 31 of the memory device 30 by Word Lines (WL) and Match Lines (ML).
The controller unit 223 is also connected to the I/O interface unit 70 of the computer device.
Data is input from the controller unit and addresses are output through the encoder.
The controller unit 223 receives user inputs and communicates with the precharge circuitry, the sense amplifiers, the data drivers, and the I/O interface units. The I/O interface unit communicates with the controller unit and the data driver.
The semiconductor device assembly provided by the embodiment of the application comprises a semiconductor device; a memory device located over the semiconductor device; and a package substrate positioned below the semiconductor device. The related circuit modules 22 corresponding to the processor module 21 and the memory device 30 are arranged in the same semiconductor device 20, and the semiconductor device 20 and the memory device 30 are stacked for 3D packaging, so that the silicon chip size occupied by the TCAM is greatly reduced, and the storage capacity is improved.
The embodiment also provides a computing device. Referring to fig. 9, the computing apparatus includes the above-described semiconductor device assembly, a memory unit 40, a program control unit 50, a query unit 60, an I/O interface unit 70, a Read Only Memory (ROM) 80, and a Random Access Memory (RAM) 90.
In some embodiments, a memory unit 40, communicatively coupled to the semiconductor device 20 in the semiconductor device assembly, is used to run program code or to cache data.
In some embodiments, a program control unit 50 is communicatively coupled to the memory unit 40.
In some embodiments, a query unit 60, communicatively coupled to the program control unit 50, is configured to obtain a query request to initiate a search for data stored in the TCAM.
In some embodiments, an I/O interface unit 70, communicatively connected with the semiconductor device 20 and the memory device 30 in the semiconductor device assembly, is used for inputting data and outputting processing results.
In some embodiments, a Read Only Memory (ROM) 80, which is communicatively connected with the semiconductor device 20 and the memory device 30 in the semiconductor device assembly.
In some embodiments, a Random Access Memory (RAM) 90 is connected with the semiconductor device 20 and the memory device communication 30 in the semiconductor device assembly.
The processor module 21 in the semiconductor device assembly can read/write data to/from the memory unit 40, a Read Only Memory (ROM) 80, and a Random Access Memory (RAM) 90.
Embodiments of the present application provide a computing apparatus that includes a semiconductor device assembly, a memory unit 40, a program control unit 50, a query unit 60, an I/O interface unit 70, a Read Only Memory (ROM) 80, and a Random Access Memory (RAM) 90. The related circuit modules 22 corresponding to the processor module 21 and the memory device 30 are arranged in the same semiconductor device 20, and the semiconductor device 20 and the memory device 30 are stacked for 3D packaging, so that the silicon chip size occupied by the TCAM is greatly reduced, and the storage capacity is improved.
Although the embodiments disclosed in the present application are described above, the descriptions are only for the convenience of understanding the present invention, and are not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.
Claims (11)
1. A semiconductor device, which is connected with a memory device stack, is characterized by comprising a processor module and an associated circuit module corresponding to the memory device;
wherein the related circuit module comprises a comparison circuit and a peripheral circuit corresponding to the memory device;
the comparison circuit comprises a search line, a match line and a comparison unit matrix;
the peripheral circuit comprises an address decoder, a comparison data driver, a bit line data driver, a search line pre-discharger, a match line pre-charger, a match line sensing amplifier and an encoder.
2. The semiconductor device of claim 1, wherein the processor module comprises a graphics processor, a central processing unit, or a system on a chip.
3. The semiconductor device of claim 1, wherein the processor module comprises a plurality of processing cores, wherein each processing core comprises a level one instruction cache and a level one data cache.
4. The semiconductor device of claim 1, wherein the associated circuit block further comprises a controller unit communicatively coupled to the peripheral circuit.
5. The semiconductor device according to claim 4, wherein the controller unit includes:
a control register for setting the memory device;
the keyword memory is used for caching the data to be searched;
and the query result storage is used for caching the query results of the plurality of processing processes.
6. A semiconductor device assembly, comprising:
the semiconductor device according to any one of claims 1 to 5;
a memory device located over the semiconductor device; wherein the memory device is connected with the processor module in the semiconductor device through a first connecting piece, and the memory device is connected with the relevant circuit module in the semiconductor device through a second connecting piece;
a package substrate positioned under the semiconductor device; wherein the package substrate is connected to the processor module in the semiconductor device through a third connection member.
7. The semiconductor device assembly of claim 6, in which the memory device comprises a tri-state content addressable memory.
8. The semiconductor device assembly of claim 6, wherein the memory device comprises at least one memory cell stacked on top of each other;
and the memory units are interconnected through a fourth connecting piece.
9. The semiconductor device assembly of claim 8, wherein each of the memory cells comprises at least one bank for storing data.
10. A computing device, comprising:
the semiconductor device assembly of any one of claims 6 to 9;
a memory unit communicatively connected to the semiconductor devices in the semiconductor device assembly for running program codes or buffering data;
the program control unit is in communication connection with the memory unit;
the query unit is in communication connection with the program control unit and is used for acquiring a query request;
an I/O interface unit communicatively connected with the semiconductor device and the memory device in the semiconductor device assembly for inputting data and outputting processing results.
11. The computing device of claim 10, further comprising:
a read-only memory communicatively connected with the semiconductor devices and the memory devices in the semiconductor device assembly;
a random access memory communicatively connected with the semiconductor devices and the memory devices in the semiconductor device assembly.
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| CN105280223A (en) * | 2014-05-27 | 2016-01-27 | 瑞萨电子株式会社 | Semiconductor integrated circuit |
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| CN108986858A (en) * | 2017-05-30 | 2018-12-11 | 瑞萨电子株式会社 | Content addressable memory |
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| US20150332767A1 (en) * | 2014-05-16 | 2015-11-19 | International Business Machines Corporation | High density search engine |
| CN105280223A (en) * | 2014-05-27 | 2016-01-27 | 瑞萨电子株式会社 | Semiconductor integrated circuit |
| CN108962315A (en) * | 2017-05-24 | 2018-12-07 | 瑞萨电子株式会社 | Content addressable memory |
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Application publication date: 20210629 |