CN113053291B - GIP circuit and driving method thereof - Google Patents
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- CN113053291B CN113053291B CN202110306680.XA CN202110306680A CN113053291B CN 113053291 B CN113053291 B CN 113053291B CN 202110306680 A CN202110306680 A CN 202110306680A CN 113053291 B CN113053291 B CN 113053291B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a GIP circuit and a driving method thereof, wherein a T1 control end is connected with G (n-4); the input end of the T2 is connected with Qb, the output end of the T2 is connected with Q, the control end of the T2 is connected with G (n-4), the output end of the T3 is connected with Qb, and the control end of the T3 is connected with G (n+4); the input end of the T4 is connected with Qb, the output end of the T4 is connected with Q, and the control end of the T4 is connected with G (n+4); the input end of the T5 is connected with the Q, the output end of the T5 is connected with the Qb, and the control end of the T5 is connected with the P; the input end of the T6 is connected with Qb, the control end of the T6 is connected with P, the output end of the T7 is connected with P, the output end of the T8 is connected with Qb, and the control end of the T8 is connected with Q; the output end of the T9 is connected with G (n), and the control end of the T9 is connected with Q; the input end of the T10 is connected with P, and the control end of the T10 is connected with Q; the input end of the T11 is connected with G (n), and the control end of the T11 is connected with P; one polar plate of C1 is connected with Q, and another polar plate of C1 is connected with G (n). The technical scheme solves the problem of abnormal picture display caused by abnormal output waveforms.
Description
Technical Field
The invention relates to the technical field of display, in particular to a GIP circuit and a driving method thereof.
Background
For the display panel, the display quality of the picture is critical, and the display quality is closely related to the output waveform of the GIP circuit. When there is an abnormality in the output waveform of the GIP circuit, it tends to cause a display problem of the panel.
In order to reduce the manufacturing cost of the display Panel and thereby achieve the purpose of a narrow bezel, GIP (Gate in Panel) technology is generally adopted in the manufacturing process, and a Gate circuit (i.e., GIP circuit) is directly integrated on the flat Panel display Panel. The output waveform of the GIP circuit is susceptible to leakage of the transistor, resulting in a distortion of the output waveform of the GIP circuit. The distorted output waveform causes problems in turning on and off transistors in a display area of the display panel, thereby causing abnormal display of the display panel.
Disclosure of Invention
Therefore, it is desirable to provide a GIP circuit and a driving method thereof, which solve the problem that the output waveform of the gate circuit is susceptible to the leakage of the transistor.
To achieve the above object, the present application provides a GIP circuit, including: transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8, transistor T9, transistor T10, transistor T11, and capacitor C1;
the input end of the transistor T1 is connected with a voltage signal FW, the output end of the transistor T1 is connected with a Qb node, and the control end of the transistor T1 is connected with a grid G (n-4);
the input end of the transistor T2 is connected with the Qb node, the output end of the transistor T2 is connected with the Q node, and the control end of the transistor T2 is connected with the grid G (n-4);
an input end of the transistor T3 is connected with a voltage signal BW, an output end of the transistor T3 is connected with a Qb node, and a control end of the transistor T3 is connected with a grid G (n+4);
an input end of the transistor T4 is connected with a Qb node, an output end of the transistor T4 is connected with a Q node, and a control end of the transistor T4 is connected with a grid G (n+4);
the input end of the transistor T5 is connected with a Q node, the output end of the transistor T5 is connected with a Qb node, and the control end of the transistor T5 is connected with a P node;
the input end of the transistor T6 is connected with a Qb node, the output end of the transistor T6 is connected with a voltage signal VGL, and the control end of the transistor T6 is connected with a P node;
the input end of the transistor T7 is connected with a voltage signal VGH, the output end of the transistor T7 is connected with a P node, and the control end of the transistor T7 is connected with a clock signal CKn;
the input end of the transistor T8 is connected with a voltage signal VGH, the output end of the transistor T8 is connected with a Qb node, and the control end of the transistor T8 is connected with a Q node;
an input end of the transistor T9 is connected with a clock signal CKn, an output end of the transistor T9 is connected with a grid G (n), and a control end of the transistor T9 is connected with a Q node;
the input end of the transistor T10 is connected with a P node, the output end of the transistor T10 is connected with a voltage signal VGL, and the control end of the transistor T10 is connected with a Q node;
the input end of the transistor T11 is connected with a grid G (n), the output end of the transistor T11 is connected with a voltage signal VGL, and the control end of the transistor T11 is connected with a P node;
one polar plate of the capacitor C1 is connected with the Q node, and the other polar plate of the capacitor C1 is connected with the grid G (n).
Further, the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11 and the capacitor C1 are all disposed on the display panel.
Further, the display panel is an LCD display panel.
Further, the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10 and T11 are thin film transistors.
Further, the GIP circuit array is disposed on the display panel, and a G (n) end of each GIP circuit is connected to one pixel.
The application also provides a GIP circuit driving method, at the time t1, the grid G (n-4) inputs high potential, the clock signal CKn inputs low potential, the grid G (n) inputs low potential, and the grid G (n+4) inputs low potential;
at time t2, the gate G (n-4) inputs a low potential, the clock signal CKn inputs a low potential, the gate G (n) inputs a low potential, and the gate G (n+4) inputs a low potential;
at time t3, the gate G (n-4) inputs a low potential, the clock signal CKn inputs a high potential, the gate G (n) inputs a high potential, and the gate G (n+4) inputs a low potential;
at time t4, the gate G (n-4) inputs a low potential, the clock signal CKn inputs a low potential, the gate G (n) inputs a low potential, and the gate G (n+4) inputs a low potential;
at time t5, the gate G (n-4) inputs a low potential, the clock signal CKn inputs a low potential, the gate G (n) inputs a low potential, the front half of the gate G (n+4) inputs a high potential, and the rear half of the gate G (n+4) inputs a low potential;
at time t6, the gate G (n-4) inputs a low potential, the clock signal CKn inputs a high potential, the gate G (n) inputs a low potential, and the gate G (n+4) inputs a low potential.
Further, in the time t1 to the time t6, the voltage signal FW and the voltage signal VGH are continuously written with high potential; the voltage signal VGL and the voltage signal BW continue to write low potentials.
Compared with the prior art, the GIP circuit of each stage has 11 capacitors and 1 capacitor, and the Qb node is added in the GIP circuit, so that the voltage of the Q point cannot be reduced due to the electric leakage influence of the transistor, the output waveform of the GIP circuit can be stable, and the problem of abnormal picture display caused by abnormal output waveform is solved.
Drawings
FIG. 1 is a circuit diagram of the GIP circuit;
FIG. 2 is a timing waveform diagram of the GIP circuit.
Detailed Description
In order to describe the technical content, constructional features, achieved objects and effects of the technical solution in detail, the following description is made in connection with the specific embodiments in conjunction with the accompanying drawings.
Referring to fig. 1 to 2, the present application discloses a GIP circuit and a driving method thereof, including: transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8, transistor T9, transistor T10, transistor T11, and capacitor C1; the input end of the transistor T1 is connected with a voltage signal FW, the output end of the transistor T1 is connected with a Qb node, and the control end of the transistor T1 is connected with a grid G (n-4); the input end of the transistor T2 is connected with the Qb node, the output end of the transistor T2 is connected with the Q node, and the control end of the transistor T2 is connected with the grid G (n-4); an input end of the transistor T3 is connected with a voltage signal BW, an output end of the transistor T3 is connected with a Qb node, and a control end of the transistor T3 is connected with a grid G (n+4); an input end of the transistor T4 is connected with a Qb node, an output end of the transistor T4 is connected with a Q node, and a control end of the transistor T4 is connected with a grid G (n+4); the input end of the transistor T5 is connected with a Q node, the output end of the transistor T5 is connected with a Qb node, and the control end of the transistor T5 is connected with a P node; the input end of the transistor T6 is connected with a Qb node, the output end of the transistor T6 is connected with a voltage signal VGL, and the control end of the transistor T6 is connected with a P node; the input end of the transistor T7 is connected with a voltage signal VGH, the output end of the transistor T7 is connected with a P node, and the control end of the transistor T7 is connected with a clock signal CKn; the input end of the transistor T8 is connected with a voltage signal VGH, the output end of the transistor T8 is connected with a Qb node, and the control end of the transistor T8 is connected with a Q node; an input end of the transistor T9 is connected with a clock signal CKn, an output end of the transistor T9 is connected with a grid G (n), and a control end of the transistor T9 is connected with a Q node; the input end of the transistor T10 is connected with a P node, the output end of the transistor T10 is connected with a voltage signal VGL, and the control end of the transistor T10 is connected with a Q node; the input end of the transistor T11 is connected with a grid G (n), the output end of the transistor T11 is connected with a voltage signal VGL, and the control end of the transistor T11 is connected with a P node; one polar plate of the capacitor C1 is connected with the Q node, and the other polar plate of the capacitor C1 is connected with the grid G (n). The GIP circuit arrays are arranged on the display panel, and the G (n) end of each GIP circuit is connected with one pixel point.
It should be noted that, in the present application, each stage GIP circuit has 11 capacitors, 1 capacitor, and the voltage signals FW and VGH are dc high voltages, and the voltage signals BW and VGL are dc low voltages. The high voltage of the clock signal CKn is VGH, and the low voltage is VGL. According to the method and the device, the Qb node is added in the GIP circuit, so that the voltage of the Q point cannot be reduced due to the electric leakage influence of the transistor, the output waveform of the GIP circuit can be stable, and the problem of abnormal picture display caused by abnormal output waveform is solved.
It should be noted that, G (n-4) inputs Vg (n-4) gate voltage signals, G (n+4) inputs Vg (n+4) gate voltage signals, G (n) outputs Vg (n) gate voltage signals, and G (n) is connected to one pixel point; in this application, n in G (n) represents an nth subpixel of a certain row; (n-4) and (n+4) in G (n-4) and G (n+4) are used to represent the start-up period of the pixels in a certain row, i.e., how many pixels are turned on in sequence in each period.
In some embodiments, the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, and C1 are all disposed on the display panel. The display panel is an LCD display panel.
In certain embodiments, the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, and T11 are thin film transistors.
In some embodiments, a method of driving a GIP circuit is also included.
At time t1, the gate G (n-4) inputs a high potential, the clock signal CKn inputs a low potential, the gate G (n) inputs a low potential, and the gate G (n+4) inputs a low potential. At time t2, the gate G (n-4) is input with a low potential, the clock signal CKn is input with a low potential, the gate G (n) is input with a low potential, and the gate G (n+4) is input with a low potential. At time t3, the gate G (n-4) is input with a low potential, the clock signal CKn is input with a high potential, the gate G (n) is input with a high potential, and the gate G (n+4) is input with a low potential. At time t4, the gate G (n-4) inputs a low potential, the clock signal CKn inputs a low potential, the gate G (n) inputs a low potential, and the gate G (n+4) inputs a low potential. At time t5, the gate G (n-4) is inputted with a low potential, the clock signal CKn is inputted with a low potential, the gate G (n) is inputted with a low potential, the first half of the gate G (n+4) is inputted with a high potential, and the second half of the gate G (n+4) is inputted with a low potential. At time t6, the gate G (n-4) inputs a low potential, the clock signal CKn inputs a high potential, the gate G (n) inputs a low potential, and the gate G (n+4) inputs a low potential. In the time T1 to the time T6, the voltage signal FW and the voltage signal VGH are continuously written with high potential; the voltage signal VGL and the voltage signal BW continue to write low potentials.
Specifically, at time t1, the gate G (n-4) changes from a low level to a high level. At this time, the transistors T1 and T2 are both turned on, and the Qb point and the Q point are both charged to the VGH potential, and since the Q point potential is at the high level, the transistors T8, T9, and T10 are all turned on, and the transistor T8 is turned on, so that the Qb point receives the high potential of the voltage signal VGH through the path of the transistor T8; the transistor T9 is turned on so that the gate G (n) receives a low potential of the clock signal Ckn through the path of the transistor T9; the transistor T10 is turned on and the potential at point P is pulled down to the low potential of the voltage signal VGL through the path of the transistor T10.
At time T2, the gate G (n-4) is turned from high to low, and at this time, the transistor T1 and the transistor T2 are both turned off, and at this time, the Q point is in an unfixed state, and the Qb point is the high voltage of the voltage signal VGH because the transistor T8 is turned on (the Q point is high). Transistors on the leakage path, such as 6 voltage signals T1-T6, which may cause a drop in Q-point potential, are analyzed, and we assume that the threshold voltages of these voltage signals are all less than 0. And analyzing the voltage signals directly connected with the Q point, such as the voltage signal T2/the voltage signal T4/the voltage signal T5, wherein the gate-source voltage VGS of the three voltage signals is equal to the voltage signal VGL-Qb (the voltage of the Qb point is high at the moment), so that the VGS of the three voltage signals is far less than 0, the voltage of the Q point cannot be reduced due to the influence of leakage current of the voltage signals, and the high voltage of the Q point can be well maintained.
At time T3, the clock signal Ckn changes from low to high, and the Q point is raised due to the capacitive coupling of the capacitor C1, so that the transistor T9 is turned on more thoroughly, and the gate G (n) is output as the high of the clock signal Ckn.
At time T4, the clock signal Ckn changes from high to low, and at this time, the Q point is reduced to the original high due to the capacitive coupling of the capacitor C1, and the transistor T9 is still kept in the on state, so that the gate G (n) outputs a low level of the clock signal Ckn.
At time T5, the gate G (n+4) is turned from low to high, and at this time, the transistors T3 and T4 are turned on, and the potential at the Q point is discharged to low level through this path.
At time T6, the clock signal Ckn is changed from low level to high level, and at this time, the transistor T7 is turned on, the voltage signal VGH is received at the point P, and the potential at the point P is high, so that the three transistors T5, T6, and T11 are turned on, and the potentials at the point Q and the point G (n) are pulled down to low potential, respectively.
It should be noted that, although the foregoing embodiments have been described herein, the scope of the present invention is not limited thereby. Therefore, based on the innovative concepts of the present invention, alterations and modifications to the embodiments described herein, or equivalent structures or equivalent flow transformations made by the present description and drawings, apply the above technical solutions directly or indirectly to other relevant technical fields, all of which are included in the scope of protection of the present patent.
Claims (3)
1. A GIP circuit, comprising: transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, transistor T7, transistor T8, transistor T9, transistor T10, transistor T11, and capacitor C1;
the input end of the transistor T1 is connected with a voltage signal FW, the output end of the transistor T1 is connected with a Qb node, and the control end of the transistor T1 is connected with a grid G (n-4); wherein, the voltage signal FW is continuously written into the high potential;
the input end of the transistor T2 is connected with the Qb node, the output end of the transistor T2 is connected with the Q node, and the control end of the transistor T2 is connected with the grid G (n-4);
an input end of the transistor T3 is connected with a voltage signal BW, an output end of the transistor T3 is connected with a Qb node, and a control end of the transistor T3 is connected with a grid G (n+4); wherein, the voltage signal BW is continuously written into the low potential;
an input end of the transistor T4 is connected with a Qb node, an output end of the transistor T4 is connected with a Q node, and a control end of the transistor T4 is connected with a grid G (n+4);
the input end of the transistor T5 is connected with a Q node, the output end of the transistor T5 is connected with a Qb node, and the control end of the transistor T5 is connected with a P node;
the input end of the transistor T6 is connected with a Qb node, the output end of the transistor T6 is connected with a voltage signal VGL, and the control end of the transistor T6 is connected with a P node;
the input end of the transistor T7 is connected with a voltage signal VGH, the output end of the transistor T7 is connected with a P node, and the control end of the transistor T7 is connected with a clock signal CKn;
the input end of the transistor T8 is connected with a voltage signal VGH, the output end of the transistor T8 is connected with a Qb node, and the control end of the transistor T8 is connected with a Q node;
an input end of the transistor T9 is connected with a clock signal CKn, an output end of the transistor T9 is connected with a grid G (n), and a control end of the transistor T9 is connected with a Q node;
the input end of the transistor T10 is connected with a P node, the output end of the transistor T10 is connected with a voltage signal VGL, and the control end of the transistor T10 is connected with a Q node;
the input end of the transistor T11 is connected with a grid G (n), the output end of the transistor T11 is connected with a voltage signal VGL, and the control end of the transistor T11 is connected with a P node;
one polar plate of the capacitor C1 is connected with the Q node, and the other polar plate of the capacitor C1 is connected with the grid G (n);
the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11 and the capacitor C1 are all disposed on the display panel;
g (n-4) inputs the gate voltage signal of Vg (n-4), G (n+4) inputs the gate voltage signal of Vg (n+4), G (n) outputs the gate voltage signal of Vg (n), and G (n) is connected with a pixel point;
the display panel is an LCD display panel;
the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10 and T11 are thin film transistors.
2. The GIP circuit of claim 1, wherein the array of GIP circuits is disposed on a display panel, and a G (n) terminal of each of the GIP circuits is connected to one pixel.
3. A GIP circuit driving method, characterized in that the GIP circuit driving method is applied to the GIP circuit of any one of claims 1 to 2;
at time t1, the gate G (n-4) inputs a high potential, the clock signal CKn inputs a low potential, the gate G (n) inputs a low potential, and the gate G (n+4) inputs a low potential;
at time t2, the gate G (n-4) inputs a low potential, the clock signal CKn inputs a low potential, the gate G (n) inputs a low potential, and the gate G (n+4) inputs a low potential;
at time t3, the gate G (n-4) inputs a low potential, the clock signal CKn inputs a high potential, the gate G (n) inputs a high potential, and the gate G (n+4) inputs a low potential;
at time t4, the gate G (n-4) inputs a low potential, the clock signal CKn inputs a low potential, the gate G (n) inputs a low potential, and the gate G (n+4) inputs a low potential;
at time t5, the gate G (n-4) inputs a low potential, the clock signal CKn inputs a low potential, the gate G (n) inputs a low potential, the front half of the gate G (n+4) inputs a high potential, and the rear half of the gate G (n+4) inputs a low potential;
at time t6, the gate G (n-4) inputs a low potential, the clock signal CKn inputs a high potential, the gate G (n) inputs a low potential, and the gate G (n+4) inputs a low potential;
wherein, in the time t1 to the time t6, the voltage signal FW and the voltage signal VGH continuously write high potential; the voltage signal VGL and the voltage signal BW continue to write low potentials.
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| CN112527150A (en) * | 2020-12-14 | 2021-03-19 | 福建华佳彩有限公司 | GIP circuit and driving method thereof |
| CN112527149A (en) * | 2020-12-14 | 2021-03-19 | 福建华佳彩有限公司 | GIP circuit for improving display stability and driving method |
| CN214541521U (en) * | 2021-03-23 | 2021-10-29 | 福建华佳彩有限公司 | GIP circuit |
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- 2021-03-23 CN CN202110306680.XA patent/CN113053291B/en active Active
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| WO2018107534A1 (en) * | 2016-12-15 | 2018-06-21 | 武汉华星光电技术有限公司 | Gate drive circuit and driving method therefor, and display device |
| CN111583850A (en) * | 2020-05-22 | 2020-08-25 | 昆山国显光电有限公司 | Shift register, light-emitting control circuit and display panel |
| CN112509512A (en) * | 2020-12-14 | 2021-03-16 | 福建华佳彩有限公司 | GIP circuit and driving method |
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