CN113051856B - Optimization method for integrated circuit design data - Google Patents
Optimization method for integrated circuit design data Download PDFInfo
- Publication number
- CN113051856B CN113051856B CN202110313460.XA CN202110313460A CN113051856B CN 113051856 B CN113051856 B CN 113051856B CN 202110313460 A CN202110313460 A CN 202110313460A CN 113051856 B CN113051856 B CN 113051856B
- Authority
- CN
- China
- Prior art keywords
- design
- integrated circuit
- design parameters
- local
- global
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000013461 design Methods 0.000 title claims abstract description 192
- 238000005457 optimization Methods 0.000 title claims abstract description 60
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000003062 neural network model Methods 0.000 claims abstract description 16
- 238000013507 mapping Methods 0.000 claims abstract description 13
- 239000002245 particle Substances 0.000 claims description 21
- 239000011159 matrix material Substances 0.000 claims description 4
- 230000004913 activation Effects 0.000 claims description 2
- 238000012827 research and development Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012549 training Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/004—Artificial life, i.e. computing arrangements simulating life
- G06N3/006—Artificial life, i.e. computing arrangements simulating life based on simulated virtual individual or collective life forms, e.g. social simulations or particle swarm optimisation [PSO]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/08—Learning methods
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Evolutionary Computation (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Health & Medical Sciences (AREA)
- Artificial Intelligence (AREA)
- Data Mining & Analysis (AREA)
- Biophysics (AREA)
- Biomedical Technology (AREA)
- Molecular Biology (AREA)
- Computing Systems (AREA)
- Computational Linguistics (AREA)
- Life Sciences & Earth Sciences (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Health & Medical Sciences (AREA)
- Computer Hardware Design (AREA)
- Geometry (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses an optimization method of integrated circuit design data, which comprises the following steps: acquiring design data of the integrated circuit, and acquiring design parameters through the design data, wherein the design parameters comprise global design parameters and local design parameters; acquiring performance indexes through the design data, and describing the mapping relation between the design data and the performance indexes through a neural network model; specifying an optimization criterion for the design data according to the performance index; acquiring basic data required by the optimization criterion according to the mapping relation; and iteratively optimizing the design data of the integrated circuit by using a multi-level population optimization algorithm. The optimization method of the integrated circuit design data can solve the problems of complex design, long period and high research and development cost of the existing integrated circuit.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to an optimization method of integrated circuit design data.
Background
Integrated circuits, also known as microcircuits, microchips, wafers/chips. The design method for the integrated circuit reduces the design efficiency of the integrated circuit, improves the research and development cost and prolongs the development period of the integrated circuit chip.
Disclosure of Invention
The invention aims to provide an optimization method of integrated circuit design data, which aims to solve the problems of complex design, long period and high research and development cost of the existing integrated circuit.
The technical scheme for solving the technical problems is as follows:
the invention provides an optimization method of integrated circuit design data, which comprises the following steps:
s1: acquiring design data of the integrated circuit, and acquiring design parameters through the design data, wherein the design parameters comprise global design parameters and local design parameters;
s2: acquiring performance indexes through the design data, and describing the mapping relation between the design data and the performance indexes through a neural network model;
s3: obtaining an optimization criterion of the design data according to the mapping relation;
s4: acquiring basic data required by the optimization criterion according to the mapping relation;
s5: substituting the basic data, and iteratively optimizing the integrated circuit design data by using a multi-level population optimization algorithm.
Optionally, in the step 1: the design data includes a plurality of integrated circuit design case data including the design parameters.
Optionally, in the step 2: the global design parameters refer to input current and the local design parameters include NMOS input transistor size, PMOS load size, and tail current source size.
Optionally, in the step 2: the design data includes a plurality of integrated circuit design case data including the performance metrics.
Optionally, in the step 2, the performance index includes a gain, a gain bandwidth, and an output common mode.
Optionally, in the step 3: the expression of the optimization criterion J is as follows:
J＝α(G 1 -G des ) 2 +β(GBW-GBW des ) 2 +γ(V-V des ) 2
G 1 GBW and V represent gain, gain bandwidth product and output common mode, respectively; g des 、GBW des And V des Representing the desired gain, gain bandwidth product and output common mode, respectively; alpha, beta and gamma respectively represent the gain, the gain bandwidth product and the optimized weight coefficient of the output common mode.
Optionally, the step 5 includes the following substeps:
s501: entering global optimization, and initializing the design parameters to obtain an initialization result of the global design parameters;
s502: according to the initialization result of the global design parameters, a first global design parameter and a first local design parameter are obtained, the first local design parameter is fixed, and the first global design parameter is optimized until a first global optimal design parameter is obtained;
s503: entering local optimization, initializing the first local design parameters to obtain second global design parameters and second local design parameters, fixing the second global design parameters, and optimizing the second local design parameters until second local optimal design parameters are obtained;
s504: adjusting the weight in the local optimization process, returning to the step S403, and repeatedly optimizing the local design parameters until the optimal local design parameters are obtained;
s505: and (2) adjusting the weight in the global optimization process according to the optimal local design parameters, and repeating the steps S502-S504 until the optimal global design parameters are obtained.
Optionally, the first local design parameter, the second local design parameter, the first global design parameter and the second global design parameter obtained according to the initialization result of the global design parameter and the initialization result of the local design parameter each include a speed parameter and a position parameter, a particle is generated according to the speed parameter and the position parameter, the position of the particle represents the searched optimal solution, and a speed V update formula of the particle is:
V i,n+1 ＝wV i,n +c 1 r 1 (P i,n -X i,n )+c 2 r 2 (G-X i,n )
the position X of the particle updates the formula as follows:
X i,n+1 ＝X i,n +V i,n+1
wherein w is an inertial weight; p (P) i,n Is the optimal position of the ith particle; g is the optimal position of the whole population; c 1 And c 2 Is a constant; r is (r) 1 And r 2 Is [0,1 ]]Random numbers in (a) and (b). The method comprises the steps of carrying out a first treatment on the surface of the V (V) i,n A speed of an ith particle representing an nth generation population; x is X i,n Representing the position of the ith particle of the nth generation population.
Optionally, the weights in the local optimization process and the weights in the global optimization process each include: updating the weight by using a weight linear decrementing strategy, wherein the weight updating formula is as follows:
wherein w is max And w min Representing the maximum and minimum values of the inertial weights; n (N) max The maximum iteration number, i represents the current iteration number, and w is the inertia weight.
The invention has the following beneficial effects:
according to the technical scheme, namely the optimization method of the integrated circuit design data provided by the embodiment of the invention, on one hand, the neural network model established according to the integrated circuit design data is combined with a multi-level population optimization algorithm, so that the integrated circuit design data has good global searching capability and local searching capability, and therefore, the design parameters reaching target performance indexes can be rapidly optimized, and the design period of a circuit can be shortened when the integrated circuit design data is applied to the integrated circuit design; on the other hand, the optimization method has less calculated amount, and does not need to rely on experience of research personnel to repeatedly test and adjust, thereby indirectly reducing research and development cost of the integrated circuit.
Drawings
FIG. 1 is a flow chart of a method for optimizing design data of an integrated circuit according to an embodiment of the present invention;
FIG. 2 is a diagram of a PMOS input differential integrated circuit loaded by an NMOS current source according to an optimization method of integrated circuit design data provided by an embodiment of the present invention;
FIG. 3 is a circuit diagram of integrated circuit design parameters obtained by a multi-level population optimization method according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of the result of a Cadence software simulation experiment according to an optimized integrated circuit design parameter of the method for optimizing integrated circuit design data according to an embodiment of the present invention;
fig. 5 is a flowchart illustrating the sub-steps of S5 in the optimization method of integrated circuit design data according to an embodiment of the present invention.
Detailed Description
The principles and features of the present invention are described below with reference to the drawings, the examples are illustrated for the purpose of illustrating the invention and are not to be construed as limiting the scope of the invention.
Examples
The invention relates to a multi-level population optimization method of integrated circuit design parameters, and a flow chart of the multi-level population optimization method is shown in figure 1. The implementation details of the multi-level population optimization method of the design parameters of the integrated circuit according to the present invention will be described in detail below by taking a PMOS input differential integrated circuit (fig. 2) with an NMOS current source as a load, where the optimization method of the design data of the integrated circuit includes:
s1: acquiring design data of the integrated circuit, and acquiring design parameters through the design data, wherein the design parameters comprise global design parameters and local design parameters;
in this embodiment, design data of the PMOS input differential integrated circuit loaded by the NMOS current source is obtained by Cadence software in combination with the orthogonal design method. Its design parameters are divided into global and local design parameters, the global design parameters referring to the input current, and the local design parameters including NMOS input transistor size, PMOS load size, and tail current source size.
S2: acquiring performance indexes through the design data, and describing the mapping relation between the design data and the performance indexes through a neural network model;
in this embodiment, a neural network model of a mapping relationship between design parameters and performance indexes of a PMOS input differential integrated circuit loaded by an NMOS current source is built by training using a back propagation algorithm, and the neural network model includes an input layer, an hidden layer and an output layer, wherein the input layer is the design parameters, and the output layer is the performance indexes.
In addition, the expression of the neural network model of the mapping relation between the design parameters of the integrated circuit and the performance indexes is as follows:
P＝g[W 2 ·g(W 1 ·U+b 1 )+b 2 ]
wherein g (·) represents the activation function of the neural network model, e -x Represents an exponential function based on a natural constant e, P and U represent an integrated circuit performance index and a design parameter, W, respectively 1 And b 1 Weight matrix and bias term respectively representing input layer to hidden layer in neural network model, W 2 And b 2 And the weight matrix and the bias term from the hidden layer to the output layer in the neural network model are represented.
S3: obtaining an optimization criterion of the design data according to the mapping relation;
in this embodiment, the optimization criterion J of the integrated circuit design parameter is expressed as follows:
J＝α(G 1 -G des ) 2 +β(GBW-GBW des ) 2 +γ(V-V des ) 2
G 1 GBW and V represent gain, gain bandwidth product and output common mode, respectively; g des 、GBW des And V des Representing the desired gain, gain bandwidth product and output common mode, respectively; alpha, beta and gamma respectively represent the gain, the gain bandwidth product and the optimized weight coefficient of the output common mode.
S4: acquiring basic data required by the optimization criterion according to the mapping relation;
s5: and iteratively optimizing the design data of the integrated circuit by utilizing a multi-level population optimization algorithm according to the basic data.
The invention has the following beneficial effects:
according to the technical scheme, namely the optimization method of the integrated circuit design data provided by the embodiment of the invention, on one hand, the neural network model established according to the integrated circuit design data is combined with a multi-level population optimization algorithm, so that the integrated circuit design data has good global searching capability and local searching capability, and therefore, the design parameters reaching target performance indexes can be rapidly optimized, and the design period of a circuit can be shortened when the integrated circuit design data is applied to the integrated circuit design; on the other hand, the optimization method has less calculated amount, and does not need to rely on experience of research personnel to repeatedly test and adjust, thereby indirectly reducing research and development cost of the integrated circuit.
Optionally, in the step 1: the design data includes a plurality of integrated circuit design case data including the design parameters.
Optionally, in the step 2: the global design parameters refer to input current and the local design parameters include NMOS input transistor size, PMOS load size, and tail current source size.
Optionally, in the step 2: the design data includes a plurality of integrated circuit design case data including the performance metrics.
Optionally, in the step 2, the performance index includes a gain, a gain bandwidth, and an output common mode.
Optionally, in the step 3: the expression of the optimization criterion J is as follows:
J＝α(G 1 -G des ) 2 +β(GBW-GBW des ) 2 +γ(V-V des ) 2
G 1 GBW and V represent gain, gain bandwidth product and output common mode, respectively; g des 、GBW des And V des Representing the desired gain, gain bandwidth product and output common mode, respectively; alpha, beta and gamma respectively represent the gain, the gain bandwidth product and the optimized weight coefficient of the output common mode. It will be appreciated that when it is desired thatThe sum of the negative value of the value and the set value tends to zero, and the set value is the optimized value.
Optionally, the step 5 includes the following substeps, referring to fig. 5:
s501: entering global optimization, and initializing the design parameters to obtain an initialization result of the global design parameters;
s502: according to the initialization result of the global design parameters, a first global design parameter and a first local design parameter are obtained, the first local design parameter is fixed, and the first global design parameter is optimized until a first global optimal design parameter is obtained;
s503: entering local optimization, initializing the first local design parameters to obtain second global design parameters and second local design parameters, fixing the second global design parameters, and optimizing the second local design parameters until second local optimal design parameters are obtained;
s504: adjusting the weight in the local optimization process, returning to the step S403, and repeatedly optimizing the local design parameters until the optimal local design parameters are obtained;
s505: and (2) adjusting the weight in the global optimization process according to the optimal local design parameters, and repeating the steps S502-S504 until the optimal global design parameters are obtained.
Based on the above, a person skilled in the art may design an integrated circuit based on the optimal local design parameter value and the optimal global design parameter value.
Optionally, all design parameters obtained according to the initialization result of the global design parameters and the initialization result of the local design parameters include a speed parameter and a position parameter, and particles are generated according to the speed parameter and the position parameter, the position of the particles represents the searched optimal solution, and a speed V update formula of the particles is as follows:
V i,n+1 ＝wV i,n +c 1 r 1 (P i,n -X i,n )+c 2 r 2 (G-X i,n )
the position X of the particle updates the formula as follows:
X i,n+1 ＝X i,n +V i,n+1
wherein w is an inertial weight; p (P) i,n Is the optimal position of the ith particle; g is the optimal position of the whole population; c 1 And c 2 Constant, usually 2; r is (r) 1 And r 2 Is [0,1 ]]Random numbers in (a) and (b). The method comprises the steps of carrying out a first treatment on the surface of the V (V) i,n A speed of an ith particle representing an nth generation population; x is X i,n Representing the position of the ith particle of the nth generation population.
Optionally, the weights in the local optimization process and the weights in the global optimization process each include: updating the weight by using a weight linear decrementing strategy, wherein the weight updating formula is as follows:
wherein w is max And w min The maximum and minimum values representing the inertia weight are usually 0.9 and 0.4 respectively; n (N) max The maximum iteration number, i represents the current iteration number, and w is the inertia weight.
In this embodiment, optimization criteria for integrated circuit design parameters and parameters for a multi-level population optimization algorithm are initialized as shown in table 1.
Table 1 initialization parameters
According to the expected performance index, the design parameters of the PMOS input differential integrated circuit loaded by the NMOS current source are optimized by using the multi-level population optimization method of the design parameters of the integrated circuit. The optimized input current, NMOS input transistor size, PMOS load size, and tail current source size were 165.8 μA, 32.1 μm/0.18 μm, 8.3 μm/0.18 μm, and 29.2 μm/0.18 μm, respectively, as shown in FIG. 3. According to the design parameters of the PMOS input differential integrated circuit taking the optimized NMOS current source as the load, the result of the Cadence software simulation experiment is shown in fig. 4, the gain bandwidth and the output common mode level of the PMOS input differential integrated circuit taking the NMOS current source as the load are respectively 22.79dB, 343.76MHz and 0.901V, and almost reach the expected performance indexes.
From the above results, it can be found that the method provided by the invention can efficiently optimize the design parameters of the integrated circuit, shorten the research and development period of the integrated circuit, and provide a reliable way for realizing the efficient design of the integrated circuit.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (7)
1. A method for optimizing integrated circuit design data, the method comprising:
s1: acquiring design data of the integrated circuit, and acquiring design parameters through the design data, wherein the design parameters comprise global design parameters and local design parameters;
s2: acquiring performance indexes through the design data, and describing the mapping relation between the design parameters and the performance indexes through a neural network model;
s3: obtaining an optimization criterion of the design data according to the performance index;
s4: acquiring basic data required by the optimization criterion according to the mapping relation;
s5: according to the basic data, iterative optimization of integrated circuit design data is performed by using a multi-level population optimization algorithm;
the expression of the neural network model of the mapping relation between the design parameters and the performance indexes is as follows:
P＝g[W 2 ·g(W 1 ·U+b 1 )+b 2 ]
wherein g (·) represents the activation function of the neural network model, e -x Represents an exponential function based on a natural constant e, P and U represent an integrated circuit performance index and a design parameter, W, respectively 1 And b 1 Weight matrix and bias term respectively representing input layer to hidden layer in neural network model, W 2 And b 2 A weight matrix and a bias term from an implicit layer to an output layer in the neural network model are represented;
in the step S3:
the expression of the optimization criterion J is as follows:
J＝α(G 1 -G des ) 2 +β(GBW-GBW des ) 2 +γ(V-V des ) 2
G 1 GBW and V represent gain, gain bandwidth product and output common mode, respectively; g des 、GBW des And V des Representing the desired gain, gain bandwidth product and output common mode, respectively; alpha, beta and gamma respectively represent the gain, the gain bandwidth and the output common mode optimization weight coefficient;
the step S5 includes the following sub-steps:
s501: entering global optimization, and initializing the design parameters to obtain an initialization result of the global design parameters;
s502: according to the initialization result of the global design parameters, a first global design parameter and a first local design parameter are obtained, the first local design parameter is fixed, and the first global design parameter is optimized until a first global optimal design parameter is obtained;
s503: entering local optimization, initializing the first local design parameters to obtain second global design parameters and second local design parameters, fixing the second global design parameters, and optimizing the second local design parameters until second local optimal design parameters are obtained;
s504: adjusting the weight in the local optimization process, returning to the step S403, and repeatedly optimizing the local design parameters until the optimal local design parameters are obtained;
s505: and (2) adjusting the weight in the global optimization process according to the optimal local design parameters, and repeating the steps S502-S504 until the optimal global design parameters are obtained.
2. The method for optimizing integrated circuit design data according to claim 1, wherein in the step S1:
the design data includes a plurality of integrated circuit design case data including the design parameters.
3. The method for optimizing integrated circuit design data according to claim 1, wherein in the step S2:
the global design parameters are input currents, and the local design parameters include NMOS input transistor size, PMOS load size, and tail current source size.
4. The method for optimizing integrated circuit design data according to claim 1, wherein in the step S2:
the design data includes a plurality of integrated circuit design case data including the performance metrics.
5. The method according to claim 1 or 4, wherein in the step S2, the performance index includes gain, gain bandwidth, and output common mode.
6. The method according to claim 1, wherein the first local design parameter, the second local design parameter, the first global design parameter, and the second global design parameter obtained from the initialization result of the global design parameter and the initialization result of the local design parameter each include a speed parameter and a position parameter, particles are generated from the speed parameter and the position parameter,
the position of the particle represents the optimal solution for searching, and the velocity V of the particle is updated according to the formula:
V i,n+1 ＝wV i,n +c 1 r 1 (P i,n -X i,n )+c 2 r 2 (G-X i,n )
the position X of the particle updates the formula as follows:
X i,n+1 ＝X i,n +V i,n+1
wherein w is an inertial weight; p (P) i,n Is the optimal position of the ith particle; g is the optimal position of the whole population; c 1 And c 2 Is a constant; r is (r) 1 And r 2 Is [0,1 ]]Random numbers in (a); v (V) i,n A speed of an ith particle representing an nth generation population; x is X i,n Representing the position of the ith particle of the nth generation population.
7. The optimization method of integrated circuit design data according to claim 1, wherein the weights in the local optimization process and the weights in the global optimization process each include:
updating the weight by using a weight linear decrementing strategy, wherein the weight updating formula is as follows:
wherein w is max And w min Representing the maximum and minimum values of the inertial weights; n (N) max The maximum iteration number, i represents the current iteration number, and w is the inertia weight.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110313460.XA CN113051856B (en) | 2021-03-24 | 2021-03-24 | Optimization method for integrated circuit design data |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110313460.XA CN113051856B (en) | 2021-03-24 | 2021-03-24 | Optimization method for integrated circuit design data |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113051856A CN113051856A (en) | 2021-06-29 |
| CN113051856B true CN113051856B (en) | 2024-01-19 |
Family
ID=76515096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110313460.XA Active CN113051856B (en) | 2021-03-24 | 2021-03-24 | Optimization method for integrated circuit design data |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113051856B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113239651B (en) * | 2021-07-12 | 2021-09-17 | 苏州贝克微电子有限公司 | Artificial intelligence implementation method and system for circuit design |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106844924A (en) * | 2017-01-12 | 2017-06-13 | 桂林电子科技大学 | Method based on Response Surface Method and genetic algorithm optimization PCB microstrip line constructions |
| CN110245436A (en) * | 2019-06-19 | 2019-09-17 | 山东大学 | A kind of Parallel Simulation circuit optimization method based on genetic algorithm and machine learning |
| CN112348155A (en) * | 2020-11-05 | 2021-02-09 | 扬州工业职业技术学院 | Optimization method and system of fuzzy neural network model |
-
2021
- 2021-03-24 CN CN202110313460.XA patent/CN113051856B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106844924A (en) * | 2017-01-12 | 2017-06-13 | 桂林电子科技大学 | Method based on Response Surface Method and genetic algorithm optimization PCB microstrip line constructions |
| CN110245436A (en) * | 2019-06-19 | 2019-09-17 | 山东大学 | A kind of Parallel Simulation circuit optimization method based on genetic algorithm and machine learning |
| CN112348155A (en) * | 2020-11-05 | 2021-02-09 | 扬州工业职业技术学院 | Optimization method and system of fuzzy neural network model |
Non-Patent Citations (2)
| Title |
|---|
| 衣文娟 ; .进化计算的PID控制参数快速整定算法.科技通报.2013,(09),全文. * |
| 贾其燕 ; 王友仁 ; 崔江 ; .一种基于遗传算法的动态电流测试生成方法.计算机技术与发展.2009,(06),全文. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113051856A (en) | 2021-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Cutkosky et al. | Momentum improves normalized sgd | |
| Sandri et al. | Analysis and correction of bias in total decrease in node impurity measures for tree-based algorithms | |
| US20160358068A1 (en) | Reducing computations in a neural network | |
| Örkcü et al. | Estimating the parameters of 3-p Weibull distribution using particle swarm optimization: A comprehensive experimental comparison | |
| CN100423012C (en) | Techniqes for making sure of buffer insertion | |
| CN113051856B (en) | Optimization method for integrated circuit design data | |
| WO2022095432A1 (en) | Neural network model training method and apparatus, computer device, and storage medium | |
| CN109800849A (en) | Dynamic cuckoo searching algorithm | |
| US20040230931A1 (en) | Placing cells of an IC design using partition preconditioning | |
| US8578320B2 (en) | Automatic design support apparatus and method | |
| CN110458287B (en) | Parameter updating method, device, terminal and storage medium of neural network optimizer | |
| Chou et al. | Wire length and delay minimization in general clock net routing | |
| CN114186671A (en) | Large-batch decentralized distributed image classifier training method and system | |
| Luo et al. | A novel sequential switching quadratic particle swarm optimization scheme with applications to fast tuning of PID controllers | |
| US8301579B2 (en) | Fast algorithm for convex optimization with application to density estimation and clustering | |
| US10691162B2 (en) | System and method for a hybrid current-mode and voltage-mode integrated circuit | |
| CN109378036A (en) | A kind of Heuristic Method based on two-line hybrid rice breeding mechanism | |
| Jinhai et al. | Dynamically-biased fixed-point LSTM for time series processing in AIoT edge device | |
| Oltean et al. | Multiobjective optimization method for analog circuits design based on fuzzy logic | |
| US20210279652A1 (en) | Automatic adjustment of replica exchange | |
| TW202230225A (en) | Method and device for calibration of analog circuits for neural network computing | |
| US11343650B1 (en) | Computation of a saddle-point | |
| Xu et al. | Subspace method based on neural networks for solving the partial differential equation | |
| Nzale et al. | A tool for automatic determination of model parameters using particle swarm optimization | |
| Jarndal et al. | GaN Power Transistor Modeling Using Global Optimization Based Artificial Neural Networks |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |