CN113050519A - CRC 16-based single-bit error correction FPGA implementation method - Google Patents

Abstract

The invention relates to a single-bit error correction FPGA implementation method based on CRC16, which comprises a data cache module, a read cache control module, an error judgment arbitration module and a sending control module, wherein the error judgment arbitration module comprises a CRC calculation module, a Hash mapping module and an error query judgment module.

Description

CRC 16-based single-bit error correction FPGA implementation method

Technical Field

The invention relates to the technical field of computers, in particular to a data transmission processing technology, and specifically relates to a single-bit error correction FPGA implementation method based on CRC 16.

Background

Today in the big data era, higher requirements are placed on security and efficiency of data transmission. The main point in security is the correctness of data transmission. The transmission efficiency is that less bandwidth is occupied under the condition of transmitting the same data, namely more data is transmitted under the condition of constant bandwidth. If the data transmission is wrong, the data needs to be retransmitted, which occupies extra bandwidth, resulting in reduced transmission efficiency. Today, electronic devices are so popular that electromagnetic interference exists everywhere, which causes great disadvantages to the security of data transmission, and also puts higher demands on data transmission and processing equipment.

CRC (cyclic redundancy check) is an important linear block code, not only has a very strong transmission error detection capability, but also is easily implemented inside an FPGA (field programmable gate array) by using a parallel processing method. The method is particularly suitable for positioning single-bit errors in high-speed data transmission.

In order to identify and correct abnormal errors generated in the data transmission process, a data sending party needs to add redundant information of data and effective data to send to a receiving party together, so that the receiving party can judge whether the data transmission is abnormal or not and correct the errors in the abnormal process. As shown in fig. 1, the prior art process is as follows:

(1) after receiving the data, the receiving device firstly carries out CRC operation on the data part;

(2) the CRC value computed by the receiving device is compared to the received CRC value. If the data are the same, the transmission is normal; if not, jumping to the step (3) to look up the table;

(3) and using the calculated CRC value as a retrieval address of the RAM for table lookup. The look-up table yields whether it is a singleton norm or a multi-bit anomaly and gives the anomaly bit in the case of singleton norms.

The prior art is divided into two types of implementation in a CPU (central processing unit) and an FPGA (field programmable gate array), the CPU can not implement parallel processing of data, the efficiency is low, the implementation scheme of the FPGA usually processes data information and redundancy check information separately at a receiving end, the time delay is increased, the data processing efficiency is reduced, a CRC (cyclic redundancy check) value obtained by calculation is used as a retrieval address of a RAM (random access memory) in the table look-up process, and the data bit width is large, so that too many on-chip RAMs and logic resources of the FPGA are occupied, and the resource waste is caused. The existing scheme has low efficiency and large resource consumption.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a simple and efficient single-bit error correction FPGA implementation method based on CRC16 for single-bit abnormal errors in the high-speed data transmission process.

The invention is realized by the following technical scheme, and provides a single-bit error correction FPGA realization method based on CRC16, which comprises a data cache module, a read cache control module, an error judgment arbitration module and a sending control module, and is characterized in that the error judgment arbitration module comprises a CRC calculation module, a Hash (Hash function) mapping module and an error query judgment module, and the process is as follows:

(1) data sent from a network is sent to a data caching module through a mac layer to realize caching of the data;

(2) when the read cache control module judges that data exist in the cache module, reading cached data information and redundant information and sending the data information and the redundant information to the CRC calculation module;

(3) performing CRC calculation on the data information and the redundant information by using a CRC calculation module, indicating that data transmission is normal when the calculation result is 0, and directly returning the normal result to the read cache control module; when the calculation result is not 0, indicating that the data transmission is abnormal, and sending the CRC calculation result to a Hash mapping module;

(4) hash mapping module instantiating a depth of 2ⁿ⁺¹The RAM is n + m in width, wherein n is the bit width of the unique normal position serial number; m is the bit width of the data obtained by the CRC calculation module, and the Hash mapping module converts the CRC value into shorter data serving as an index value for retrieving the data of the corresponding address of the RAM;

(5) and the error query judging module receives the data sent by the hash mapping module in real time. If the value is 0, the multi-bit exception is indicated; if not, the data is represented as the abnormal position of the single bit of the current data. The judgment result is sent to the sending control module.

(6) And the sending control module controls the data to be directly sent and discarded or to be subjected to single-bit turnover correction for sending according to the returned result.

Preferably, the initialization method of the RAM in the step (4) is as follows:

firstly, initializing data under an address corresponding to a hash index value corresponding to a single-bit error are a single-bit normal position serial number (high n-bit data) and a corresponding CRC value (low m-bit data);

when the hash value conflicts, carrying out XOR operation on the hash value of n +1 bits and the low n +1 bits of the CRC value to obtain a value which is used as an address again, and storing the current single-bit abnormal position serial number (high n-bit data) and the corresponding CRC value (low m-bit data) under the address change;

and all the rest addresses are initialized to 0.

Preferably, the data processing flow of the module in the step (4) is as follows:

reading out data under the address according to the index address;

judging data:

A. if the low m bit data under the address is 0, indicating that the multi-bit is abnormal, sending the high n bit 0 to an error query judgment module;

B. if the low m-bit data under the address is equal to the CRC value currently used for hash operation, the position serial number of the high n-bit is sent to an error query judgment module;

C. and if not, performing XOR operation on the hash value of the n +1 bit and the lower n +1 bit of the CRC value, taking the obtained value as the address again, and jumping to the step B.

In summary, the invention sends the data information and the redundant information to the CRC calculation module for Hash operation, thereby reducing the delay in the data processing and judging processes, and reducing the data bit width, i.e. reducing the address space for data retrieval.

Drawings

FIG. 1 is a block diagram of data transmission in the prior art;

FIG. 2 is a block diagram of the transmission error determination module according to the present invention;

FIG. 3 is a schematic diagram of the correction process when the ratio is more specific in the present invention.

Detailed Description

In order to clearly illustrate the technical features of the present invention, the present invention is further illustrated by the following detailed description with reference to the accompanying drawings.

The receiver-side check code calculated value is only related to the transmission error and the generator polynomial, and is not related to the transmitted information data. With respect to the above conclusions, a brief explanation is given of CRC-16 with a production polynomial of x16+ x12+ x5+1, as shown in Table 1.

TABLE 1 CRC values for single bit errors

In this embodiment, as shown in fig. 2 and fig. 3, the method for implementing a single-bit error correction FPGA based on CRC16 includes a data cache module, a read cache control module, an error judgment arbitration module, and a sending control module, and is characterized in that the error judgment arbitration module includes a CRC calculation module, a Hash mapping module, and an error query judgment module, and the process is as follows:

(1) data sent from a network is sent to a data caching module through a mac layer to realize caching of the data;

(2) when the read cache control module judges that data exist in the cache module, reading cached data information and redundant information and sending the data information and the redundant information to the CRC calculation module;

(3) performing CRC calculation on the data information and the redundant information by using a CRC calculation module, indicating that data transmission is normal when the calculation result is 0, and directly returning the normal result to the read cache control module; when the calculation result is not 0, indicating that the data transmission is abnormal, and sending the CRC calculation result to a Hash mapping module;

(4) h Hash mapping module, instantiating a depth of 2ⁿ⁺¹The RAM is n + m in width, wherein n is the bit width of the unique normal position serial number; m is the bit width of the data obtained by the CRC calculation module, and the Hash mapping module converts the CRC value into shorter data serving as an index value for retrieving the data of the corresponding address of the RAM;

(5) and the error query judging module receives the data sent by the hash mapping module in real time. If the value is 0, the multi-bit exception is indicated; if not, the data is represented as the abnormal position of the single bit of the current data. The judgment result is sent to the sending control module.

(6) And the sending control module controls the data to be directly sent and discarded or to be subjected to single-bit turnover correction for sending according to the returned result.

In this embodiment, the method for initializing the RAM in step (4) is as follows:

firstly, initializing data under an address corresponding to a hash index value corresponding to a single-bit error are a single-bit normal position serial number (high n-bit data) and a corresponding CRC value (low m-bit data);

when the hash value conflicts, carrying out XOR operation on the hash value of n +1 bits and the low n +1 bits of the CRC value to obtain a value which is used as an address again, and storing the current single-bit abnormal position serial number (high n-bit data) and the corresponding CRC value (low m-bit data) under the address change;

and all the rest addresses are initialized to 0.

The data processing flow of the module in the step (4) is as follows:

reading out data under the address according to the index address;

judging data:

A. if the low m bit data under the address is 0, indicating that the multi-bit is abnormal, sending the high n bit 0 to an error query judgment module;

B. if the low m-bit data under the address is equal to the CRC value currently used for hash operation, the position serial number of the high n-bit is sent to an error query judgment module;

C. and if not, performing XOR operation on the hash value of the n +1 bit and the lower n +1 bit of the CRC value, taking the obtained value as the address again, and jumping to the step B.

Finally, it should be further noted that the above examples and descriptions are not limited to the above embodiments, and technical features of the present invention that are not described may be implemented by or using the prior art, and are not described herein again; the above embodiments and drawings are only for illustrating the technical solutions of the present invention and not for limiting the present invention, and the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that changes, modifications, additions or substitutions within the spirit and scope of the present invention may be made by those skilled in the art without departing from the spirit of the present invention, and shall also fall within the scope of the claims of the present invention.

Claims (3)

1. A single-bit error correction FPGA implementation method based on CRC16 comprises a data cache module, a read cache control module, an error judgment arbitration module and a sending control module, and is characterized in that the error judgment arbitration module comprises a CRC calculation module, a Hash mapping module and an error query judgment module, and the process is as follows:

(1) data sent from a network is sent to a data caching module through a mac layer to realize caching of the data;

(2) when the read cache control module judges that data exist in the cache module, reading cached data information and redundant information and sending the data information and the redundant information to the CRC calculation module;

(3) performing CRC calculation on the data information and the redundant information by using a CRC calculation module, indicating that data transmission is normal when the calculation result is 0, and directly returning the normal result to the read cache control module; when the calculation result is not 0, indicating that the data transmission is abnormal, and sending the CRC calculation result to a Hash mapping module;

(4) hash mapping module instantiating a depth of 2ⁿ⁺¹The RAM is n + m in width, wherein n is the bit width of the unique normal position serial number; m is the bit width of the data obtained by the CRC calculation module, and the Hash mapping module converts the CRC value into shorter data serving as an index value for retrieving the data of the corresponding address of the RAM;

(5) and the error query judging module receives the data sent by the hash mapping module in real time. If the value is 0, the multi-bit exception is indicated; if not, the data is represented as the abnormal position of the single bit of the current data. The judgment result is sent to the sending control module.

(6) And the sending control module controls the data to be directly sent and discarded or to be subjected to single-bit turnover correction for sending according to the returned result.

2. The method for implementing the single-bit error correction FPGA based on the CRC16 of claim 1, wherein the initialization method of the RAM in the step (4) is as follows:

firstly, initializing data under an address corresponding to a hash index value corresponding to a single-bit error are a single-bit normal position serial number (high n-bit data) and a corresponding CRC value (low m-bit data);

when the hash value conflicts, carrying out XOR operation on the hash value of n +1 bits and the low n +1 bits of the CRC value to obtain a value which is used as an address again, and storing the current single-bit abnormal position serial number (high n-bit data) and the corresponding CRC value (low m-bit data) under the address change;

and all the rest addresses are initialized to 0.

3. The method for implementing the single-bit error correction FPGA based on the CRC16 of claim 2, wherein the data processing flow of the module in the step (4) is as follows:

reading out data under the address according to the index address;

judging data:

A. if the low m bit data under the address is 0, indicating that the multi-bit is abnormal, sending the high n bit 0 to an error query judgment module;

B. if the low m-bit data under the address is equal to the CRC value currently used for hash operation, the position serial number of the high n-bit is sent to an error query judgment module;

C. and if not, performing XOR operation on the hash value of the n +1 bit and the lower n +1 bit of the CRC value, taking the obtained value as the address again, and jumping to the step B.

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