CN113035786A - 半导体结构及其制造方法 - Google Patents
半导体结构及其制造方法 Download PDFInfo
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- CN113035786A CN113035786A CN202011116630.7A CN202011116630A CN113035786A CN 113035786 A CN113035786 A CN 113035786A CN 202011116630 A CN202011116630 A CN 202011116630A CN 113035786 A CN113035786 A CN 113035786A
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Abstract
公开一种半导体结构及其制造方法。半导体结构包括第一衬底、封装、第二衬底以及盖。封装贴合到第一衬底的第一侧。第二衬底贴合到第一衬底的第二侧。盖连接到第一衬底及第二衬底。盖包括:环形部,位于第一衬底的第一侧之上。环形部及第一衬底界定空间且封装容纳在空间中。盖还包括:多个外悬部,从环形部的隅角侧壁朝第二衬底延伸,以覆盖第一衬底的隅角侧壁。
Description
技术领域
本公开实施例涉及半导体结构及其制造方法。
背景技术
由于各种电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度的持续增加,半导体行业已经历快速增长。在很大程度上,集成密度的这种增加来自于最小特征大小(feature size)的不断地减小,这使得更多的组件能够集成到给定面积内。
由缩小电子器件的需求增加,亟需更小且更具创造性的半导体管芯的封装技术。这种封装***的实例是叠层封装(Package-on-Package,PoP)技术。在PoP器件中,顶部半导体封装被堆叠在底部半导体封装的顶部上,以提供高集成水平及组件密度。另一实例是衬底上晶片上芯片(Chip-On-Wafer-On-Substrate,CoWoS)结构,其中半导体芯片贴合到晶片(例如,中介层)以形成晶片上芯片(Chip-On-Wafer,CoW)结构。然后将CoW结构贴合到衬底(例如,印刷电路板(printed circuit board,PCB))以形成CoWoS结构。这些及其他先进的封装技术使得半导体器件的生产具有增强的功能及小的占用面积(footprint)。
发明内容
根据实施例,一种半导体结构包括:第一衬底,包括第一侧及与所述第一侧相对的第二侧;封装,贴合到所述第一衬底的所述第一侧;第二衬底,贴合到所述第一衬底的所述第二侧;盖,连接到所述第一衬底及所述第二衬底,所述盖包括:环形部,位于所述第一衬底的所述第一侧之上,其中所述环形部及所述第一衬底界定空间且所述封装容纳在所述空间中;以及多个外悬部,从所述环形部的隅角侧壁朝所述第二衬底延伸,以覆盖所述第一衬底的隅角侧壁。
根据另一实施例,一种半导体结构包括:第一衬底,包括第一侧及与所述第一侧相对的第二侧;封装,贴合到所述第一衬底的所述第一侧;第二衬底,贴合到所述第一衬底的所述第二侧;盖,连接到所述第一衬底及所述第二衬底,所述盖包括:帽部;环形部,从所述帽部的底表面朝所述第一衬底延伸,其中所述环形部、所述帽部及所述第一衬底界定空间,且所述封装容纳在所述空间中;以及多个外悬部,从所述帽部的隅角侧壁朝所述第二衬底延伸,以覆盖所述第一衬底的隅角侧壁。
根据再一实施例,一种制造半导体结构的方法包括:将封装贴合到第一衬底的第一侧;提供盖,其中所述盖包括环形部及多个外悬部;将所述盖的所述环形部的底表面通过第一粘合剂贴合到所述第一衬底的所述第一侧;将所述第一衬底的与所述第一侧相对的第二侧通过多个电连接件贴合到第二衬底;以及将所述盖的所述多个外悬部的底表面通过第二粘合剂贴合到所述第二衬底,所述多个外悬部从所述环形部的隅角侧壁朝所述第二衬底延伸,以覆盖所述第一衬底的隅角侧壁。
附图说明
结合附图阅读以下详细说明,会最好地理解本公开的各个方面。应注意,根据本行业中的标准惯例,各种特征并非按比例绘制。事实上,为使论述清晰起见,可任意增大或减小各种特征的尺寸。
图1A到图5A示出根据各种实施例的制造半导体结构的中间阶段的剖视图。
图1B到图5B示出制造图1A到图5A的半导体结构的中间阶段的俯视图。
图6示出图5A的半导体结构的透视图。
图7A、图7B、图8A、图9A及图10A示出根据各种实施例的半导体结构的剖视图。
图8B到图10B示出图8A到图10A的半导体结构的俯视图。
图11是示出根据一些实施例的制造半导体结构的方法的流程图。
具体实施方式
以下公开内容提供用于实施本发明的不同特征的许多不同的实施例或实例。以下阐述组件及布置的具体实例以简化本公开。当然,这些仅为实例而非旨在进行限制。举例来说,以下说明中将第一特征形成在第二特征之上或第二特征上可包括其中第一特征与第二特征被形成为直接接触的实施例,且也可包括其中第一特征与第二特征之间可形成有附加特征从而使得所述第一特征与所述第二特征可不直接接触的实施例。另外,本公开可能在各种实例中重复使用参考编号和/或字母。这种重复使用是出于简洁及清晰的目的,而不是自身指示所论述的各种实施例和/或配置之间的关系。
此外,为易于说明,本文中可能使用例如“在...之下(beneath)”、“在...下方(below)”、“下部的(lower)”、“在...上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括器件在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向),且本文中所使用的空间相对性描述语可同样相应地进行解释。
本公开也可包括其他特征及工艺。举例来说,可包括测试结构,以帮助对三维(three-dimensional,3D)封装或三维集成电路(three-dimensional integratedcircuit,3DIC)器件进行验证测试。所述测试结构可包括例如在重布线层中或在衬底上形成的测试焊盘,以使得能够对3D封装或3DIC进行测试、使用探针和/或探针卡(probe card)等。可对中间结构以及最终结构实行验证测试。另外,本文中所公开的结构及方法可结合包括对已知良好管芯(known good die)进行中间验证的测试方法来使用,以提高良率并降低成本。
各种实施例提供包括盖的半导体结构。盖具有多个外悬部。外悬部贴合到板,以防止CoWoS结构的翘曲以及CoWoS结构与板之间的冷接缝(cold joint)。另外,外悬部被设置成环绕CoWoS结构的隅角侧壁,以保护电连接件并减少电连接件中由于外部应力导致的裂纹。
图1A到图5A示出根据各种实施例的制造半导体结构100的中间阶段的剖视图。图1B到图5B示出制造图1A到图5A的半导体结构100的中间阶段的俯视图。图6示出图5A的半导体结构100的透视图。在各种实施例中,半导体结构100包括封装103、第一衬底110及第二衬底104。封装103可为三维集成电路器件(例如,晶片上芯片(CoW)封装),且封装103可被称为CoW封装103。CoW封装103结合到第一衬底110。CoW封装103与第一衬底110的组合可被称为衬底上晶片上芯片(CoWoS)结构102。CoWoS结构102可包括芯片堆叠,例如逻辑搭载逻辑(logic-on-logic,LoL)、逻辑搭载存储器(memory-on-logic,MoL)等。
图1A及图1B示出CoWoS结构102。在一些实施例中,CoWoS结构102的CoW封装103包括管芯106、管芯108及封装组件105。管芯106可与管芯108相同或不同。举例来说,第一管芯106与第二管芯108具有不同的功耗。在一些实施例中,管芯106可为高功耗管芯,而管芯108可为低功耗管芯。尽管图1A示出具有一个管芯106及一个管芯108的CoWoS结构102,但其他实施例可包括任意数目的管芯106和/或管芯108。管芯106可设置在两个管芯108之间。管芯106及管芯108可为管芯堆叠且可被称为芯片。管芯106消耗相对高的功率量,且因此,与较低功耗的管芯相比会产生相对大量的热。举例来说,管芯106可消耗从约100W到约1,000W的功率,且管芯108可消耗从约10W到约100W的功率。管芯106消耗的功率对管芯108消耗的功率的比率可为从约10到约30,例如约16。在一些实施例中,管芯106可为处理器,例如中央处理器(central processing unit,CPU)、图形处理单元(graphic processing unit,GPU)等。管芯108可为存储器管芯,例如高带宽存储器(high bandwidth memory,HBM)、存储器立方体、存储器堆栈等。在一些实施例中,管芯106及108分别为扇出型封装及扇入型封装。
管芯106及管芯108可被包含模制化合物的包封体120环绕。可将管芯106、管芯108及包封体120平坦化,使得管芯106的顶表面、管芯108的顶表面及包封体120的顶表面齐平。由于在包封体120中可能不会产生热量,因此在包封体120附近的区域中散热要求可能较低。
CoW封装103的封装组件105可为中介层衬底,所述中介层衬底可为半导体衬底,例如硅衬底。封装组件105也可由另一种半导体材料(例如硅锗、碳化硅等)形成。根据一些实施例,在封装组件105的表面处形成有例如晶体管(未单独示出)等有源器件。在封装组件105中也可形成有例如电阻器和/或电容器等无源器件(未单独示出)。根据本公开的替代实施例,封装组件105可为半导体衬底或介电衬底,且相应的封装组件105可不包括其中的有源器件。根据这些实施例,封装组件105可包括或可不包括形成在其中的无源器件。
可形成从封装组件105的顶表面延伸到封装组件105中的穿孔。在封装组件105是硅衬底的实施例中,穿孔可被称为衬底穿孔或硅穿孔。在一些实施例中,封装组件105可包括形成在衬底之上的内连结构(未单独示出),所述内连结构用于电连接到集成电路器件(如果有的话)及CoWoS结构102的穿孔。内连结构可包括多个介电层、形成在介电层中的金属线、以及形成在上覆金属线与下伏金属线之间并将上覆金属线与下伏金属线内连的通孔。根据一些实施例,介电层可由氧化硅、氮化硅、碳化硅、氮氧化硅、其组合、和/或其多层形成。作为另外一种选择,介电层可包括具有低介电常数(k值)的一个或多个低介电常数介电层。举例来说,介电层中的低介电常数介电材料的k值可低于约3.0或低于约2.5。
封装组件105的俯视图大小大于管芯106及108的俯视图大小。管芯106及管芯108可通过倒装芯片结合而结合到封装组件105,其中使用多个电连接件109(例如金属凸块、焊料球等)将管芯106及管芯108结合到封装组件105。
CoW封装103贴合到第一衬底110的第一侧。在一些实施例中,CoW封装103结合到第一衬底110的顶表面110a。CoW封装103可通过多个电连接件112电耦合到及机械耦合到第一衬底110,所述多个电连接件112可为导电凸块、微凸块、金属柱等。
第一衬底110可为陶瓷衬底或有机衬底。有机衬底可为层压式有机衬底或积层式有机衬底(build-up organic substrate)。第一衬底110还包括导电特征,例如导电层及导通孔。导电层及导通孔可分别由任何合适的材料(例如铜箔及铜/铜合金)形成。也可使用其他导电材料。导电特征可用于热传导目的,以使热量远离管芯106及108的中心消散。在一些实施例中,导电特征也可用于电连接,例如,作为第一衬底110中的接地、电源、和/或信号输入及输出层。在其他实施例中,一些或所有导电特征可能不会提供电功能且可被称为虚拟特征。
在一些实施例中,第一衬底110包括芯体及设置在芯体的前侧及背侧上的积层层(build-up layers)。穿孔可从芯体的前侧延伸且电连接到芯体的背侧。芯体可包括导电层(例如,铜箔)。芯体可包括两个、四个、六个、八个、或更多个导电层。尽管附加的导电层可增加第一衬底110的整体热导率,但导电层的数目可根据半导体结构的布局设计(例如,电路设计)而定。积层层包括内连结构,所述内连结构具有通过导通孔电连接的图案化导电层。在各种实施例中,导电特征(导电层及导通孔)可用于功能性电气目的,例如电源、接地、和/或信号IO层。在各种其他实施例中,导电特征可包括用于增加热导率的虚拟特征。在一些实施例中,第一衬底110包括有源器件、无源器件等。在一些实施例中,根据布局设计而定,第一衬底110包括不同数目的芯体层及积层层。
在第一衬底110与CoW封装103之间可形成有环绕第一电连接件112的底部填充材料118。底部填充材料118也可延伸且环绕CoW封装103。
在图2A及图2B中,在一些实施例中,CoWoS结构102包括沉积在第一衬底110的顶表面110a上的粘合剂122。在一些实施例中,CoWoS结构102还包括沉积在CoW封装103之上的热界面材料(thermal interface material,TIM)124。粘合剂122可为环氧树脂、硅树脂、胶水等。粘合剂122可具有优于TIM 124的粘合能力。粘合剂122可被定位成使得散热特征(例如,图3A中所示的盖126)贴合在CoWoS结构102周围。因此,在一些实施例中,粘合剂122可被设置成围绕CoW封装103的***或者甚至包围CoW封装103。
TIM 124可为具有良好热导性的聚合物,以利于散热特征(例如,图3A中所示的盖126)散熱。在一些实施例中,TIM 124可包含具有导热填料的聚合物。导热填料可将TIM 124的有效热导率从约10W/m·K增加到约50W/m·K或更高。适用的导热填料材料可包括氧化铝、氮化硼、氮化铝、铝、铜、银、铟、其组合等。在其他实施例中,TIM 124可包含其他材料,例如包括银、铟膏等的金属系材料或焊料系材料。在再一些实施例中,TIM 124可包含膜系材料或片系材料(sheet-based material),例如包括合成碳纳米管(carbon nanotube,CNT)的片系材料或具有垂直取向的石墨填料的导热片。
尽管TIM 124被示出为在CoW封装103的包封体120、管芯106及管芯108之上延伸的连续的TIM,但在一些实施例中,TIM 124可为不连续的。举例来说,在相邻的管芯(例如,管芯106和/或管芯108)之间的TIM 124中可具有空隙,以减少管芯之间的侧向热交互作用。在一些实施例中,TIM 124可在粘合剂122之后沉积;然而,TIM 124也可在粘合剂122之前沉积。
在图3A及图3B中,将盖126贴合到CoWoS结构102。盖126可被贴合以保护CoWoS结构102,以将CoWoS结构102产生的热量扩散到更大的面积,从而消散CoWoS结构102的热量。盖126可由具有高热导性的材料(例如钢、不锈钢、铜、铝、其组合等)形成。在一些实施例中,盖126可为涂覆有另一种金属(例如金)的金属。举例来说,盖126可由热导率从约100W/m·K到约400W/m·K(例如约400W/m·K)的材料形成。如果盖126的热导率低于100W/m·K,则无法提供足够的散热。如果盖126的热导率大于400W/m·K,则用于盖126的材料成本太高。
盖126覆盖且环绕CoW封装103及第一衬底110的部分。在一些实施例中,盖126是单一的连续的材料。在其他实施例中,盖126可包括可为相同或不同材料的多个部件。
盖126包括帽部128、环形部130及多个外悬部132。帽部128覆盖CoW封装103及第一衬底110。帽部128的俯视图面积大于CoW封装103的俯视图面积。在一些实施例中,盖126的帽部128与第一衬底110具有实质上相同的形状及实质上相同的俯视图面积。在一些实施例中,帽部128的底表面128b与位于CoW封装103之上的TIM 124实体接触。因此,帽部128使得热量能够从TIM 124远离CoW封装103而消散。在一些实施例中,帽部128的底表面128b与CoW封装103的管芯106及管芯108直接实体接触。因此,帽部128使得热量能够远离CoW封装103而消散。
盖126的环形部130从帽部128的底表面128b朝第一衬底110延伸。环形部130的俯视图大小大于CoW封装103的俯视图大小。在俯视图中,环形部130可包围CoW封装103。环形部130、帽部128及第一衬底110界定空间,且CoW封装103容纳在所述空间中。
在一些实施例中,环形部130的俯视图大小与第一衬底110的俯视图大小(长度及宽度)相同。环形部130具有内侧壁130s1及外侧壁130s2。在一些实施例中,环形部130的内侧壁130s1及外侧壁130s2是直的,但并不仅限于此。内侧壁130s1与底部填充材料118间隔开。换句话说,在CoW封装103、底部填充材料118及环形部130之间具有空隙AG。环形部130的外侧壁130s2可与第一衬底110的侧壁110s对齐。在一些实施例中,环形部130的外侧壁130s2与第一衬底110的侧壁110s实质上共面。
在一些实施例中,环形部130的俯视图大小大于第一衬底110的俯视图大小,如图7A及图7B中所示。环形部130的外侧壁130s2可不与第一衬底110的侧壁110s对齐。环形部130的外侧壁130s2可在侧向上延伸超过第一衬底110的侧壁110s。
环形部130的底表面130b的水平高度可相同于、高于、或低于CoW封装103的底表面103b的水平高度。环形部130的底表面130b的面积Ar对第一衬底110的面积Ap的比率介于从约10%到约50%的范围内。如果面积Ar对面积Ap的比率大于50%,则环形部130将占据第一衬底110过大的面积。
盖126的外悬部132位于帽部128的隅角侧壁128s处,且延伸以覆盖环形部130的隅角侧壁130s3及第一衬底110的隅角侧壁110s1。在一些实施例中,盖126具有四个外悬部132,但外悬部132的数目可根据半导体结构的布局设计(例如,电路设计)而定。在一些实施例中,外悬部132与环形部130的隅角侧壁130s3及第一衬底110的隅角侧壁110s1实质上共形。外悬部132在俯视图中具有例如L形形状,但本公开并不仅限于此。外悬部132可均为实质上相同的形状或者可为不同的形状。
外悬部132具有顶表面132a。外悬部132的顶表面132a的水平高度可高于第一衬底110的顶表面110a的水平高度,而外悬部132的顶表面132a的水平高度可低于、等于或高于帽部128的顶表面128a的水平高度。在一些实施例中,外悬部132的顶表面132a与帽部128的顶表面128a实质上共面。
外悬部132具有内侧壁132s1及外侧壁132s2。外悬部132的内侧壁132s1及外侧壁132s2可为例如直的、倾斜的或弯曲的,但并不仅限于此。在一些实施例中,内侧壁132s1与第一衬底110的隅角侧壁110s1接触。在一些实施例中,外悬部132的内侧壁132s1通过间隙与第一衬底110的隅角侧壁110s1隔开(如图7A及图7B中所示)。
外悬部132具有沿第一方向D1的长度Lo1及沿第二方向D2的长度Lo2。外悬部132的长度Lo1可相同或不同。外悬部132的长度Lo2可相同或不同。长度Lo1与长度Lo2可相同或不同。长度Lo1小于环形部130沿第一方向D1的长度Lr1,且长度Lo2小于环形部130沿第二方向D2的长度Lr2。在一些实施例中,长度Lo1对长度Lr1的比率介于从约60%到约5%的范围内;且长度Lo2对长度Lr2的比率介于从约100%到约5%的范围内。如果长度Lo1对长度Lr1的比率和/或长度Lo2对长度Lr2的比率大于60%,则所述工艺难以实行球栅阵列(ball grid array,BGA)返工。如果长度Lo1对长度Lr1的比率和/或长度Lo2对长度Lr2的比率低于5%,则外悬部132不能提供足够的机械强度。在一些实施例中,环形部130的长度Lr1与环形部130的长度Lr2不同,而外悬部132的长度Lo1与长度Lo2相同。
外悬部132沿第一方向D1具有厚度To1,且沿第二方向D2具有厚度To2。外悬部132的厚度To1可相同或不同。外悬部132的厚度To2可相同或不同。厚度To1与厚度To2可相同或不同。厚度To1小于环形部130沿第一方向D1的厚度Tr1,且厚度To2小于环形部130沿第二方向D2的厚度Tr2。厚度To1对厚度Tr1的比率介于例如从约100%到约10%的范围内;且厚度To2对厚度Tr2的比率介于例如从约100%到约10%的范围内。在一些实施例中,厚度To1及To2分别介于从200μm到5000μm的范围内。如果外悬部132的厚度To1或To2小于200μm,则粘合剂136的面积(如图5A中所示)不足,从而导致粘合强度差。如果外悬部132的厚度To1或To2大于5000μm,则外悬部132将占据第二衬底104过大的面积,且增加重量。
相邻的外悬部132沿第一方向D1隔开距离d1。距离d2沿第二方向D2将相邻的外悬部132隔开。距离d1及d2一般来说大于零。在一些实施例中,距离d1对环形部130的长度Lr1的比率介于从大于0%到约95%的范围内,且距离d2对环形部130的长度Lr2的比率介于从大于0%到约95%的范围内。如果距离d2对长度Lr2的比率大于95%,则粘合剂136的面积(如图5A中所示)太小,从而导致粘合强度差。
外悬部132的底表面132b的水平高度低于第一衬底110的底表面110b的水平高度。外悬部132的底表面132b可具有相同的面积或不同的面积Ao。每个外悬部132的底表面132b的面积Ao小于环形部130的底表面130b的面积Ar。在一些实施例中,面积Ao对面积Ar的比率介于从约0.1%到约20%的范围内。如果面积Ao对面积Ar的比率低于0.1%,则粘合强度可能不足。如果面积Ao对面积Ar的比率大于20%,则盖126的过大重量及面积可增加成本且在下伏的衬底上产生过度的应变。
环形部130的底表面130b通过粘合剂122粘合到第一衬底110。粘合剂122具有比TIM 124大的粘合能力但比TIM 124低的热导率。因此,在一些实施例中,粘合剂122设置在CoW封装103的***周围以及盖126与第一衬底110之间,以将盖126的环形部130的底表面130b粘合到第一衬底110的顶表面110a。
在一些实施例中,粘合剂122设置在环形部130的底表面130b下方。在替代实施例中,粘合剂122进一步延伸到环形部130的内侧壁130s1的下部部分,同时粘合剂122与底部填充材料118间隔开。粘合剂122的面积可等于、小于或大于环形部130的底表面130b的面积。粘合剂122在俯视图中具有例如环形形状,但并不仅限于此。
在替代实施例中,半导体结构100’的粘合剂122包括第一部分122a及第二部分122b(如图7A及图7B中所示)。第一部分122a设置在CoW封装103的***周围以及盖126与第一衬底110之间,以将盖126的环形部130粘合到第一衬底110的顶表面110a。第二部分122b设置在第一衬底110的隅角侧壁110s1与外悬部132的内侧壁132s1之间的间隙中,使得外悬部132通过第二部分122b粘合到第一衬底110的隅角侧壁110s1。在一些实施例中,第二部分122b连接到第一部分122a(如图7A中所示)。在替代实施例中,第二部分122b与第一部分122a间隔开(如图7B中所示)。
在图3A及图3B中,多个电连接件116结合到第一衬底110的底表面110b。所述多个电连接件116可为导电凸块、微凸块、金属柱等。第一衬底110的隅角下方的电连接件116在侧向上与外悬部132相邻且与外悬部132间隔开。
在图4A及图4B中,第二衬底104贴合到与第一衬底110的第一侧相对的第二侧。CoWoS结构102的第一衬底110通过回焊工艺结合到第二衬底104的顶表面104a。第一衬底110可通过电连接件116电耦合及机械耦合到第二衬底104。第二衬底104可为封装衬底,所述封装衬底可为印刷电路板(PCB)等。第二衬底104可包括一个或多个介电层及导电特征,例如导电线及导通孔。在一些实施例中,第二衬底104可包括穿孔、有源器件、无源器件等。第二衬底104可还包括形成在第二衬底104的上表面及下表面处的导电焊盘。
在图4A、图5A及图5B中,向第二衬底104的顶表面104a与外悬部132的底表面132b之间的空间S中分配粘合剂136。空间S的高度Hs介于从约10μm到约300μm的范围内。如果空间S的高度小于10μm,则粘合剂136难以流入到空间S中。如果空间S的高度Hs大于300μm,则对于粘合剂136的流动而言毛细效应(capillary effect)太弱。在一些实施例中,粘合剂136与电连接件116间隔开。粘合剂136可为环氧树脂、硅树脂、胶水等。粘合剂136可具有优于TIM 124的粘合能力。粘合剂136与粘合剂122可具有相同的材料或不同的材料。粘合剂136可具有从约10GPa到约1MPa的杨氏模量(Young’s modulus)。粘合剂136可具有从约10μm到约300μm的厚度。
外悬部132的底表面132b通过粘合剂136粘合到第二衬底104的顶表面104a。每个粘合剂136的俯视图面积Aa3可等于、相同于、或大于对应的外悬部132的面积Ao1。举例来说,每个粘合剂136的俯视图面积Aa3可小于粘合剂122的俯视图面积Aa。每个粘合剂136的面积Aa3及粘合剂122的面积Aa分别与外悬部132的底表面132b的面积Ao及环形部130的底表面130b的面积Ar相关。在一些实施例中,俯视图面积Aa3对俯视图面积Aa的比率介于例如从约0.1%到约20%的范围内。如果面积Aa3对面积Aa的比率低于0.1%,则粘合强度可能不足。如果面积Aa3对面积Aa的比率大于20%,则盖126的过大重量及面积可增加成本且在下伏的衬底上产生过度的应变。
一旦将盖126与第二衬底104粘合,便可通过向粘合剂122及136以及TIM 124加热而使粘合剂122及136以及TIM 124固化。在一些实施例中,可通过将CoWoS结构102放置在固化炉中而使粘合剂122及136以及TIM 124固化。在固化工艺之后,粘合剂122可具有从200μm到约20μm的厚度T1,且每个粘合剂136可具有小于约300μm的厚度T2,且TIM 124可具有小于约200μm的厚度T3。
在图5A、图5B及图6中,贴合到第二衬底104的盖126的外悬部132可用于限制电连接件116的偏离,且可有助于防止CoWoS结构102的翘曲以及CoWoS结构102与第二衬底104之间的冷接缝。另外,盖126的外悬部132被设置成环绕CoWoS结构102的隅角侧壁、可保护电连接件116且减少由外部应力导致的电连接件116中的裂纹。CoWoS结构102的翘曲及电连接件116的裂纹的减少有助于形成更可靠的半导体结构。
图8A示出根据各种实施例的半导体结构200的剖视图。图8B示出图8A的半导体结构200的俯视图。
在图8A及图8B中,半导体结构200类似于图5A及图5B中所示的半导体结构100,且相同的参考编号表示相同的组件。半导体结构200的盖226包括帽部228、环形部230、多个外悬部232及多个突出部234。帽部228、环形部230及所述多个外悬部232的构造及材料类似于帽部128、环形部130及所述多个外悬部132的构造及材料,且不再进行重复。
突出部234从外悬部232的外侧壁232s2朝第二衬底104的边缘延伸。突出部234的高度Hp小于外悬部232的高度Ho。突出部234的高度Hp被界定成从突出部234的顶表面234a到底表面234b的距离。外悬部232的高度Ho被界定成从帽部228的底表面228b到外悬部232的底表面232b的距离。高度Hp对高度Ho的比率介于例如从约10%到约100%的范围内。如果高度Hp对高度Ho的比率低于10%,则突出部234不会提供足够的支撑。
在一些实施例中,突出部234与外悬部232共形。举例来说,突出部234在俯视图中可具有L形形状。突出部234与外悬部232的组合在俯视图及剖视图中可具有L形形状,但本公开并不仅限于此。
在一些实施例中,突出部234的底表面234b与外悬部232的底表面232b的组合面积Apo对环形部230的面积Ar2的比率介于从约1%到约60%的范围内。在其他一些实施例中,突出部234的底表面234b与外悬部232的底表面232b的组合面积Apo对环形部230的面积Ar2的比率介于从约1%到约20%的范围内。如果面积Apo对面积Ar2的比率低于1%,则粘合强度可能不足。如果面积Apo对面积Ar2的比率大于20%,则盖126的过大重量及面积将导致成本增加且在下伏的衬底上产生过度的应变。
在外悬部232的底表面232b及突出部234的底表面234b下方设置有粘合剂236,以将外悬部232及突出部234粘合到第二衬底104的顶表面104a。因此,由于突出部234提供了附加的底表面234b,因此突出部234可增加盖126到CoWoS结构102的粘合力。
每个粘合剂236的俯视图面积Aa3可等于、相同于、或大于突出部234的底表面234b与外悬部232的底表面232b的组合面积Apo。举例来说,每个粘合剂236的俯视图面积Aa3可小于环形部230的底表面230b下方的粘合剂222的俯视图面积Aa。在一些实施例中,俯视图面积Aa3对俯视图面积Aa的比率介于从约1%到约30%的范围内。在其他一些实施例中,俯视图面积Aa3对俯视图面积Aa的比率介于从约1%到约10%的范围内。如果俯视图面积Aa3对俯视图面积Aa的比率低于1%,则粘合强度可能不足。如果俯视图面积Aa3对俯视图面积Aa的比率大于10%,则盖226的过大重量及面积可增加成本且在下伏的衬底上产生过度的应变。
图9A示出根据各种实施例的半导体结构300的剖视图。图9B示出图9A的半导体结构300的俯视图。
在图9A及图9B中,半导体结构300类似于图5A及图5B中所示的半导体结构100,且相同的参考编号表示相同的组件。半导体结构300的盖326包括帽部328、环形部330及多个外悬部332。环形部330及所述多个外悬部332的构造及材料类似于环形部130及所述多个外悬部332的构造及材料,且不再进行重复。帽部328的构造类似于图5A及图5B中所示的帽部128的构造,但帽部328中具有开口329。开口329的俯视图大小可小于、等于或大于CoW封装103的俯视图大小。帽部328的顶表面328a的水平高度可低于、等于或高于CoW封装103的顶表面103a的水平高度。帽部328的底表面328b的水平高度可低于、等于或高于CoW封装103的顶表面103a的水平高度。在一些实施例中,开口329暴露出CoW封装103的顶表面103a且与环形部330和CoW封装103之间的间隙G连通,从而改善CoWoS结构102的散热。
图10A示出根据各种实施例的半导体结构400的剖视图。图10B示出图10A的半导体结构400的俯视图。
在图10A及图10B中,半导体结构400类似于图5A及5B中所示的半导体结构100,且相同的参考编号指代相同的组件。半导体结构400的盖426包括环形部430及多个外悬部432,但不包括环形部430上的帽部。环形部430及所述多个外悬部432的材料及构造类似于环形部130及所述多个外悬部132的材料及构造,且不再进行重复。盖426与盖126之间的构造差异将在下面详细阐述。
外悬部432定位在外悬部430的隅角侧壁430s3及第一衬底110的隅角侧壁110s1处。外悬部432具有顶表面432a。外悬部432的顶表面432a的水平高度可高于第一衬底110的顶表面110a的水平高度。外悬部432的顶表面432a的水平高度可低于、等于、或高于环形部430的表面430a的水平高度。在一些实施例中,外悬部432的顶表面432a与环形部430的顶表面430a可实质上共面。
盖426的环形部430设置在第一衬底110之上且可包围CoW封装103。环形部430的顶表面430a的水平高度可等于或高于CoW封装103的顶表面103a的水平高度。环形部430暴露出CoW封装103的顶表面103a及第一衬底110的顶表面110a的一部分,从而改善CoWoS结构102的散热。
图11是示出根据一些实施例的制造半导体结构(例如(举例来说),图5A中所示的半导体结构100、100’、300或400)的方法的流程图。所述方法从工艺1101开始,其中如上面参照图1A所述,将封装(例如(举例来说),图1A中所示的封装103)贴合到第一衬底(例如(举例来说),图1A中所示的第一衬底110)的第一侧。在工艺1102中,如上面参照图1A所述,提供盖(例如(举例来说),图3A、图8A、图9A或图10A中所示的盖126、226、326或426)。盖包括环形部(例如(举例来说)图3A、图8A或图9A中所示的环形部130、230或330)及多个外悬部(例如(举例来说),图3A、图9A或图10A中所示的外悬部132、332或432)。在工艺1103中,如上面参照图3A、图7A及图7B所述,利用第一粘合剂(例如(举例来说),图3A、图7A或图7B中所示的粘合剂122、122a、222)将环形部的底表面贴合到第一衬底的第一侧。在工艺1104中,如上面参照图3A及图4A所述,将第二衬底(例如(举例来说),图3A及图4A中所示的第二衬底104)通过多个电连接件(例如(举例来说),图3A及图4A中所示的电连接件116)贴合到第一衬底的与第一侧相对的第二侧。在工艺1105中,如上参照图5A所述,利用第二粘合剂(例如(举例来说),图5A中所示的粘合剂136)将盖的所述多个外悬部的底表面贴合到第二衬底。
本公开的实施例提供包括盖的半导体结构。盖具有多个外悬部,以限定电连接件在CoWoS结构与板之间的偏离,且防止CoWoS结构的翘曲以及CoWoS结构与板之间的冷接缝。另外,外悬部环绕CoWoS结构的隅角侧壁可减少由外部应力导致的电连接件中的裂纹。CoWoS结构的翘曲及电连接件的裂纹的减少有助于形成更可靠的半导体结构。
根据实施例,一种半导体结构包括:第一衬底,包括第一侧及与所述第一侧相对的第二侧;封装,贴合到所述第一衬底的所述第一侧;第二衬底,贴合到所述第一衬底的所述第二侧;盖,连接到所述第一衬底及所述第二衬底,所述盖包括:环形部,位于所述第一衬底的所述第一侧之上,其中所述环形部及所述第一衬底界定空间且所述封装容纳在所述空间中;以及多个外悬部,从所述环形部的隅角侧壁朝所述第二衬底延伸,以覆盖所述第一衬底的隅角侧壁。
在一些实施例中,所述多个外悬部与所述第一衬底的所述隅角侧壁实质上共形。
在一些实施例中,所述多个外悬部具有L形形状。
在一些实施例中,所述多个外悬部中的一者具有底表面,且所述底表面的面积小于所述环形部的底表面的面积。
在一些实施例中,所述的半导体结构还包括多个电连接件,所述多个电连接件将所述第一衬底的所述第二侧连接到所述第二衬底,其中所述多个外悬部在侧向上位于所述多个电连接件的一部分的旁边。
在一些实施例中,所述的半导体结构还包括:第一粘合剂,将所述盖的所述环形部连接到所述第一衬底;以及多个第二粘合剂,将所述盖的所述多个外悬部连接到所述第二衬底。
在一些实施例中,所述多个电连接件与所述多个第二粘合剂间隔开。
在一些实施例中,所述第一粘合剂还将所述多个外悬部的内侧壁连接到所述第一衬底的隅角侧壁。
根据另一实施例,一种半导体结构包括:第一衬底,包括第一侧及与所述第一侧相对的第二侧;封装,贴合到所述第一衬底的所述第一侧;第二衬底,贴合到所述第一衬底的所述第二侧;盖,连接到所述第一衬底及所述第二衬底,所述盖包括:帽部;环形部,从所述帽部的底表面朝所述第一衬底延伸,其中所述环形部、所述帽部及所述第一衬底界定空间,且所述封装容纳在所述空间中;以及多个外悬部,从所述帽部的隅角侧壁朝所述第二衬底延伸,以覆盖所述第一衬底的隅角侧壁。
在一些实施例中,所述帽部覆盖所述封装的顶表面,且在所述封装、所述环形部及所述帽部之间具有空隙。
在一些实施例中,所述帽部具有开口,所述开口暴露出所述封装的顶表面。
在一些实施例中,所述盖还包括多个突出部,所述多个突出部从所述多个外悬部的外侧壁朝所述第二衬底的边缘延伸。
在一些实施例中,所述的半导体结构还包括:第一粘合剂,将所述盖的所述环形部连接到所述第一衬底;以及多个第二粘合剂,将所述盖的所述多个外悬部连接到所述第二衬底。
在一些实施例中,所述多个突出部还通过所述多个第二粘合剂连接到所述第二衬底。
在一些实施例中,所述多个外悬部与所述第一衬底的所述隅角侧壁实质上共形。
在一些实施例中,所述的半导体结构还包括多个电连接件,所述多个电连接件将所述第一衬底的所述第二侧连接到所述第二衬底,其中所述多个外悬部在侧向上位于所述多个电连接件的一部分旁边。
在一些实施例中,所述的半导体结构,其中所述封装包括:中介层衬底;第一管芯,结合到所述中介层;第二管芯,与所述第一管芯相邻且结合到所述中介层,其中所述第一管芯与所述第二管芯具有不同的功耗;以及包封体,包封所述第一管芯及所述第二管芯。
根据再一实施例,一种制造半导体结构的方法包括:将封装贴合到第一衬底的第一侧;提供盖,其中所述盖包括环形部及多个外悬部;将所述盖的所述环形部的底表面通过第一粘合剂贴合到所述第一衬底的所述第一侧;将所述第一衬底的与所述第一侧相对的第二侧通过多个电连接件贴合到第二衬底;以及将所述盖的所述多个外悬部的底表面通过第二粘合剂贴合到所述第二衬底,所述多个外悬部从所述环形部的隅角侧壁朝所述第二衬底延伸,以覆盖所述第一衬底的隅角侧壁。
在一些实施例中,所述制造半导体结构的方法还包括:在所述将所述第一衬底的所述第二侧贴合到所述第二衬底之前且在贴合所述盖的所述环形部的所述底表面之后,将所述多个电连接件结合在所述第一衬底的所述第二侧上。
在一些实施例中,所述制造半导体结构的方法还包括:
将所述盖的所述多个外悬部的侧壁通过所述第一粘合剂贴合到所述第一衬底的所述隅角侧壁。
以上概述了若干实施例的特征,以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应理解,他们可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到,这些等效构造并不背离本公开的精神及范围,而且他们可在不背离本公开的精神及范围的条件下在本文中作出各种改变、代替及变更。
[符号的说明]
100:半导体结构/半导体
100’、200、300、400:半导体结构
102:衬底上晶片上芯片(CoWoS)结构
103:封装/CoW封装
103a、104a、110a、128a、132a、234a、328a、432a:顶表面
103b、110b、128b、130b、132b、228b、230b、232b、234b、328b:底表面
104:第二衬底
105:封装组件
106、108:管芯
109、112、116:电连接件
110:第一衬底
110s:侧壁
110s1、128s、130s3、430s3:隅角侧壁
118:底部填充材料
120:包封体
122、136、222、236:粘合剂
122a:第一部分
122b:第二部分
124:热界面材料(TIM)
126、226、326、426:盖
128、228、328:帽部
130:环形部
130s1、132s1:内侧壁
130s2、132s2、232s2:外侧壁
132:外悬部
230、330、430:环形部
232、332、432:外悬部
234:突出部
329:开口
430a:表面
1101、1102、1103、1104、1105:工艺
Aa、Aa3:面积
AG:空隙
Ao、Ap、Ar、Ar2:面积
Apo:面积
D1:第一方向
D2:第二方向
d1、d2:距离
G:间隙
Ho、Hs、Hp:高度
Lo1、Lo2、Lr1、Lr2:长度
S:空间
T1、T2、T3、To1、To2、Tr1、Tr2:厚度
Claims (10)
1.一种半导体结构,其特征在于包括:
第一衬底,包括第一侧及与所述第一侧相对的第二侧;
封装,贴合到所述第一衬底的所述第一侧;
第二衬底,贴合到所述第一衬底的所述第二侧;以及
盖,连接到所述第一衬底及所述第二衬底,其中所述盖包括:
环形部,位于所述第一衬底的所述第一侧之上,其中所述环形部及所述第一衬底界定空间且所述封装容纳在所述空间中;以及
多个外悬部,从所述环形部的隅角侧壁朝所述第二衬底延伸,以覆盖所述第一衬底的隅角侧壁。
2.根据权利要求1所述的半导体结构,其中所述多个外悬部与所述第一衬底的所述隅角侧壁实质上共形。
3.一种半导体结构,其特征在于包括:
第一衬底,包括第一侧及与所述第一侧相对的第二侧;
封装,贴合到所述第一衬底的所述第一侧;
第二衬底,贴合到所述第一衬底的所述第二侧;以及
盖,连接到所述第一衬底及所述第二衬底,所述盖包括:
帽部;
环形部,从所述帽部的底表面朝所述第一衬底延伸,其中所述环形部、所述帽部及所述第一衬底界定空间,且所述封装容纳在所述空间中;以及
多个外悬部,从所述帽部的隅角侧壁朝所述第二衬底延伸,以覆盖所述第一衬底的隅角侧壁。
4.根据权利要求3所述的半导体结构,其中所述帽部覆盖所述封装的顶表面,且在所述封装、所述环形部及所述帽部之间具有空隙。
5.根据权利要求3所述的半导体结构,其中所述帽部具有开口,所述开口暴露出所述封装的顶表面。
6.根据权利要求3所述的半导体结构,其中所述盖还包括多个突出部,所述多个突出部从所述多个外悬部的外侧壁朝所述第二衬底的边缘延伸。
7.根据权利要求3所述的半导体结构,其中所述封装包括:
中介层衬底;
第一管芯,结合到所述中介层;
第二管芯,与所述第一管芯相邻且结合到所述中介层,其中所述第一管芯与所述第二管芯具有不同的功耗;以及
包封体,包封所述第一管芯及所述第二管芯。
8.一种制造半导体结构的方法,其特征在于包括:
将封装贴合到第一衬底的第一侧;
提供盖,其中所述盖包括环形部及多个外悬部;
将所述盖的所述环形部的底表面通过第一粘合剂贴合到所述第一衬底的所述第一侧;
将所述第一衬底的第二侧通过多个电连接件贴合到第二衬底,所述第一衬底的所述第二侧与所述第一侧相对;以及
将所述盖的所述多个外悬部的底表面通过第二粘合剂贴合到所述第二衬底,所述多个外悬部从所述环形部的隅角侧壁朝所述第二衬底延伸,以覆盖所述第一衬底的隅角侧壁。
9.根据权利要求8所述制造半导体结构的方法,还包括:在所述将所述第一衬底的所述第二侧贴合到所述第二衬底之前且在贴合所述盖的所述环形部的所述底表面之后,将所述多个电连接件结合在所述第一衬底的所述第二侧上。
10.根据权利要求8所述制造半导体结构的方法,还包括:
将所述盖的所述多个外悬部的侧壁通过所述第一粘合剂贴合到所述第一衬底的所述隅角侧壁。
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US11270956B2 (en) * | 2020-03-27 | 2022-03-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and fabricating method thereof |
US20220052667A1 (en) * | 2020-08-14 | 2022-02-17 | Qorvo Us, Inc. | Electronic device with solder interconnect and multiple material encapsulant |
US11764118B2 (en) * | 2021-04-29 | 2023-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and formation method of chip package with protective lid |
US20230063270A1 (en) * | 2021-08-31 | 2023-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor die package with ring structure and method for forming the same |
US20230078862A1 (en) * | 2021-09-13 | 2023-03-16 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing semiconductor devices |
US20240071847A1 (en) * | 2022-08-26 | 2024-02-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method |
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US9299649B2 (en) * | 2013-02-08 | 2016-03-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
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US10269682B2 (en) * | 2015-10-09 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices |
US9735131B2 (en) | 2015-11-10 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-stack package-on-package structures |
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TW201947712A (zh) * | 2018-05-15 | 2019-12-16 | 宏濂科技股份有限公司 | 晶片及感測元件之封裝結構及其製作方法 |
US10978373B2 (en) * | 2018-06-19 | 2021-04-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device methods of manufacture |
KR102566974B1 (ko) * | 2018-07-11 | 2023-08-16 | 삼성전자주식회사 | 반도체 패키지 |
US10770369B2 (en) * | 2018-08-24 | 2020-09-08 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package |
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TW202127591A (zh) | 2021-07-16 |
US11450580B2 (en) | 2022-09-20 |
US20210193538A1 (en) | 2021-06-24 |
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