CN113026067A

CN113026067A - Electroplating solution and electroplating process for wafer level packaging

Info

Publication number: CN113026067A
Application number: CN202110240731.3A
Authority: CN
Inventors: 姚玉; 陈建龙; 王江锋
Original assignee: Zhuhai Chuangzhixin Technology Co ltd
Current assignee: Zhuhai Chuangzhixin Technology Co ltd
Priority date: 2021-03-04
Filing date: 2021-03-04
Publication date: 2021-06-25

Abstract

The invention relates to an electroplating solution and an electroplating process for wafer level packaging, belonging to the technical field of materials; comprises the following components: 75g/L of copper methylsulfonate; 220g/L of methanesulfonic acid; chloride ion: 70 mg/L; accelerator: respectively adding a certain amount of sodium polydithio-dipropyl sulfonate and/or 3-mercapto-propane sulfonate into a methanesulfonic acid solution with the mass fraction of 5% to prepare an acidic solution of 0.5g/L of sodium polydithio-dipropyl sulfonate and/or 0.5g/L of 3-mercapto-propane sulfonate, and then respectively adding 0.02g of cuprous oxide; inhibitor (B): polyethylene glycol with molecular mass of 8000 and 10000 and polypropylene glycol 200 mg/L; leveling agent: 5ml/l of quaternary ammonium compound or nitrogen-containing heterocyclic compound. The invention also provides a novel filling process, which provides guidance for subsequent electroplating.

Description

Electroplating solution and electroplating process for wafer level packaging

Technical Field

The invention belongs to the technical field of materials, and particularly relates to an electroplating solution and an electroplating process for wafer-level packaging.

Background

In order to reduce the feature size and solve the problems of interconnection delay, the three-dimensional integration technology is beginning to become a research hotspot in the field of packaging, wherein the TSV technology is the mainstream and is also known as the fourth generation packaging technology. In the TSV technology, the filling quality of the silicon hole directly affects the performance of the three-dimensional packaged chip. In the silicon hole filling process, the formation of voids (Void) or gaps (team) can cause serious reliability problems of the three-dimensional packaged chip.

The filling of the silicon hole mainly comprises the implementation of insulating layer deposition, diffusion barrier layer deposition, seed layer deposition and interconnection conductive line in the hole, wherein the implementation method of the conductive layer in the hole has various methods. Electroplating has been developed as the first choice of deposition technology in the semiconductor industry because of its low cost and suitability for mass production.

Disclosure of Invention

The present invention is directed to an electroplating solution and an electroplating process for wafer level packaging, so as to solve the above-mentioned technical problems in the background art.

In order to achieve the purpose, the specific technical scheme of the electroplating solution and the electroplating process for wafer level packaging is as follows:

an electroplating solution for wafer level packaging comprises the following components:

copper salt: 70-80g/L of copper methylsulfonate;

acid: 200-250g/L of methanesulfonic acid;

chloride ion: 60-80 mg/L;

accelerator: adding a certain amount of sodium polydithio-dipropyl sulfonate (SPS) and/or sodium 3-mercaptopropane sulfonate (MPS) into a methanesulfonic acid solution with the mass fraction of 5% respectively to prepare an acidic solution of 0.5g/L of sodium polydithio-dipropyl sulfonate and/or 0.5g/L of sodium 3-mercaptopropane sulfonate, and then adding 0.02g of cuprous oxide respectively, wherein the acidic solution is used because the cuprous oxide cannot be dissolved in neutral SPS or MPS but can be dissolved in the acidic solution, and the mass of Cu (I) is the mass of monovalent copper which is supposed that the cuprous oxide is dissolved and does not undergo disproportionation or oxidation reaction.

Inhibitor (B): polyethylene glycol (PEG8000 and PEG10000) with molecular mass of 8000 and 10000 and polypropylene glycol (PPG)150-250 mg/L;

leveling agent: 2-8ml/l of quaternary ammonium compound or nitrogen-containing heterocyclic compound.

Further, the inhibitor may be at least one selected from ethylene oxide-polypropylene oxide-polyethylene oxide triblock copolymer (EPE), polyvinylpyrrolidone (PVP), polyalkylene glycol compound, polyvinyl alcohol, carboxymethyl cellulose, stearic acid polyethylene glycol, alkoxy tea phenol, oleic acid polyethylene glycol, and polyethylene glycol-propylene glycol random copolymer.

Further, the leveling agent may be selected from at least one of Janus Green (JGB), JGB derivative Diazine Black (DB), Aniline Red (ST), Dodecyl Trimethyl Ammonium Chloride (DTAC), condensed epichlorohydrin and Imidazole (IMEP), and Alsinoblue-tetra (methylpyridine) chloride (BPV).

The invention also provides an electroplating process for wafer level packaging, which comprises the following steps in sequence:

step S1: processing a TSV blind hole on one surface of the substrate by an ICP (inductively coupled plasma) silicon hole etching process;

step S2: depositing an insulating layer on the surface of the substrate with the blind hole structure by a PECVD (plasma Enhanced Chemical Vapor deposition) process, and then sequentially depositing a barrier layer and a seed layer by a magnetron sputtering process;

step S3: the surface containing the seed layer is coated with photoresist uniformly, so that the blind holes are fully filled with the photoresist;

step S4: exposing and developing the silicon wafer containing the photoresist to enable the photoresist to be only remained at the bottom of the blind hole;

step S5: etching the seed layer exposed in the blind hole by using an etching process;

step S6: removing the residual photoresist in the blind hole to enable the residual seed layer at the bottom to emerge;

step S7: and the seed layer at the bottom of the blind hole is used as a guiding medium to realize the growth of the filling metal from bottom to top.

Further, after the photoresist throwing step in step S3, a vacuum standing step is added, that is, the TSV silicon wafer containing the photoresist is placed in a vacuum chamber with a vacuum degree of 0 to minus one atmosphere for ten minutes, so that the gas in the blind holes is smoothly discharged and the photoresist can fully fill the blind holes.

The electroplating solution and the electroplating process for wafer level packaging have the following advantages: a novel bottom-up electroplating process realizes bottom-up growth and pore-free filling in silicon blind holes.

Drawings

FIG. 1 morphology of the metal layer on the surface of the silicon wafer before electroplating and a cross-sectional side view of the wafer in example 1.

FIG. 2 is a cross-sectional side view and the topography of the metal layer on the surface of the silicon wafer after electroplating in example 1.

FIG. 3 is a graph of the profile of the photoresist inside the blind via and the photoresist thickness versus exposure time for example 1.

Fig. 4 shows the cross-sectional shapes of TSVs after the respective process steps in the pretreatment in example 1.

FIG. 5 shows the effect of Cu electroplating filling inside the blind via holes according to the change of electroplating time in example 1.

FIG. 6 shows the filling effect after electroplating according to the process of the present invention in example 1.

Detailed Description

For better understanding of the objects, structure and functions of the present invention, the electroplating solution and electroplating process for wafer level packaging according to the present invention will be described in detail with reference to the accompanying drawings.

Example 1:

the specification of the adopted silicon wafer is 2 inches in size, 100 metallographic phases and 380 mu m in thickness, the thickness of the insulating layer SiO2 is 500nm, the thickness of the barrier layer Ti is 200nm, the thickness of the seed layer Cu is 1 mu m, the size of the blind hole is 30 mu m in diameter and 112 mu m in depth, the working condition and parameters of the electroplating solution are detailed below, and a vacuum wetting mode is adopted.

Copper salt: 75g/L copper methylsulfonate

Acid: methanesulfonic acid 220g/L

Chloride ion: 70mg/L

Accelerator: adding a certain amount of sodium polydithio-dipropyl sulfonate (SPS) into a methanesulfonic acid solution with the mass fraction of 5% respectively to prepare an acidic solution of 0.5g/L sodium polydithio-dipropyl sulfonate, and then adding 0.02g of cuprous oxide.

Inhibitor (B): 200mg/L of polyethylene glycol (PEG8000 and PEG10000) with molecular mass of 8000 and 10000;

leveling agent: 5ml/l of quaternary amine compound;

of this experimentThe electroplating environment adopts electroplating solution and additives in TSV blind hole electroplating, the volume of the electroplating solution is 1000ml, the temperature of the electroplating solution is controlled at 25 ℃, and the magnetic stirring speed is 360 r/min. The silicon wafer used in the experimental process was 2 inches in size, 100 metallographic phases, 380 μm thick. Firstly, a layer of SiO with a thickness of 500nm is grown on the surface of a polished silicon wafer by using a PECVD (plasma Enhanced Chemical Vapor deposition) process₂(as an insulating layer). Then adopting a magnetron sputtering mode to form a layer of SiO₂A layer of 200nm thick Ti (as a barrier layer) was sputtered on the layer. Then, half of the Ti layer was subjected to a masking treatment, and sputtering of a layer of Cu 1 μm thick (as a seed layer) was continued on the exposed Ti layer. FIG. 1 shows the topography and cross-sectional side view of a metal layer on the surface of a processed silicon wafer. Wherein the left picture is a top view, the left area of the surface of the silicon chip is metal Ti, and the right area of the surface of the silicon chip is metal Cu. The right side view is a cross-sectional side view, and it can be observed that a layer of metal with a thickness of 1 μm is attached to the right side surface of the silicon wafer, and no metal layer is attached to the left side surface. Therefore, metal Ti is attached to the entire upper surface of the silicon wafer, and metal Cu is attached to only a half area of the surface of the metal Ti layer.

Then, a metal Ti is used as a conductive medium, and a cathode electrode is loaded on the conductive medium to carry out an electroplating experiment. The plating current density was 0.1ASD and the plating time was 60 minutes. FIG. 2 shows the topography of the metal layer on the surface of the silicon wafer after the electroplating experiment and a cross-sectional side view. The left picture is a top view, a metal Ti area on the left side of the surface of the silicon wafer is not deposited with metal Cu, a new layer of metal Cu is deposited on a metal Cu area on the right side, and the surface color and the density of the metal Cu are changed. The right side view is a cross-sectional side view, and it can be observed that the thickness of the metal layer on the right side surface is increased to 4.3 μm, the longitudinal growth rate is 3.3 μm/h, and no metal layer is formed on the left side surface.

From the above experimental results, it can be understood that although the plating cathode is loaded on the metal Ti layer, the resistivity due to the metal Ti is 4.2X 10^-8Omega.m, good conductivity, and good conductivity of electroplating current of the electroplating system. Thus, metal ions in the plating solution can be smoothly deposited on the seed layer Cu. Although the entire plating coupon was in the plating solution,but no metal layer is deposited on the metal Ti. The reason for this may be as follows: (1) metal ion Cu in electroplating solution²⁺The metal layer is selective during deposition, namely the metal layer grows only on the seed layer Cu and does not grow on the barrier layer Ti; (2) metal ion Cu in electroplating solution²⁺Also on the barrier layer Ti during deposition, but at a very low growth rate. Because the main salt of the electroplating solution is a methanesulfonic acid solution (with certain acidity), the electroplating solution has certain corrosivity on metal Cu. When the corrosion rate is greater than or equal to the growth rate of the metal Cu on the metal layer Ti, no metal layer Cu is deposited on the metal layer Ti. In order to verify the influence of the main salt of the acidic electroplating solution on the Cu metal of the plating layer, the following supplementary experiment is carried out: and immersing the silicon wafer sputtered with the Ti and Cu metal layers into the electroplating solution for standing. After half an hour, slight corrosion phenomenon appears on the surface of the metal Cu layer; after 4 hours, the 1 μm thick metallic Cu was completely etched away. This additional experiment shows that the acidic plating solution is somewhat corrosive to metallic Cu, with a longitudinal corrosion rate of 0.25 μm/h. The corrosion rate of the plating metal by the main salt of the plating solution is low compared to the normal plating deposition rate.

The experimental result shows that the electroplating cathode is loaded on the barrier layer Ti, and the electroplating experiment is feasible by taking the barrier layer Ti metal as a conductive medium, namely, the metal ion Cu in the electroplating solution²⁺Can still be deposited on the seed layer Cu smoothly; meanwhile, on the barrier layer Ti, the growth rate of the metal Cu is negligible. Thus, the metal ion Cu in the plating solution²⁺The growth difference between the Ti metal layer and the Cu metal layer is obvious. Since the plating solution of this experiment contains additives and the inhibitor has a large influence on the plating rate of the surface of the sample, the deposition rate of metallic Cu is low. However, when electroplating the silicon via from the bottom to the top, metal grows from the bottom of the blind via, the growth rate of the filling material at the bottom of the blind via becomes faster due to the influence of the accelerator, and the inhibitor has a weaker influence on the metal deposition at the bottom of the blind via. Thus, a new process of electroplating based on the barrier layer Ti as a conductive medium is feasible and process efficiency can be ensured.

And after the silicon wafer containing the TSV structure is metallized, carrying out glue homogenizing process treatment on the substrate, and selecting corresponding exposure time to be 40s and developing time to be 5min according to the specification of the TSV. Firstly, the cleaned bare silicon wafer is subjected to glue homogenizing and photoetching, and the pattern on the mask plate is copied to the photoresist. And etching silicon blind holes by using photoresist with a graphic structure as a mask through an ICP (inductively coupled plasma) process, wherein the size of the blind holes is 30 micrometers in diameter, 90 micrometers in depth and the aspect ratio is 3: 1. And finally, carrying out glue homogenizing on the silicon wafer containing the TSV structure. The conventional photoresist homogenizing process is to dry directly after photoresist throwing to remove the excessive solvent in the photoresist, solidify the photoresist and enhance the viscosity of the photoresist and the substrate. However, the TSV blind hole has a large aspect ratio, and photoresist is not easy to enter the blind hole, so that gas is remained in the blind hole. Therefore, in the experiment, after the photoresist throwing step, a vacuum standing step is added, namely, the TSV silicon wafer containing the photoresist is placed in a vacuum box with the vacuum degree of 0 to minus one atmosphere for ten minutes, so that the gas in the blind holes can be smoothly discharged, and the photoresist can be fully filled in the blind holes. The lower the viscosity and the better the fluidity of the photoresist, the easier the photoresist will enter the blind via. And after the air standing step, drying treatment is carried out. Then, exposure and development are performed. Because the experimental assumption is that the photoresist is only reserved in the blind hole, and the photoresist on the surface of the silicon wafer is not needed, the sample wafer can be directly placed in an exposure environment in the whole exposure process, an alignment process is not needed, and the process is simple. The experiment hopes that the photoresist can completely fill the blind holes, and other parameters such as the appearance of the surface of the sample wafer, the thickness of the photoresist and the like do not have too much requirements, so that the photoresist used in the experiment is PR1-1000A, and the photoresist has low viscosity and good fluidity.

FIG. 3 shows the profile of the photoresist filled blind via interior and the photoresist thickness versus exposure time curve. Wherein, the graph (a) is the appearance of the photoresist in the blind hole after the photoresist is homogenized and before the photoresist is exposed, and the depth of the blind hole is 90 μm. The gas inside the blind hole is removed and no bubbles exist. The photoresist can be completely filled in the blind holes by the photoresist homogenizing process; FIG. b shows the photoresist remaining inside the blind via holes after exposure for 40s, with different development times. When the developing time was 1 minute, the residual photoresist thickness inside the blind via was 56 μm. With further increase of the exposure time to 1.5 min, 2 min and 2.5 min, the photoresist inside the blind holes was further removed with corresponding residual thicknesses of 47 μm, 39 μm and 33 μm, respectively. Graph (c) is a plot of residual photoresist thickness in the blind hole versus exposure time. The thickness of the photoresist inside the initial blind hole, namely the depth of the blind hole, is 90 μm; in the early development stage, the removal rate of the residual photoresist in the blind hole is higher along with the increase of the development time; in the later development stage, the removal rate of the residual photoresist inside the blind hole starts to slow down along with the increase of the development time.

Experimental results show that after the photoresist homogenizing process (glue dripping, glue throwing, vacuum and drying) is adopted, gas in the silicon blind holes can be completely discharged, no bubbles exist, and photoresist can be ensured to fully enter the blind holes. After exposure and development, the thickness value of the residual photoresist in the blind hole is correspondingly reduced along with the increase of the development time, meanwhile, the photoresist at the upper part in the blind hole can be completely removed, and only the photoresist at the lower part in the blind hole is left. Therefore, for the silicon chip with the TSV structure, the photoresist can be completely filled in the silicon hole by changing the photoresist homogenizing process; meanwhile, the photoresist only remains at the bottom of the blind hole and the residual photoresist with a specific thickness value can be obtained by controlling the exposure and development time.

After the above experimental operation, the photoresist was present only in the bottom region of the blind via, and the upper portion of the blind via and the seed layer on the surface of the silicon wafer were not covered with the photoresist. Then, H is used₂O₂And carrying out a wet etching process by using HCl solution to etch the exposed Cu seed layer, wherein the seed layer at the bottom of the blind hole is protected by the photoresist. And then removing the residual photoresist in the blind holes by using acetone to enable the residual seed layer at the bottom to emerge. After each step, the corresponding TSV cross-sectional profile is shown in fig. 4. Wherein, the figure (a) is the appearance of the blind hole after photoetching and developing. The yellow area at the middle upper part of the blind hole is a metal layer Cu, the gray area at the bottom of the blind hole is residual photoresist, and the thickness of the photoresist is 20 micrometers; and (b) is the appearance of the blind hole after wet etching of the metal Cu. The exposed seed layer is completely etched, and a gray area at the middle upper part of the blind hole is made of metal Ti; FIG. (c) shows the removal of residuesAnd (4) keeping the appearance of the blind hole after the photoresist is left. The seed layer Cu only remains at the bottom of the blind hole. Meanwhile, obvious etching stripes exist in the silicon holes after ICP etching, and the smooth degree of the inner wall of the blind hole is not high; and (d) is an enlarged view of the blind via morphology and blind via bottom under SEM.

After the treatment, the metal layer structure with the seed layer Cu only existing at the bottom of the blind hole is obtained. And then, loading an electroplating cathode electrode on a barrier layer Ti on the surface of the silicon wafer, and carrying out an electroplating experiment by using metal Ti as a conductive medium, wherein the current density is 0.1 ASD. FIG. 5 shows the change of the metal Cu electroplating filling effect in the blind via hole along with the electroplating time. Wherein, the pattern (a) is the filling morphology inside the blind hole at different time points of electroplating. The initial thickness of the metallic Cu layer was 1 μm and was manufactured by a magnetron sputtering process. After 0.5h, 3h, 7h, 12h and 14h of electroplating, the thickness of the metallic Cu layer deposited inside the blind via holes became 6.6 μm, 33.6 μm, 69.4 μm, 108.8 μm and 120 μm, respectively. Initially, the plating fill rate exceeds 11 μm/h; the electroplating speed is gradually reduced along with the progress of the electroplating experiment; at the final stage, the plating rate was reduced to 5.6 μm/h. The plating rate variation is due to the acceleration of the accelerator in the plating solution to the bottom of the blind via and the suppression of the inhibitor to the top of the blind via. With the progress of the electroplating experiment, the blind holes are gradually filled with metal Cu, and the grooves in the blind holes are shallower, so that the influence of the accelerator on the deposition rate of the filling metal is gradually weakened (the inhibition effect of the flattening agent on the accelerator is gradually strengthened) and the influence of the inhibitor is gradually strengthened. The average plating rate throughout the experiment was 8.6 μm/h. Graph (b) is a plot of the thickness of the metal layer deposited in the blind via versus plating time. The plating rate gradually decreases during the whole plating process.

FIG. 6 shows the fill effect after electroplating using the present process. Wherein the right picture is a metallographic microscopic picture after electroplating, the blind hole array on the silicon wafer has good filling consistency, and pore-free filling is realized in each hole. The left picture is an X-Ray scanning picture which has good integral uniformity, reflects the integral characteristic of the electroplating process and can be applied to large-batch TSV blind hole electroplating.

In the silicon wafer adopted in the research, etching stripes caused by an ICP (inductively coupled plasma) process are arranged at the opening of the blind hole and at the bottom of the blind hole, but the electroplating filling of the blind hole is not influenced, so that the quality requirement on the side wall is reduced when the blind hole is filled in a bottom-up growth mode, and the cost of the etching process can be further reduced.

Most of the traditional blind hole filling modes are conformal electroplating, or special electroplating additives are adopted to inhibit the growth of the side wall of the blind hole and accelerate the filling speed of the bottom to realize the bottom-up growth in the blind hole. However, this filling method cannot achieve ideal conditions for the suppression of the sidewall and the acceleration of the bottom, and can only be approximated. Meanwhile, the cost of the electroplating solution is high, and the electroplating current density is not easy to control. Therefore, the electroplating effect cannot be ensured, and the process cost is high. In the traditional through hole bottom-up filling process, bonding and bonding removing steps need to be introduced, so that the process complexity is increased, the process flow is prolonged, and the manufacturing cost is increased. Meanwhile, the process requirement for etching through the silicon wafer increases the etching time and the process cost.

The experimental results show that the novel bottom-up electroplating filling process provided in the embodiment is feasible. The bottom-up growth of metal in the blind hole can be realized in the blind hole, the pore-free filling is realized, and the defect that the internal defect is easy to generate when the blind hole is subjected to conformal electroplating is overcome. Although partial process flows (glue homogenizing and etching) are added, the process is simple, and steps such as bonding and the like are not needed, so that the process cost can be effectively controlled. Because the seed layer Cu on the surface of the silicon wafer is removed in the wet etching step, and the electroplated metal ions cannot grow on the surface barrier layer Ti, a plating solution metal layer cannot cover the whole surface of the silicon wafer after electroplating, and grinding and polishing processes such as CMP can be avoided.

It is to be understood that the present invention has been described with reference to certain embodiments, and that various changes in the features and embodiments, or equivalent substitutions may be made therein by those skilled in the art without departing from the spirit and scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims

1. An electroplating solution for wafer level packaging is characterized by comprising the following components:

copper salt: 70-80g/L of copper methylsulfonate;

acid: 200-250g/L of methanesulfonic acid;

chloride ion: 60-80 mg/L;

accelerator: respectively adding a certain amount of sodium polydithio-dipropyl sulfonate and/or 3-mercapto-propane sulfonate into a methanesulfonic acid solution with the mass fraction of 5% to prepare an acidic solution of 0.5g/L of sodium polydithio-dipropyl sulfonate and/or 0.5g/L of 3-mercapto-propane sulfonate, and then respectively adding 0.02g of cuprous oxide;

inhibitor (B): polyethylene glycol with molecular mass of 8000 and 10000 and polypropylene glycol 150-;

2. The electroplating solution for wafer level packaging according to claim 1, wherein the inhibitor is at least one selected from ethylene oxide-polypropylene oxide-polyethylene oxide triblock copolymer, polyvinylpyrrolidone, polyalkylene glycol compound, polyvinyl alcohol, carboxymethyl cellulose, stearic acid polyethylene glycol, alkoxy tea phenol, oleic acid polyethylene glycol, and polyethylene glycol-propylene glycol random copolymer.

3. The electroplating solution for wafer level packaging according to claim 1, wherein the leveling agent is further selected from at least one of Janus Green, JGB derivative dioxazine Black, aniline Red, dodecyl trimethyl ammonium chloride, condensed epichlorohydrin, and chloride of imidazole and Alcian blue-tetra (methylpyridine).

4. An electroplating process for wafer level packaging is characterized by comprising the following steps which are carried out in sequence:

5. The electroplating process for wafer level packaging according to claim 4, wherein a vacuum standing step is added after the photoresist throwing step in step S3, that is, the TSV silicon wafer containing the photoresist is placed in a vacuum box with a vacuum degree of 0 to minus one atmosphere for ten minutes, so that the gas in the blind holes can be smoothly exhausted and the photoresist can fully fill the blind holes.