CN113014357A - Data encoding method, data encoding device, and storage medium - Google Patents
Data encoding method, data encoding device, and storage medium Download PDFInfo
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Abstract
The invention provides a data encoding method, a data encoding device and a storage medium. The data encoding method includes: acquiring a first bit stream of original coded data; performing a first logic operation according to the first bit stream to obtain a second bit stream comprising a parity bit stream; judging whether the logic values of a plurality of continuous preset bits in the target bit stream are the same or not, if so, inverting the logic value of a first target bit in the target bit stream to be used as the logic value of a first bit of the target bit stream, and inverting the logic value of a second target bit in the target bit stream to be used as a second bit of the target bit stream to obtain encoded data; otherwise, the logic value of the first target bit in the target bit stream is inverted to be used as the first bit of the target bit stream to obtain the coded data. The invention can avoid error code, simplify coding process, reduce coding calculation amount and calculation difficulty, and reduce operation load of display device.
Description
Technical Field
The present invention relates to the field of display, and in particular, to a data encoding method, a data encoding apparatus, and a storage medium.
Background
In a display product, when a digital signal is transmitted in a digital channel, the transmitted digital signal needs to be encoded firstly and transmitted in a baseband manner, and because an independent clock signal does not exist in the data transmission process, the transmitted data needs to be encoded in order to avoid the occurrence of error codes caused by excessive continuous 0 or 1 in the transmitted data.
In the research and practice process of the prior art, the inventor of the present application finds that the existing data encoding technology usually performs logical operations on all bit data in one data packet or performs different logical operations on bit data at different positions, the encoding process is complicated, the calculation amount and the calculation difficulty are large, and the operation burden of the display device is increased.
Therefore, a data encoding method, a data encoding apparatus and a storage medium are needed to solve the above technical problems.
Disclosure of Invention
The invention provides a data encoding method, a data encoding device and a storage medium, which are used for solving the problem that the operation burden of a display device is increased due to the fact that the encoding process of the existing data encoding method is complicated and the calculated amount and the calculated difficulty are large.
In order to solve the technical problems, the technical scheme provided by the invention is as follows:
the embodiment of the invention provides a data encoding method, which comprises the following steps:
acquiring a first bit stream of original coded data;
performing a first logic operation according to the first bit stream to obtain a second bit stream, wherein the second bit stream comprises a benchmarking bit stream; and
judging whether the logic values of a plurality of continuous preset bits in the benchmarking bit stream are the same or not, if so, taking the logic value of a first target bit in the benchmarking bit stream as the logic value of the first bit of the target bit stream after being inverted, and taking the logic value of a second target bit in the benchmarking bit stream as the second bit of the target bit stream after being inverted so as to obtain encoded data; otherwise, inverting the logic value of the first target bit in the opposite standard bit stream to be used as the first bit of the target bit stream to obtain the coded data;
wherein the number of bits of the target bit stream is greater than the number of bits of the target bit stream, the number of bits in the target bit stream having the same logical value and being continuous is less than X, and the values of the preset bits are X, where X >2 and is an integer.
In an embodiment, the performing the first logical operation according to the first bit stream to obtain a second bit stream, where the second bit stream includes a bitstream, includes:
the first bit stream includes a pre-marked bit stream, and a plurality of consecutive preset bits of the pre-marked bit stream are arranged in a reverse order to obtain the marked bit stream.
In an embodiment, the pre-marked bitstream is three-bit data, the marked bitstream is three-bit data, and the step of arranging a plurality of consecutive preset bits of the pre-marked bitstream in a reverse order to obtain the marked bitstream includes:
assigning a logic value of a first bit of the pre-scalar bitstream to a logic value of a third bit of the pair-scalar bitstream;
assigning a logical value of a second bit of the pre-scalar bitstream to a logical value of a second bit of the pair-scalar bitstream;
the logic value of the third bit of the pre-scalar bitstream is assigned to the logic value of the first bit of the pair-scalar bitstream.
In an embodiment, the step of determining whether the logical values of a plurality of consecutive preset bits in the bitstream are the same includes:
performing second logic operation on logic values of a plurality of continuous preset bits in the pair of standard bit streams to obtain a first operation result;
performing third logical operation on the logical values of a plurality of continuous preset bits in the pair of standard bit streams to obtain a second operation result;
performing logical NAND operation on the first operation result and the second operation result to obtain a third operation result;
when the third operation result is 1, the logical values of a plurality of continuous preset bits in the pair standard bit stream are the same, and when the third operation result is 0, the logical values of a plurality of continuous preset bits in the pair standard bit stream are different;
the second logical operation is a logical nand operation, and the third logical operation is a logical or operation; or
The second logical operation is a logical OR operation and the third logical operation is a logical NAND operation.
In an embodiment, the step of inverting the logic value of a first target bit in the bitstream to obtain a first bit of the target bitstream and inverting the logic value of a second target bit in the bitstream to obtain a second bit of the target bitstream to obtain encoded data includes:
the logical value of the first target bit in the target bit stream is inverted to be used as the logical value of the first bit of the target bit stream;
the logical value of the first bit in the target bit stream is used as the logical value of the second bit of the target bit stream after being inverted;
the logic value of the Nth bit in the pair target bit stream is used as the logic value of the (N +1) th bit of the target bit stream;
n is a positive integer greater than 1.
In an embodiment, the step of inverting the logic value of the first target bit in the bitstream to obtain the encoded data as the logic value of the first bit of the target bitstream includes:
inverting the logic value of the first target bit in the opposite-sign bit stream to be used as the logic value of the first bit of the target bit stream;
taking a logical value of an Mth bit in the bitstream as a logical value of an (M +1) th bit in the target bitstream;
m is a positive integer greater than or equal to 1.
In an embodiment, the data encoding method further includes:
and the first bit stream or the second bit stream obtains the logic value of a fourth target bit positioned outside the target bit stream in the third bit stream according to a fourth logic operation.
In an embodiment, the step of obtaining, by the first bitstream or the second bitstream, a logic value of a fourth target bit, located outside the target bitstream, in the third bitstream according to a fourth logic operation includes:
the first bit stream comprises a fifth target bit positioned outside a preset bit stream, and the number of the fourth target bit corresponding to the fifth target bit in the third bit stream is determined according to the number of the fifth target bit in the first bit stream, the number of the preset bit stream in the first bit stream and the number of segments of the preset bit stream in the first bit stream;
and assigning the logic value of the fifth target bit to the logic value of the corresponding fourth target bit in the third bit stream.
An embodiment of the present invention further provides a data encoding apparatus, including a controller and a memory, where the memory is used to store program instructions, and the controller is used to execute the program instructions to implement the method described above.
An embodiment of the present invention further provides a storage medium, which includes a plurality of instructions stored in the storage medium, where the instructions are suitable for being loaded by a processor to perform the steps in the data encoding method.
Has the advantages that: the invention can avoid error code, simplify coding process, reduce coding calculation amount and calculation difficulty, and reduce operation load of display device.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic diagram of a data encoding method according to the present invention.
FIG. 2 is a schematic structural diagram of a data encoding apparatus according to the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The existing data coding method has the problems of complicated coding flow, large calculation amount and difficulty, and increased operation burden of a display device. Based on this, the present application proposes a data encoding method, a data encoding device, and a storage medium.
Referring to fig. 1, the data encoding method includes:
s100, acquiring a first bit stream of the original coded data.
In this embodiment, the data length of the first bit stream may be 8 bits or other lengths, and is not limited specifically herein.
When the length of the first bit stream is 8 bits, the first bit stream can be represented as Ori [7] Ori [6] Ori [5] Ori [4] Ori [3] Ori [2] Ori [1] Ori [0], i.e., Ori [ 7-0 ], when the first bit stream is arranged in the order from right to left according to the precedence order.
S200, performing a first logic operation according to the first bit stream to obtain a second bit stream, wherein the second bit stream comprises a benchmarking bit stream.
In this embodiment, step S200 may include:
s210, the first bit stream includes a pre-marked bit stream, and a plurality of consecutive preset bits of the pre-marked bit stream are arranged in a reverse order to obtain the marked bit stream.
In this embodiment, the pre-standard bit stream may be three bits of data, and the pair-standard bit stream may be three bits of data.
When the pre-marked bitstream is three-bit data and the marked bitstream is three-bit data, step S210 may include:
and S211, assigning the logic value of the first bit of the pre-standard bit stream as the logic value of the third bit of the pair-standard bit stream.
And S212, assigning the logic value of the second bit of the pre-standard bit stream as the logic value of the second bit of the pair-standard bit stream.
And S213, assigning the logic value of the third bit of the pre-standard bit stream as the logic value of the first bit of the pair-standard bit stream.
In this embodiment, when the length of the first bit stream is 8 bits and the length of the pre-marked bit stream is 3, the pre-marked bit stream in the first bit stream may have two segments; the corresponding pair of label bit streams is also two segments.
For example: the pre-standard bit stream can be Ori [ 7-5 ] and Ori [ 3-1 ], when the length of the second bit stream is 8 bits, it can be represented as B [ 0-7 ], and the corresponding standard bit stream can be B [ 7-5 ] and B [ 3-1 ].
Taking the pre-standard bit stream Ori [ 7-5 ] as an example, the logic expression from step S211 to step S213 may be:
ori [7] ═ B [5 ]; (the logical value of the 8 th bit of the first bitstream is assigned to the logical value of the 6 th bit of the second bitstream)
Ori [6] ═ B [6 ]; (the logical value of the 7 th bit of the first bitstream is assigned to the logical value of the 7 th bit of the second bitstream)
Ori [5] ═ B [7 ]; (the logical value of the 6 th bit of the first bitstream is assigned to the logical value of the 8 th bit of the second bitstream)
Or, the second bitstream is only composed of the bitstream, and in this case, when the bitstream in the first bitstream is two segments, the two segments may correspond to the second bitstream, respectively.
In this embodiment, step S200 may further include:
and S220, obtaining a logic value of a third target bit positioned outside the alignment mark bit stream in the second bit stream according to a second logic operation by the first bit stream.
Step S220 may be performed before step S210, after step S210, or simultaneously with step S210, in which case step S220 may include:
s221, the first bit stream includes a fifth target bit except the preset bit stream, and the logic value of the fifth target bit is assigned to the third target bit corresponding to the number of bits of the fifth target bit.
For example: when the pre-standard bit stream is Ori [ 7-5 ] and Ori [ 3-1 ], the target bit stream is B [ 7-5 ] and B [ 3-1 ], and the fifth target bit can be Ori [4] and Ori [0], then, the logical value of Ori [4] is assigned as B [4], and the logical value of Ori [0] is assigned as B [0 ].
S300, judging whether the logic values of a plurality of continuous preset bits in the benchmarking bit stream are the same, if so, executing the step S400, otherwise, executing the step S500.
In this embodiment, the number of bits of the target bit stream is greater than the number of bits of the target bit stream, the number of consecutive bits having the same logic value in the target bit stream is less than X, and the values of the preset bits are X, where X >2 and is an integer.
In this embodiment, step S300 may include:
s310, carrying out second logic operation on the logic values of the continuous preset bits in the pair standard bit stream to obtain a first operation result.
And S320, performing third logical operation on the logical values of the continuous preset bits in the pair of standard bit streams to obtain a second operation result.
S330, performing logical NAND operation on the first operation result and the second operation result to obtain a third operation result.
S340, when the third operation result is 1, the logical values of the consecutive preset bits in the pair standard bit stream are the same, and when the third operation result is 0, the logical values of the consecutive preset bits in the pair standard bit stream are different.
Wherein the second logical operation is a logical nand operation and the third logical operation is a logical or operation.
Alternatively, the second logical operation is a logical or operation, and the third logical operation is a logical nand operation.
For example: when the bitstream is B [ 7-5 ], the logic expression for determining whether the logic values of a plurality of consecutive preset bits in the bitstream are the same may be:
NAND (NAND (B2: 0), OR (B2: 0)) wherein when all B7 to B5 are 1 OR 0, NAND (NAND (B2: 0), OR (B2: 0)) is 1; when all B7-5 are 1 OR 0, NAND (B2: 0, OR (B2: 0)) is 0.
And S400, if the two bit values are the same, inverting the logic value of the first target bit in the benchmarking bit stream to be used as the logic value of the first bit of the target bit stream, and inverting the logic value of the second target bit in the benchmarking bit stream to be used as the second bit of the target bit stream to obtain the coded data.
In this embodiment, step S400 may include:
s410, taking the logic value of the first target bit in the target bit stream as the logic value of the first bit of the target bit stream after inverting the logic value of the first target bit in the target bit stream.
For example: the bitstream is B [ 3-1 ], and when the first target bit is the first bit in the bitstream, the logic expression of step S410 may be:
B[1]＝～En[1]。
and S420, taking the logic value of the first bit in the target bit stream as the logic value of the second bit of the target bit stream after inverting the logic value of the first bit.
In this embodiment, the first target bit and the second target bit may be the same or different, and the second target bit is the first bit in the pair standard bit stream.
For example: the bitstream is denoted as B [ 3-1 ], and the logic expression of step S420 may be:
B[1]＝～En[2]。
and S430, taking the logic value of the Nth bit in the pair standard bit stream as the logic value of the (N +1) th bit of the target bit stream.
Wherein N is a positive integer greater than 1.
For example: and if the pair-mark bit stream is 3-bit data and the target bit stream is 4-bit data, the logic value of the second bit in the pair-mark bit stream is used as the logic value of the third bit in the target bit stream, and the logic value of the third bit in the pair-mark bit stream is used as the logic value of the fourth bit in the target bit stream.
When the bitstream is denoted as B [ 3-1 ], the logic expression of step S400 may be:
B[1]＝～En[1]；
B[1]＝～En[2]；
B[2]＝En[3]；
B[3]＝En[4]。
in this embodiment, step S430 may be performed before step S410, and in this case, when the pair target bitstream is represented by B [ 3-1 ], the logic expression of step S400 may be:
B[2]＝En[3]；
B[3]＝En[4]；
B[1]＝～En[1]；
B[1]＝～En[2]。
s500, if not, inverting the logic value of the first target bit in the opposite standard bit stream to be used as the first bit of the target bit stream to obtain the coded data.
In this embodiment, step S500 may include:
s510, inverting the logic value of the first target bit in the bitstream to obtain the logic value of the first bit of the target bitstream.
In this embodiment, the bitstream is B [ 3-1 ], and when the first target bit is the first bit in the bitstream, the logic expression of step S410 may be:
B[1]＝～En[1]。
s520, taking the logic value of the Mth bit in the benchmarking bit stream as the logic value of the (M +1) th bit in the target bit stream.
Wherein M is a positive integer greater than or equal to 1.
In this embodiment, since the logic value of the first bit of the pair-labeled bitstream can be directly assigned as the logic value of the second bit of the target bitstream, M is an integer greater than or equal to 1.
For example: and if the bitstream is 3-bit data and the target bitstream is 4-bit data, the logic value of the first bit in the bitstream is used as the logic value of the second bit in the target bitstream, the logic value of the second bit in the bitstream is used as the logic value of the third bit in the target bitstream, and the logic value of the third bit in the bitstream is used as the logic value of the fourth bit in the target bitstream.
When the bitstream is denoted as B [ 3-1 ], the logic expression of step S400 may be:
B[1]＝～En[1]；
B[1]＝En[2]；
B[2]＝En[3]；
B[3]＝En[4]。
in this embodiment, step S520 may be performed before step S510, and in this case, when the pair target bitstream is represented by B [ 3-1 ], the logic expression of step S500 may be:
B[2]＝En[3]；
B[3]＝En[4]；
B[1]＝～En[1]；
B[1]＝En[2]。
in this embodiment, the data encoding method further includes step S600:
and the first bit stream or the second bit stream obtains the logic value of a fourth target bit positioned outside the target bit stream in the third bit stream according to a fourth logic operation.
Step S600 may be performed before step S200 or step S300, before step S400 or step S500, or step S600 may be performed simultaneously with step S430 or step S520.
In this embodiment, the step of obtaining, by the third bitstream, a logical value of the fourth target bit in the third bitstream, which is located outside the target bitstream, according to the fourth logical operation by the first bitstream, may include:
s610, obtaining a logic value of a fourth target bit corresponding to the third bit stream according to the fourth logic operation by a fifth target bit outside the preset bit stream in the first bit stream.
Step S610 may include:
s611, determining, according to the number of bits of the fifth target bit in the first bit stream, the number of bits of the preset bit stream in the first bit stream, and the number of segments of the preset bit stream in the first bit stream, the number of bits of the fourth target bit in the third bit stream corresponding to the fifth target bit.
And S612, assigning the logic value of the fifth target bit to be the logic value of the corresponding fourth target bit in the third bit stream.
For example: when the first bitstream is 8-bit data, denoted as Ori [ 7-0 ], the pre-scaled bitstream is Ori [ 7-5 ] and Ori [ 3-1 ], and the fifth target bit is Ori [0], the bit number of the fifth target bit in the first bitstream is a first bit, the bit number of the fourth target bit corresponding thereto is a first bit, denoted as En [0], and then Ori [0] ═ En [0 ]; when the fifth target bit is Ori [4], the number of bits in the first bit stream is 5, and since it is located between two pieces of the pre-scaled bit stream, the number of bits of the fourth target bit corresponding thereto is 6, which is denoted as En [5], and then Ori [4] ═ En [5 ].
In this embodiment, the step of obtaining, by the third bitstream through the second bitstream according to the fourth logical operation, a logical value of the fourth target bit in the third bitstream, which is located outside the target bitstream, may include:
s620, obtaining a logic value of a corresponding fourth target bit in the third bitstream according to the fourth logic operation by a sixth target bit outside the aligned bitstream in the second bitstream.
Step S620 may include:
s621, determining, according to the number of bits of the sixth target bit in the second bitstream, the number of bits of the second bitstream, and the number of segments of the second bitstream, the number of bits of the third bitstream of the fourth target bit corresponding to the sixth target bit.
S622, assigning the logic value of the sixth target bit to the logic value of the corresponding fourth target bit in the third bitstream.
For example: when the second bit stream is 8-bit data, denoted as B [ 7-0 ], the target bit stream is B [ 7-5 ] and B [ 3-1 ], and the sixth target bit is B [0], the bit number of the sixth target bit in the second bit stream is the first bit, the bit number of the corresponding fourth target bit is the first bit, denoted as En [0], and at this time, B [0] ═ En [0 ]; when the sixth target bit is B [4], the number of bits in the second bitstream is 5, and since it is located between two pieces of the pre-standard bitstream, the number of bits of the fourth target bit corresponding thereto is 6, which is denoted as En [5], and at this time, B [4] ═ En [5 ].
And when the data length of the first bit stream is 8 bits and the number of segments of the pre-standard bit stream is 2, the data length of the third bit stream is 10 bits.
In this embodiment, the data length of the first bit stream may be 8 bits or other lengths, the data length of the pre-scaled bit stream may be 3 bits or other data lengths smaller than or equal to the data length of the first bit stream, and the data length of the first bit stream and the data length of the pre-scaled bit stream may satisfy the following relation:
(number of pre-scalar bitstream segments +1) × length of pre-scalar bitstream ≧ first bitstream length ≧ number of pre-scalar bitstream segments ≧ length of pre-scalar bitstream.
In the embodiment, the pre-marked bit stream in the first bit stream of the original encoded data is encoded to avoid error codes, simplify the encoding process, reduce the calculation amount of encoding and the calculation difficulty, reduce the operation burden of the display device, and improve the product quality of the display device.
Referring to fig. 2, the present application also provides a data encoding apparatus 100, which includes a controller 10 and a memory 20, where the memory 20 is used for storing program instructions, and the controller 10 is used for executing the program instructions to implement the method as described above.
The present application also proposes a storage medium comprising a plurality of instructions stored thereon, which are suitable for being loaded by a processor to perform the steps of the data encoding method as described above.
The invention provides a data encoding method, a data encoding device and a storage medium. The data encoding method includes: acquiring a first bit stream of original coded data; performing a first logic operation according to the first bit stream to obtain a second bit stream comprising a parity bit stream; judging whether the logic values of a plurality of continuous preset bits in the target bit stream are the same or not, if so, inverting the logic value of a first target bit in the target bit stream to be used as the logic value of a first bit of the target bit stream, and inverting the logic value of a second target bit in the target bit stream to be used as a second bit of the target bit stream to obtain encoded data; otherwise, the logic value of the first target bit in the target bit stream is inverted to be used as the first bit of the target bit stream to obtain the coded data. The invention can avoid error code, simplify coding process, reduce coding calculation amount and calculation difficulty, and reduce operation load of display device.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The data encoding method, the data encoding apparatus and the storage medium provided by the embodiments of the present invention are described in detail above, and the principles and embodiments of the present invention are explained herein by applying specific embodiments, and the description of the embodiments is only used to help understanding the technical solutions and core ideas of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A method of encoding data, comprising:
acquiring a first bit stream of original coded data;
performing a first logic operation according to the first bit stream to obtain a second bit stream, wherein the second bit stream comprises a benchmarking bit stream; and
judging whether the logic values of a plurality of continuous preset bits in the benchmarking bit stream are the same or not, if so, taking the logic value of a first target bit in the benchmarking bit stream as the logic value of the first bit of the target bit stream after being inverted, and taking the logic value of a second target bit in the benchmarking bit stream as the second bit of the target bit stream after being inverted so as to obtain encoded data; otherwise, inverting the logic value of the first target bit in the opposite standard bit stream to be used as the first bit of the target bit stream to obtain the coded data;
wherein the number of bits of the target bit stream is greater than the number of bits of the target bit stream, the number of bits in the target bit stream having the same logical value and being continuous is less than X, and the values of the preset bits are X, where X >2 and is an integer.
2. The data encoding method of claim 1, wherein the step of performing the first logical operation according to the first bit stream to obtain a second bit stream, and wherein the second bit stream includes a parity bit stream comprises:
the first bit stream includes a pre-marked bit stream, and a plurality of consecutive preset bits of the pre-marked bit stream are arranged in a reverse order to obtain the marked bit stream.
3. The data encoding method according to claim 2, wherein the pre-standard bit stream is three-bit data, the target bit stream is three-bit data, and the step of arranging a plurality of consecutive preset bits of the pre-standard bit stream in a reverse order to obtain the target bit stream comprises:
assigning a logic value of a first bit of the pre-scalar bitstream to a logic value of a third bit of the pair-scalar bitstream;
assigning a logical value of a second bit of the pre-scalar bitstream to a logical value of a second bit of the pair-scalar bitstream;
the logic value of the third bit of the pre-scalar bitstream is assigned to the logic value of the first bit of the pair-scalar bitstream.
4. The data encoding method of claim 1, wherein the step of determining whether the logical values of the plurality of consecutive preset bits in the bitstream pair are the same comprises:
performing second logic operation on logic values of a plurality of continuous preset bits in the pair of standard bit streams to obtain a first operation result;
performing third logical operation on the logical values of a plurality of continuous preset bits in the pair of standard bit streams to obtain a second operation result;
performing logical NAND operation on the first operation result and the second operation result to obtain a third operation result;
when the third operation result is 1, the logical values of a plurality of continuous preset bits in the pair standard bit stream are the same, and when the third operation result is 0, the logical values of a plurality of continuous preset bits in the pair standard bit stream are different;
the second logical operation is a logical nand operation, and the third logical operation is a logical or operation; or
The second logical operation is a logical OR operation and the third logical operation is a logical NAND operation.
5. The data encoding method of claim 1, wherein the step of inverting the logical value of a first target bit in the bitstream as a first bit of the target bitstream and inverting the logical value of a second target bit in the bitstream as a second bit of the target bitstream to obtain encoded data comprises:
the logical value of the first target bit in the target bit stream is inverted to be used as the logical value of the first bit of the target bit stream;
the logical value of the first bit in the target bit stream is used as the logical value of the second bit of the target bit stream after being inverted;
the logic value of the Nth bit in the pair target bit stream is used as the logic value of the (N +1) th bit of the target bit stream;
n is a positive integer greater than 1.
6. The data encoding method according to claim 1, wherein the step of inverting the logical value of the first target bit in the bitstream as the logical value of the first bit of the target bitstream to obtain the encoded data comprises:
inverting the logic value of the first target bit in the opposite-sign bit stream to be used as the logic value of the first bit of the target bit stream;
taking a logical value of an Mth bit in the bitstream as a logical value of an (M +1) th bit in the target bitstream;
m is a positive integer greater than or equal to 1.
7. The data encoding method of any one of claims 2 to 6, further comprising:
and the first bit stream or the second bit stream obtains the logic value of a fourth target bit positioned outside the target bit stream in the third bit stream according to a fourth logic operation.
8. The data encoding method of claim 7, wherein the step of obtaining the logic value of a fourth target bit in the third bitstream, which is located outside the target bitstream, from the first bitstream or the second bitstream according to a fourth logical operation comprises:
the first bit stream comprises a fifth target bit positioned outside a preset bit stream, and the number of the fourth target bit corresponding to the fifth target bit in the third bit stream is determined according to the number of the fifth target bit in the first bit stream, the number of the preset bit stream in the first bit stream and the number of segments of the preset bit stream in the first bit stream;
and assigning the logic value of the fifth target bit to the logic value of the corresponding fourth target bit in the third bit stream.
9. A data encoding apparatus comprising a controller and a memory, the memory being arranged to store program instructions, the controller being arranged to execute the program instructions to implement the method of any one of claims 1 to 8.
10. A storage medium storing a plurality of instructions adapted to be loaded by a processor to perform the steps of the data encoding method according to any one of claims 1 to 8.
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