CN112994688A - High-resolution ultrasonic frequency source signal processing device and method - Google Patents

High-resolution ultrasonic frequency source signal processing device and method Download PDF

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CN112994688A
CN112994688A CN202110152486.0A CN202110152486A CN112994688A CN 112994688 A CN112994688 A CN 112994688A CN 202110152486 A CN202110152486 A CN 202110152486A CN 112994688 A CN112994688 A CN 112994688A
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phase
phase difference
module
square wave
control word
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CN112994688B (en
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金文博
赵腾
詹益萍
李泉
张瑾芸
朱栋
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Changzhou University
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

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Abstract

The invention discloses a high-resolution ultrasonic frequency source signal processing device and a method, wherein the method comprises the following steps: adjusting a frequency control word K according to the comparison threshold of the smoothed phase difference and the set phase difference; step 2: generating a sine wave by using a lookup table mode according to the adjusted frequency control word K; and step 3: level comparison is carried out on the sine wave and the comparison level, digital square waves are generated, and the digital square waves are processed by a power amplification and isolation circuit and then drive an ultrasonic transducer; and 4, step 4: and (4) iterating the phase difference smoothed in the step (1) according to the voltage and current signals of the ultrasonic transducer, and circularly repeating the step (1-3). The invention has the advantages of high ultrasonic frequency resolution, quick automatic frequency tracking, flexible configuration, small heat productivity of the whole machine and the like, and can be applied to various ultrasonic generators.

Description

High-resolution ultrasonic frequency source signal processing device and method
Technical Field
The invention relates to a high-resolution ultrasonic frequency source signal processing device and method, and belongs to the technical field of ultrasonic generators.
Background
An ultrasonic generator, also called an ultrasonic power supply or an ultrasonic power supply, is one of the core components of a high-power ultrasonic system. At present, ultrasonic generators mainly based on analog systems are often in the market, and the problems of large heat productivity, short service life, unstable technical state, poor reliability and the like of power tubes often occur.
The digital ultrasonic generator is used as a substitute product and is mainly used for welding materials such as masks, plastics, chemical fibers and the like, the existing digital ultrasonic generator adopts a generator controlled by a pure single chip microcomputer, and the defects of low digital pulse resolution, low phase discrimination precision, low frequency following speed, inflexible signal processing mode configuration and the like are caused due to the defects of the existing signal processing method. Therefore, the redesign of the digital ultrasonic generator is urgently needed by those skilled in the art to solve the above disadvantages.
Disclosure of Invention
The purpose is as follows: in order to overcome the defects in the prior art, the invention provides a high-resolution ultrasonic frequency source signal processing device and a high-resolution ultrasonic frequency source signal processing method.
The technical scheme is as follows: in order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a high resolution ultrasonic frequency source signal processing device comprises the following modules:
the parameter receiving module is used for outputting the comparison level to the shaping module and outputting the initial value of the frequency control word K and the phase difference comparison threshold parameter to the frequency control word K automatic adjusting module;
the reference clock module is used for receiving clock pulses of an external crystal oscillator and is used as a reference clock of the counting/converting module;
the frequency control word K automatic adjusting module is used for adjusting the current frequency control word K to increase or decrease according to the smoothed phase difference output by the mean value filtering module and inputting the adjusted frequency control word K into the DDS module;
the DDS module is used for generating a sine wave by using a lookup table mode according to the frequency control word K;
the shaping module is used for comparing the level of the sine wave with the comparison level and generating a digital square wave, wherein the sine wave outputs a high level when being higher than the comparison level, and outputs a low level when being lower than the comparison level;
the band-pass filter module is used for receiving the logic level square waves of the voltage and the current of the transducer for filtering and reducing the logic level square waves into voltage and current sine waves with high signal-to-noise ratio;
the zero level comparator is used for converting a voltage sine wave and a current sine wave into a standard digital square wave with a duty ratio of 50%;
the exclusive-OR operation module performs exclusive-OR logic operation on the standard digital square waves of the voltage and the current to obtain square waves after exclusive-OR, and records the phase lead or lag relation between the voltage and the current corresponding to each square wave;
the counting/converting module is used for counting each square wave by using the square wave subjected to the exclusive or as a counting enabling signal and utilizing a high-frequency reference clock in an oscillation period to obtain a counting value of each square wave;
the average filtering module is used for averaging square wave count values measured in a plurality of continuous oscillation periods by using a sliding window averaging method to obtain a smoothed phase difference and outputting the smoothed phase difference to the frequency control word K automatic adjusting module.
Preferably, the frequency control word K is adjusted as follows:
when the phase difference is larger than a preset phase difference comparison threshold and the U phase is ahead of the I phase, subtracting 1 from the value of the frequency control word K; when the phase U lags behind the phase I, adding 1 to the value of the frequency control word K;
and when the phase difference is not greater than the preset phase difference comparison threshold, not changing the value of the current frequency control word K.
Preferably, the band-pass filter module adopts a narrow-band filter with the oscillation frequency of the transducer as the center frequency.
Preferably, the steps of the xor logic operation and the voltage and current phase lead or lag relation obtaining are as follows:
taking one period of a standard digital square wave of voltage or current as an oscillation period, if a phase difference exists between the voltage and the current, carrying out XOR logic operation to obtain two square waves with equal pulse width in one oscillation period, wherein the pulse width of each square wave represents the phase difference between the voltage and the current; when the voltage phase and the current phase are completely consistent, namely the phase difference is zero, obtaining low levels which are all 0 in one oscillation period after the exclusive-or operation;
when each square wave is at a rising edge, if the voltage standard digital square wave is at a high level and the current standard digital square wave is at a low level, recording the leading phase I of the U phase;
conversely, if the current standard digital square wave is at a high level and the voltage standard digital square wave is at a low level, the U phase lag I phase is recorded.
As a preferred scheme, the parameter receiving module, the frequency control word K automatic adjusting module, the DDS module, the shaping module, the band-pass filter module, the zero level comparison module, the exclusive or operation module, the counting/conversion module, the mean filtering module, and the reference clock module are all implemented by an FPGA.
The ultrasonic frequency source signal processing method comprises the following steps:
step 1: adjusting a frequency control word K according to the comparison threshold of the smoothed phase difference and the set phase difference;
step 2: generating a sine wave by using a lookup table mode according to the adjusted frequency control word K;
and step 3: level comparison is carried out on the sine wave and the comparison level, digital square waves are generated, and the digital square waves are processed by a power amplification and isolation circuit and then drive an ultrasonic transducer;
and 4, step 4: and (4) iterating the phase difference smoothed in the step (1) according to the voltage and current signals of the ultrasonic transducer, and circularly repeating the step (1-3).
Preferably, the step of iterating the phase difference smoothed in step 1 according to the voltage and current signals of the ultrasonic transducer is as follows:
step 1.1: filtering out phase noise in square waves by using a logic level square wave of a voltage U at two ends of an ultrasonic transducer and a current I signal flowing through the transducer, reducing the logic level square wave into a U sine wave and an I sine wave, and comparing zero levels to form a U standard digital square wave and an I standard digital square wave with duty ratio of 50%;
step 1.2: performing exclusive-or operation on the standard digital square waves of U and I with the duty ratio of 50% to obtain exclusive-or square waves, wherein the width of the square waves represents the phase difference between the U and the I, and two square waves with equal pulse width are obtained in each oscillation period;
step 1.3: measuring the numerical values of the two square waves by using a counting method in an oscillation period, and recording the phase advance I phase of the U phase if the voltage standard digital square wave is at a high level and the current standard digital square wave is at a low level when each square wave is at a rising edge; on the contrary, if the current standard digital square wave is at a high level and the voltage standard digital square wave is at a low level, recording the U phase lag I phase;
step 1.4: square wave values in a plurality of continuous oscillation periods are pressed into an FIFO register, and sliding window type mean value filtering is carried out to obtain a smoothed phase difference;
step 1.5: replacing the phase difference smoothed in the step 1 with the phase difference smoothed in the step 1.4;
step 1.6: and (5) circularly repeating the step 1.1 to the step 1.5.
As a preferred scheme, the specific steps of adjusting the frequency control word K are as follows:
step 2.1: when the smoothed phase difference exceeds a preset threshold and the U phase is ahead of the I phase, subtracting 1 from the value of the adjusting frequency control word K, and when the U phase is behind the I phase, adding 1 to the value of the adjusting frequency control word K;
step 2: and if the smoothed phase difference does not exceed the preset threshold, the adjusting frequency control word K is not changed.
Has the advantages that: according to the device and the method for processing the high-resolution ultrasonic frequency source signal, the frequency resolution of the ultrasonic frequency source is high, the output frequency can be conveniently and accurately adjusted, and the transducer is stable in a resonance state; the voltage effective value of the transducer can be accurately adjusted according to the duty ratio of the digital square wave; the driving circuit of the digital square wave can greatly reduce the average current of the power tube and effectively reduce the heat productivity of the power tube; the digital signal processing is realized in the FPGA, so that flexible modification and reconfiguration are facilitated.
Drawings
FIG. 1 is a schematic diagram of the structure of the apparatus of the present invention.
FIG. 2 is a schematic flow diagram of the process of the present invention.
Fig. 3 is a digital pulse waveform driving an ultrasonic transducer.
Fig. 4 is a signal waveform of each stage of the digital phase detector.
Detailed Description
The present invention will be further described with reference to the following examples.
As shown in fig. 1, a high-resolution ultrasonic frequency source signal processing apparatus includes a parameter receiving module, a frequency control word K automatic adjusting module, a DDS module, a shaping module, a band-pass filter module, a zero level comparing module, an xor operation module, a counting/converting module, a mean value filtering module, and a reference clock module, which are connected in sequence, and further includes a reference clock module for providing a global unified clock source for each other module.
And a parameter receiving module in the FPGA is connected with the singlechip through a GPIO port, and receives comparison level, initial values of frequency control words K and phase difference comparison threshold parameters in an SPI serial bus mode.
And the reference clock module in the FPGA is connected with an external crystal oscillator outside the FPGA and used for receiving clock pulses of the external crystal oscillator.
And the frequency control word K automatic adjusting module in the FPGA adjusts the current frequency control word K to increase or decrease according to the smoothed phase difference output by the mean value filtering module so as to control the output frequency of the DDS. When the phase difference is larger than a preset phase difference comparison threshold, adjusting the current frequency control word as follows: when the U phase leads the I phase, subtracting 1 from the value of the current frequency control word K to reduce the output frequency of the DDS; when the U phase lags the I phase, 1 is added to the value of the current frequency control word K to increase the output frequency of the DDS. And if the phase difference is not greater than the preset phase difference comparison threshold, not changing the value of the current frequency control word K. After adjustment, outputting a frequency control word K; u represents the voltage at two ends of the transducer, and I represents the current flowing through the transducer; the preset phase difference comparison threshold is sent by the parameter receiving module.
And the DDS module in the FPGA generates a sine wave by using a lookup table mode according to the frequency control word K.
And the shaping module in the FPGA is connected to an external power amplification and isolation circuit through a GPIO port, amplifies the logic level digital pulse into a high-voltage pulse and drives the ultrasonic transducer through the power amplification and isolation circuit. The shaping module carries out level comparison on the sine wave and the comparison level and generates a digital square wave, the sine wave outputs a high level when being higher than the comparison level, the sine wave outputs a low level when being lower than the comparison level, the duty ratio of the digital square wave can be adjusted by changing the comparison level, and the effective value of the output voltage can be controlled by adjusting the duty ratio of the square wave.
And the band-pass filter module in the FPGA is connected with an external voltage/current sampling circuit and receives logic level square waves of the voltage and the current of the transducer. The band-pass filter module filters square wave signals of voltage and current on the transducer, and the band-pass filter is a narrow-band filter taking the oscillation frequency of the transducer as the center frequency and restores the square wave signals of the voltage and the current on the transducer into voltage and current sine waves with high signal-to-noise ratio so as to accurately measure the phase difference between the voltage and the current sine waves.
And a zero level comparator in the FPGA converts the voltage and current sine waves output by the band-pass filter module into standard digital square waves with the duty ratio of 50% for carrying out digital phase discrimination on the square waves.
An exclusive-or operation module in the FPGA performs exclusive-or logic operation on the standard digital square waves of the voltage and the current, one period of the standard digital square waves of the voltage or the current is used as an oscillation period, if a phase difference exists between the voltage and the current, two square waves with equal pulse width are obtained in one oscillation period after the exclusive-or logic operation, and the pulse width of each square wave represents the magnitude of the phase difference between the voltage and the current; when the voltage and current phases are completely consistent, namely the phase difference is zero, the low level of all 0 is obtained in one oscillation period after the exclusive-or operation. Recording the corresponding lead or lag relation of each square wave, and recording the phase lead I of the U phase if the voltage standard digital square wave is at a high level and the current standard digital square wave is at a low level when each square wave is at a rising edge; conversely, if the current standard digital square wave is at a high level and the voltage standard digital square wave is at a low level, the U phase lag I phase is recorded.
The counting/conversion module in the FPGA uses square waves subjected to exclusive-or logic operation as a counting enabling signal, and counts each square wave by using a high-frequency reference clock in an oscillation period to obtain a count value of each square wave, namely the count value represents a phase difference between voltage and current.
The mean value filtering module in the FPGA averages square wave counting values obtained by measurement in a plurality of continuous oscillation periods in a sliding window mean value solving mode, phase difference denoising is achieved, a smoothed phase difference is obtained, and the smoothed phase difference is used as a judgment basis for adjusting the DDS output frequency.
A high-resolution ultrasonic frequency source signal processing device can generate a frequency source for driving an ultrasonic transducer, can deal with the resonance frequency drift of the transducer, realizes an automatic frequency following function, and enables the transducer to work in a resonance state all the time.
As shown in fig. 2, a method for processing an ultrasonic frequency source signal includes the following steps:
step 1: and adjusting the frequency control word K according to the comparison threshold of the smoothed phase difference and the set phase difference.
Step 2: and generating a sine wave by using a lookup table mode according to the adjusted frequency control word K.
And step 3: and level comparison is carried out on the sine wave and the comparison level to generate a digital square wave, and the digital square wave is processed by a power amplification and isolation circuit to drive the ultrasonic transducer.
And 4, step 4: and (3) iterating the phase difference smoothed in the step (1) according to the voltage and current signals of the ultrasonic transducer, and circularly repeating the step (1-3) to keep the U phase and the I phase consistent, wherein the ultrasonic transducer is always in a resonance state.
The step of iterating the phase difference smoothed in the step 1 according to the voltage and current signals of the ultrasonic transducer is as follows:
step 1: filtering out phase noise in square waves by using a logic level square wave of a voltage U at two ends of an ultrasonic transducer and a current I signal flowing through the transducer, reducing the logic level square wave into a U sine wave and an I sine wave, and forming a U standard digital square wave and an I standard digital square wave with a duty ratio of 50% after zero level comparison, thereby facilitating phase difference measurement;
step 2: the standard digital square waves of U and I with the duty ratio of 50% are subjected to exclusive OR operation to obtain square waves after exclusive OR, the width of the square waves represents the magnitude of the phase difference between the U and the I, two square waves with equal pulse width are obtained in each oscillation period and represent the front edge phase difference and the back edge phase difference respectively, and the measurement accuracy of the phase difference can be improved.
And step 3: measuring the numerical values of the two square waves by using a counting method in an oscillation period, and recording the phase advance I phase of the U phase if the voltage standard digital square wave is at a high level and the current standard digital square wave is at a low level when each square wave is at a rising edge; conversely, if the current standard digital square wave is at a high level and the voltage standard digital square wave is at a low level, the U phase lag I phase is recorded.
And 4, step 4: and (3) pressing the square wave values in a plurality of continuous oscillation periods into an FIFO register, carrying out sliding window type mean value filtering, eliminating noise and obtaining the smoothed phase difference.
And 5: replacing the original smoothed phase difference with the newly calculated smoothed phase difference;
step 6: and (5) circularly repeating the step 1 to the step 5.
The specific steps of adjusting the frequency control word K are as follows:
step 1: when the smoothed phase difference exceeds a preset threshold and the U phase leads the I phase, subtracting one from the adjusting frequency control word K value, namely reducing the output frequency of the DDS, and when the U phase lags the I phase, adding one to the adjusting frequency control word K value to improve the output frequency of the DDS;
step 2: and if the smoothed phase difference does not exceed the preset threshold, the adjusting frequency control word K is not changed.
The steps finish the digital phase discrimination between the U and the I, and adjust the DDS output frequency according to the phase discrimination result, thereby realizing the automatic closed loop feedback type frequency tracking function.
Example 1:
a high-resolution ultrasonic frequency source signal processing device utilizes a Spartan6 series FPGA of Xilinx company as a main processor, generates digital pulses with certain frequency and realizes closed-loop control by measuring voltage and current phase difference of a transducer so as to stabilize the resonance state of the ultrasonic transducer. ISE14 was used as a development environment for FPGA programs and a 25MHz external crystal was used as a reference clock. The STM32 singlechip is used as a coprocessor, the singlechip writes the initial value of the frequency control word K, the comparison level value and the phase difference comparison threshold parameter into the FPGA through an SPI bus to realize the initialization of the device, and the specific implementation method of the signal processing in the FPGA comprises the following steps:
as shown in fig. 3 (1), after the FPGA circuit board is powered on, the single chip microcomputer writes in an initial value of a frequency control word, a sine wave with a corresponding frequency is generated by using a DDS IP verification example in an ISE14 development environment, the bit width of the frequency control word of the DDS is set to 28 bits, and when the reference clock is 25MHz, the frequency resolution is better than 0.1 Hz;
(2) the sine wave is shaped into square waves by utilizing a level comparison mode, the comparison level of the square waves can be adjusted on site by a user through a potentiometer, the single chip microcomputer writes the corresponding comparison level into the FPGA according to the voltage value on the potentiometer, and the duty ratio of the shaped square waves can be changed by adjusting the comparison level, so that the output power on the transducer is adjusted;
(3) the square wave with certain frequency and duty ratio is isolated by an IGBT power amplifying circuit and a transformer and then output to an ultrasonic transducer;
(4) after the ultrasonic transducer starts oscillation, a voltage/current acquisition circuit is utilized to convert a higher voltage U at two ends of the transducer and a current I flowing through the transducer into a logic level square wave through a level comparator based on operational amplifier and send the logic level square wave into an FPGA;
as shown in fig. 4, (5) digital phase discrimination is performed on the U and I sampling square waves inside the FPGA, and the specific process is as follows: the U-and I-sampling square waves are subjected to band-pass filtering in sequence to obtain sine waves U _ sin and I _ sin, standard digital square waves U _ half _ duty and I _ half _ duty with duty ratios of 50% are obtained after zero level comparison, the U _ half _ duty standard digital square wave period is taken as an oscillation period, and the U _ half _ duty and the I _ half _ duty standard digital square waves are subjected to an exclusive-OR gate in the oscillation period to obtain U _ I _ xor square waves (pulse widths of the square waves represent phase differences between U and I). The U _ I _ xor square wave is used as a counting enabling signal, a 25MHz clock is used for counting, the pulse width of the U _ I _ xor square wave is obtained by counting in a vibration period, if an ultrasonic transducer works at 20KHz, one vibration period is 50 microseconds, and the phase lead/lag state between U and I is recorded;
(6) carrying out mean value filtering on pulse width values of the U _ I _ xor square waves obtained in 16 continuous vibration periods to remove noise and obtain a smooth U-I phase difference;
(7) and when the U-I phase difference is larger than a preset threshold, automatically adjusting the DDS frequency control word. And when the U leads the I, subtracting one from the DDS frequency control word value, otherwise, adding one to the DDS frequency control word value, thereby realizing the closed-loop control of the working frequency of the ultrasonic transducer and enabling the ultrasonic transducer to be in a resonance state all the time.
Generating a sine wave with high frequency and high resolution by using a DDS (direct digital synthesizer) on an FPGA (field programmable gate array) chip, and shaping the sine wave into a digital square wave with a certain duty ratio by using a level comparator; the digital square wave is amplified to drive an ultrasonic transducer; meanwhile, in order to adapt to the problem of the resonance frequency point drift of the transducer, phase difference measurement is carried out on voltage and current signals on the ultrasonic transducer in the FPGA, and the frequency of the DDS sine wave is automatically adjusted according to the phase difference measurement result, so that the closed-loop feedback type automatic frequency following function is realized. Based on the working principle, the invention has the advantages of high ultrasonic frequency resolution, quick automatic frequency tracking, flexible configuration, small overall heat productivity and the like, can replace the traditional analog ultrasonic generator and the digital ultrasonic generator based on a single chip microcomputer, and is more beneficial to being integrated on a full-automatic material welding production line.
The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.

Claims (8)

1. A high resolution ultrasonic frequency source signal processing device is characterized in that: the system comprises the following modules:
the parameter receiving module is used for outputting the comparison level to the shaping module and outputting the initial value of the frequency control word K and the phase difference comparison threshold parameter to the frequency control word K automatic adjusting module;
the reference clock module is used for receiving clock pulses of an external crystal oscillator and is used as a reference clock of the counting/converting module;
the frequency control word K automatic adjusting module is used for adjusting the current frequency control word K to increase or decrease according to the smoothed phase difference output by the mean value filtering module and inputting the adjusted frequency control word K into the DDS module;
the DDS module is used for generating a sine wave by using a lookup table mode according to the frequency control word K;
the shaping module is used for comparing the level of the sine wave with the comparison level and generating a digital square wave, wherein the sine wave outputs a high level when being higher than the comparison level, and outputs a low level when being lower than the comparison level;
the band-pass filter module is used for receiving the logic level square waves of the voltage and the current of the transducer for filtering and reducing the logic level square waves into voltage and current sine waves with high signal-to-noise ratio;
the zero level comparator is used for converting a voltage sine wave and a current sine wave into a standard digital square wave with a duty ratio of 50%;
the exclusive-OR operation module performs exclusive-OR logic operation on the standard digital square waves of the voltage and the current to obtain square waves after exclusive-OR, and records the phase lead or lag relation between the voltage and the current corresponding to each square wave;
the counting/converting module is used for counting each square wave by using the square wave subjected to the exclusive or as a counting enabling signal and utilizing a high-frequency reference clock in an oscillation period to obtain a counting value of each square wave;
the average filtering module is used for averaging square wave count values measured in a plurality of continuous oscillation periods by using a sliding window averaging method to obtain a smoothed phase difference and outputting the smoothed phase difference to the frequency control word K automatic adjusting module.
2. The apparatus according to claim 1, wherein: the frequency control word K is adjusted as follows:
when the phase difference is larger than a preset phase difference comparison threshold and the U phase is ahead of the I phase, subtracting 1 from the value of the frequency control word K; when the phase U lags behind the phase I, adding 1 to the value of the frequency control word K;
and when the phase difference is not greater than the preset phase difference comparison threshold, not changing the value of the current frequency control word K.
3. The apparatus according to claim 1, wherein: the band-pass filter module adopts a narrow-band filter taking the oscillation frequency of the transducer as the center frequency.
4. The apparatus according to claim 1, wherein: the XOR logic operation and the voltage and current phase lead or lag relationship obtaining steps are as follows:
taking one period of a standard digital square wave of voltage or current as an oscillation period, if a phase difference exists between the voltage and the current, carrying out XOR logic operation to obtain two square waves with equal pulse width in one oscillation period, wherein the pulse width of each square wave represents the phase difference between the voltage and the current; when the voltage phase and the current phase are completely consistent, namely the phase difference is zero, obtaining low levels which are all 0 in one oscillation period after the exclusive-or operation;
when each square wave is at a rising edge, if the voltage standard digital square wave is at a high level and the current standard digital square wave is at a low level, recording the leading phase I of the U phase;
conversely, if the current standard digital square wave is at a high level and the voltage standard digital square wave is at a low level, the U phase lag I phase is recorded.
5. The apparatus and method for processing high resolution ultrasonic frequency source according to any one of claims 1 to 4, wherein: the parameter receiving module, the frequency control word K automatic adjusting module, the DDS module, the shaping module, the band-pass filter module, the zero level comparison module, the XOR operation module, the counting/conversion module, the mean value filtering module and the reference clock module are all realized through the FPGA.
6. A high-resolution ultrasonic frequency source signal processing method is characterized by comprising the following steps: the method comprises the following steps:
step 1: adjusting a frequency control word K according to the comparison threshold of the smoothed phase difference and the set phase difference;
step 2: generating a sine wave by using a lookup table mode according to the adjusted frequency control word K;
and step 3: level comparison is carried out on the sine wave and the comparison level, digital square waves are generated, and the digital square waves are processed by a power amplification and isolation circuit and then drive an ultrasonic transducer;
and 4, step 4: and (4) iterating the phase difference smoothed in the step (1) according to the voltage and current signals of the ultrasonic transducer, and circularly repeating the step (1-3).
7. The method for processing the signal of the high-resolution ultrasonic frequency source according to claim 6, wherein: the step of iterating the phase difference smoothed in the step 1 according to the voltage and current signals of the ultrasonic transducer is as follows:
step 1.1: filtering out phase noise in square waves by using a logic level square wave of a voltage U at two ends of an ultrasonic transducer and a current I signal flowing through the transducer, reducing the logic level square wave into a U sine wave and an I sine wave, and comparing zero levels to form a U standard digital square wave and an I standard digital square wave with duty ratio of 50%;
step 1.2: performing exclusive-or operation on the standard digital square waves of U and I with the duty ratio of 50% to obtain exclusive-or square waves, wherein the width of the square waves represents the phase difference between the U and the I, and two square waves with equal pulse width are obtained in each oscillation period;
step 1.3: measuring the numerical values of the two square waves by using a counting method in an oscillation period, and recording the phase advance I phase of the U phase if the voltage standard digital square wave is at a high level and the current standard digital square wave is at a low level when each square wave is at a rising edge; on the contrary, if the current standard digital square wave is at a high level and the voltage standard digital square wave is at a low level, recording the U phase lag I phase;
step 1.4: square wave values in a plurality of continuous oscillation periods are pressed into an FIFO register, and sliding window type mean value filtering is carried out to obtain a smoothed phase difference;
step 1.5: replacing the phase difference smoothed in the step 1 with the phase difference smoothed in the step 1.4;
step 1.6: and (5) circularly repeating the step 1.1 to the step 1.5.
8. The method for processing the signal of the high-resolution ultrasonic frequency source according to claim 6, wherein: the specific steps of adjusting the frequency control word K are as follows:
step 2.1: when the smoothed phase difference exceeds a preset threshold and the U phase is ahead of the I phase, subtracting 1 from the value of the adjusting frequency control word K, and when the U phase is behind the I phase, adding 1 to the value of the adjusting frequency control word K;
step 2: and if the smoothed phase difference does not exceed the preset threshold, the adjusting frequency control word K is not changed.
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