CN112993746A

CN112993746A - Semiconductor laser pulse driver with multiple closed-loop control

Info

Publication number: CN112993746A
Application number: CN202110155684.2A
Authority: CN
Inventors: 黄丫; 张聪; 于兰; 孟瑜; 李胜男; 吴戈
Original assignee: Changchun Institute of Applied Chemistry of CAS
Current assignee: Changchun Institute of Applied Chemistry of CAS
Priority date: 2021-02-04
Filing date: 2021-02-04
Publication date: 2021-06-18
Anticipated expiration: 2041-02-04
Also published as: CN112993746B

Abstract

The invention discloses a semiconductor laser pulse driver with multiple closed-loop control, which belongs to the technical field of electronic technology and is structurally provided with a singlechip module (1), a high-voltage energy storage module (2), a pulse width adjusting module (3), a pulse driving module (4), a modulation input module (5), a pulse display module (6), an indicator lamp driving module (7), a key input module (8), a front panel (9), an adaptive sampling module (10), a pulse peak current detection module (11), an adaptive peak adjusting module (12), a pulse width detection module (13), a detection module (14), a band-pass filtering module (15) and a pulse frequency detection module (16). The invention detects the peak current, the repetition frequency and the pulse width of the output pulse current signal in real time with high precision and corrects the peak current, the repetition frequency and the pulse width of the output pulse current signal of the driver to be consistent with the set value.

Description

Semiconductor laser pulse driver with multiple closed-loop control

Technical Field

The invention belongs to the technical field of electronic technology. And more particularly to a pulse driver for a semiconductor laser with multiple closed loop control.

Background

Pulse-driven semiconductor lasers have important applications in many fields such as laser radar, laser ranging, optical fiber communication, 3D image processing, and the like. The performance of the material directly influences the effect of the material in practical application, such as: in pulse type semiconductor laser range finders and laser radars, the rise time of pulse laser is closely related to the measurement accuracy, and the shorter the rise time is, the more the measurement accuracy is improved; the peak power of the pulse laser is closely related to the measurement distance, and the larger the peak power is, the more beneficial the measurement distance is to be increased. The performance of the pulsed semiconductor laser mainly depends on the pulse driver for providing the driving signal, so that the pulse driver needs to be designed with optimized parameters.

At present, common semiconductor laser pulse drivers do not have closed-loop control, and the closest prior art to the present invention is a chinese patent ZL201611197547.0 "pulse laser distance measuring instrument emitter driving power supply", in which a design scheme of a semiconductor laser pulse driving power supply is provided, so that the driving power supply can output a larger pulse peak current and simultaneously keep a shorter output pulse width and a shorter pulse current rise time.

However, the technique disclosed in patent ZL201611197547.0 has no closed-loop control on the peak value, repetition frequency and pulse width of the output current pulse signal of the laser pulse driver, and this circuit has many disadvantages: firstly, when a pulse driver drives semiconductor lasers of different models, the output peak current and the pulse width of the pulse driver of the laser are changed due to different equivalent reactance parameters of the lasers, so that the peak current and the pulse width of a pulse current signal output by the driver have larger deviation from a set value; secondly, different use environments of the laser pulse driver, temperature environment change inside the instrument caused by heating after the laser pulse driver is started and other factors can affect the repetition frequency of the pulse current signal output by the laser pulse driver, so that the repetition frequency of the pulse current signal output by the driver has larger deviation with a set value. Therefore, the technology of the pulse driver of the semiconductor laser disclosed at present needs to be further improved.

Disclosure of Invention

The invention aims to solve the technical problem that the prior art is insufficient, and provides a semiconductor laser pulse driver with multiple closed-loop control, which is used for carrying out real-time high-precision detection on the peak current, the repetition frequency and the pulse width of a pulse current signal output by the laser pulse driver and correcting the output of the laser pulse driver according to the fed-back pulse current signal parameters, so that closed-loop control is formed, and the peak current, the repetition frequency and the pulse width of the pulse current signal output by the laser pulse driver are ensured to be consistent with set values.

The technical problem of the invention is solved by the following technical scheme:

a semiconductor laser pulse driver with multiple closed-loop control structurally comprises a pulse display module 6 and a front panel 9, and is characterized in that the pulse driver is further structurally provided with a single chip microcomputer module 1, a high-voltage energy storage module 2, a pulse width adjusting module 3, a pulse driving module 4, a modulation input module 5, an indicator lamp driving module 7, a key input module 8, an adaptive sampling module 10, a pulse peak current detection module 11, an adaptive peak adjusting module 12, a pulse width detection module 13, a detection module 14, a band-pass filtering module 15 and a pulse frequency detection module 16;

the structure of the single chip microcomputer module 1 is that a port VCC and a port GND of a single chip microcomputer U1 are respectively connected with a +5V power supply and a digital ground, VCC is grounded through a capacitor C1 and a capacitor C2, the port VCC and the port GND of a level conversion chip U2 are respectively connected with the +5V power supply and the digital ground, a port VDD is connected with the +5V power supply through a capacitor C3, a port VEE is connected with the digital ground through a capacitor C4, a capacitor C5 is connected between the port C2+ and the port C2-, a capacitor C6 is connected between the port C1+ and the port C1-, a port T1IN and a port R1OUT are respectively connected with a port D and a port TXD of a single chip microcomputer U1, the port RXRD 1IN and the port T1OUT are respectively connected with a pin 3 and a pin 2 of a D-shaped interface J3, the pin 5 of the D-shaped interface J3 is connected with the digital ground, the model number of the single chip microcomputer U1 is STC15W408, the model of the level conversion chip 2;

the high-voltage energy storage module 2 is structurally characterized in that a port GND of the switch control chip U3 is connected with an analog ground, and an endThe port VCC is connected with a +12V power supply, the port SWC is connected with a port SWC through a resistor R2 and is connected with an analog ground through a capacitor C7, the port SWE is connected with the grid electrode of an N-channel field effect tube Q1 and is connected with the analog ground through a resistor R4, the port TCAP is connected with the analog ground through a capacitor C8, the port IPK is connected with the same name end of a primary coil of a pulse transformer T1, the port DRVC is connected with a port R3 and is connected with the +12V power supply through a resistor R1, the other end of the primary coil of the pulse transformer T1 is connected with the drain electrode of the N-channel field effect tube Q1, the source electrode of the N-channel field effect tube Q1 is connected with the analog ground, a port-V IN of a switch control chip U3 is connected with a port W of a digital potentiometer U4 and is connected with the analog ground through a resistor R5, a port VDD and a port GND of the digital potentiometer U4 are respectively connected with the +5V power supply and the digital ground, a port ADDR 1 and a port VSS are respectively connected with an EXV, the port SDA is connected with a port P21 of a singlechip U1 through a resistor R8

The power supply is connected with a +5V power supply through a resistor R7, the like name of a secondary coil of a pulse transformer T1 is connected with the anode of a Schottky diode D1, the like name of the secondary coil of the pulse transformer T1 is connected with a port A of a digital potentiometer U4 through a resistor R6, the other end of the secondary coil of the pulse transformer T1 is connected with an analog ground, the cathode of the Schottky diode D1 serving as the output end of the high-voltage energy storage module 2 is marked as a port H _ Vpulse, and the Schottky diode D1 is connected with the analog ground through capacitors C10, C11, C12, C13 and C14 which are connected in parallel, the model of the switch control chip U3 is MC34063, and the model of the digital potentiometer U4;

the key input module 8 has the structure that the input end of an inverted Schmitt trigger U11A is connected with a +5V power supply through a pin 1 of a resistor R31 socket J5 and is connected with a digital ground through a resistor R30 and a capacitor C22, the output end of the inverted Schmitt trigger U11B is connected with a port P06 of a singlechip U1 through a pin 2 of a resistor R33 socket J5 and is connected with a +5V power supply through a resistor R32 and is connected with a digital ground through a capacitor C23, the output end of the inverted Schmitt trigger U11C is connected with a port P07 of a singlechip U1 through a pin 3 of a resistor R35 socket J5 and is connected with a +5V power supply through a resistor R34 and is connected with a digital ground through a capacitor C24, the output end of the inverted Schmitt trigger U11D is used as one output end of the key input module 8 and is marked as a port Enable, the input end of the inverted Schmitt trigger U11 is connected with a digital ground through a pin 4 of a resistor R2 socket J5956 and is connected with a capacitor C84, the output end of the INT0 of the singlechip U1, the input end of the reverse Schmitt trigger U11E is connected with a pin 5 of a plug socket J5 through a resistor R39, a +5V power supply through a resistor R38 and a digital ground through a capacitor C26, and the output end of the INT1 of the singlechip;

the structure of the modulation input module 5 is that a port P25 of a singlechip U1 is connected with a grid electrode of an N-channel field effect tube Q3, a source electrode of the N-channel field effect tube Q3 is connected with an analog ground, a drain electrode is connected with a pin 5 of a relay K1, a pin 4 of a relay K1 is connected with a +12V power supply, a pin 3 is connected with a port P24 of the singlechip U1, a pin 1 is used as an output end of the modulation input module 5 and is marked as a port Pulse _ Orig, a pin 2 is connected with an anode of a Schottky diode D6 and a cathode of the Schottky diode D7 and is connected with an output end of an operational amplifier U9A through a resistor R18, a cathode of the Schottky diode D6 is connected with the +5V power supply, an anode of the Schottky diode D7 is connected with a digital ground, a non-inverting input end of the operational amplifier U9A is connected with an output end of the operational amplifier U9A through a resistor R17 and is connected with the digital ground through a resistor R16, an anode of the Schottky diode D4 and a cathode of the Schottky, the cathode of the Schottky diode D4 is connected with a +5V power supply, the anode of the Schottky diode D5 is connected with a digital ground, and the 2 pin of the socket J2 is connected with the digital ground;

the structure of the Pulse width adjusting module 3 is that the port D of the D trigger U5A is connected with the port Enable of the key input module 8, the port CLK is connected with the port Pulse _ origin of the modulation input module 5, the port CLR is connected with the +5V power supply, and the port

The output terminal of the Pulse width adjusting module 3 is denoted as a port Pulse _ LC, the port PR is connected to the port a of the digital potentiometer U6 and is connected to the digital ground through a capacitor C15, the port Q is connected to the tap end of the potentiometer W1, one fixed terminal of the potentiometer W1 is connected to the port W of the digital potentiometer U6, the port VDD and the port GND of the digital potentiometer U6 are respectively connected to the +5V power supply and the digital ground, the port ADDR and the port VSS are respectively connected to the +5V power supply and the digital ground, the port EXT _ CAP is connected to the digital ground through a capacitor C16, the port SCL is connected to the port P22 of the monolithic computer U1 through a resistor R12,the port SDA is connected with a port P23 of a singlechip U1 through a resistor R11

The power supply of +5V is connected through a resistor R10, and the model of the digital potentiometer U6 is AD5272 BRMZ-50;

the Pulse driving module 4 is structured IN that a tap of a potentiometer W2 is connected with a port Pulse _ LC of the Pulse width adjusting module 3, a fixed end of a potentiometer W2 is connected with an analog ground through a capacitor C19 and is connected with a port IN a and a port IN B of the MOSFET driving chip U7 IN parallel, a port VCC and a port GND of the MOSFET driving chip U7 are respectively connected with a +12V power supply and an analog ground, ports EN a and EN B are connected with a +12V power supply and are connected with an analog ground through a capacitor C17 and a capacitor C18 which are connected IN parallel, a port OUT a and a port OUT B are connected with an anode of a diode D2 and are connected with a base of a PNP triode Q2, a collector of the PNP triode Q2 is connected with the analog ground, a cathode of the diode D2 is connected with an anode of a diode D3, a cathode of the diode D3 is connected with an emitter of the PNP triode Q2 and is connected with one end of a capacitor C13 and one end of a capacitor C20, and the other end of the resistor R13 and the capacitor C35, after the

pins

1, 3, 4 and 6 of the high-speed MOSFET chip U8 are connected together, the output end of the pulse driving module 4 is marked as a port L _ Apulse, the port D of the high-speed MOSFET chip U8 is connected with the port 2 of the socket J12, and the port 1 of the socket J12 is connected with the port H _ Vpulse; the model of the MOSFET driving chip U7 is IXDD404, and the model of the high-speed MOSFET chip U8 is DE275-201N 25A;

the self-adaptive sampling module 10 is structurally characterized in that a port P55 of a singlechip U1 is connected with a grid electrode of an N-channel field effect tube Q10, a source electrode of an N-channel field effect tube Q10 is connected with an analog ground, a drain electrode of the N-channel field effect tube Q10 is connected with a pin 5 of a relay K2, a pin 4 of a relay K2 is connected with a +12V power supply, a pin 3 is connected with the ground through a connecting resistor Rs1, a pin 1 is connected with a port L _ Apulse of a pulse driving module 4, and a pin 2 is connected with the ground through; the type of the relay K2 is HRS4H-S-DC 12V;

the pulse display module 6 has the structure that the ports D0-D7 of the display screen U10 are respectively connected with the ports P10-P17 of the singlechip U1, and the ports EN, W/R and RS are respectively connected with the ports P26, P26 and RS of the singlechip U1

And port

The port VL and the port BL-are connected with a digital ground, the port BL + is connected with a tap end of a potentiometer W3, the port VDD is connected with a +5V power supply and is connected with the digital ground through a capacitor C21, the port VSS is connected with the digital ground, one fixed end of the potentiometer W3 is connected with the +5V power supply, and the display screen U10 is of the type LCD 1602;

the structure of the indicator lamp driving module 7 is that the grid of an N-channel field effect transistor Q4 is connected with a port P03 of a singlechip U1 through a resistor R20, the source is connected with a digital ground, the drain is connected with a 1 pin of a socket J4 through a resistor R19, the grid of the N-channel field effect transistor Q5 is connected with a port P04 of a singlechip U1 through a resistor R22, the source is connected with a digital ground, the drain is connected with a2 pin of a socket J4 through a resistor R21, the grid of the N-channel field effect transistor Q6 is connected with a port P05 of a singlechip U1 through a resistor R24, the source is connected with a digital ground, the drain is connected with a 3 pin of a socket J23 through a resistor R4, the grid of the P-channel field effect transistor Q7 is connected with a port Enable of a key input module 8 through a resistor R26, the source is connected with a +5V power supply; the grid of the N-channel field effect transistor Q8 is connected with the grid of the P-channel field effect transistor Q9 and is connected with a port P25 of a singlechip U1 through a resistor R29, the source is connected with a digital ground, the drain is connected with a pin 5 of a socket J4 through a resistor R27, the source of the P-channel field effect transistor Q9 is connected with a +5V power supply, and the drain is connected with a pin 6 of a socket J4 through a resistor R28;

the structure of the front panel 9 includes a display screen 901, a pulse amplitude indicator lamp 902, a pulse width indicator lamp 903, a repetition frequency indicator lamp 904, a pulse parameter selection button 905, a parameter adjustment knob 906, a power switch 907, an output control switch 908, a modulation input port 909, an internal modulation indicator lamp 910, an external modulation indicator lamp 911, an operation mode button 912, a current output indicator lamp 913 and a current output port 914, wherein the display screen 901 is a display screen U10 of the pulse display module 6, the model is an LCD1602, the pulse amplitude indicator lamp 902, the pulse width indicator lamp 903, the repetition frequency indicator lamp 904, the current output indicator lamp 913 and the internal modulation indicator lamp 910 are 5 light emitting diodes, the anodes thereof are all connected with a +5V power supply, the cathodes thereof are respectively connected with a pin 1, a pin 2, a pin 3, a pin 4 and a pin 5 of a socket 4 of the indicator lamp driving module 7, the external modulation indicator lamp 911 is also a light emitting diode, the anode of the parameter adjusting knob is connected with 6 pins of a socket J4 in an indicator lamp driving module 7, the cathode of the parameter adjusting knob is connected with a digital ground, one pin of a pulse parameter selecting button 905 is connected with 1 pin of a socket J5 in a key input module 8, the other pin is connected with the digital ground, the parameter adjusting knob 906 is a rotary encoder, the 1 pin of the rotary encoder is connected with 4 pins of the socket J5 in the key input module 8, the 2 pins of the rotary encoder is connected with 5 pins of a socket J5 in the key input module 8, the common end of the 3 pins of the rotary encoder is connected with the digital ground, a power switch 907 is a master switch for judging whether the whole device is electrified or not, an output control switch 908 is a key switch, one pin of the key switch is connected with 3 pins of a socket J5 in the key input module 8, the other pin is connected with the digital ground, a modulation input port 909 is a female SMA head, the anode of the parameter adjusting knob is connected with 1 pin of a socket J2, one pin of the working mode button 912 is connected to pin 2 of the socket J5 in the key input module 8, the other pin is connected to digital ground, the current output port 914 is also an SMA female connector, the anode thereof is connected to pin 1 of the socket J1 in the pulse driving module 4, and the cathode thereof is connected to pin 2 of the socket J1 in the pulse driving module 4.

The pulse peak current detection module 11 has the structure that a port 4 of an amplifier U12A is grounded, a port 3 is connected with a port L _ Apulse, a port 8 is connected with a +5V power supply, a port 1 is connected with an input end of a D8, an output end of the D8 is connected with a capacitor C27 and is grounded, a port 2 is connected with an R42 and is connected with an output end of a diode D8 and a port P00 of a single chip microcomputer U1;

the adaptive peak value adjusting module 12 has a structure that a VDD port and a GND port of U13 are respectively connected with a +5V power supply and an analog ground, a port ADDR is connected with a +5V power supply, a port SCL is connected with a port P02 of a singlechip U1 through a resistor R44, a port SDA is connected with a port P27 of a singlechip U1 through a resistor R45, and the port SDA is connected with a port P27 of the singlechip U1

A +5V power supply is connected through a resistor R46, a port EXT _ CAP is grounded through a capacitor C28, a port VSS is grounded, a port W is connected with a port 6 of U12B and is grounded through a R47, a port 5 of U12B is connected with an L _ Apulse, and a terminalThe port a is connected with the port 7 of the U12B, and then serves as the output end of the adaptive peak adjusting module 12, which is marked as the port H _ Apulse;

the pulse width detection module 13 is configured such that a port H _ Apulse is connected to a port 5 of U14B, a port 2 of U14A, a VCC port and a VSS port of U15 are respectively connected to a +5V power supply and a-5V power supply, a port S1 is grounded, a port S3 is connected to Sine1k, a port IN3 is connected to a port 7 of U14 3, a port 8 of U14 3 is connected to the +5V power supply, a positive electrode of D3 is grounded, a negative electrode of D3 is connected to a port 3 of U14 3, a port 6 of U14 3 is connected to the +5V power supply through a resistor R3, a port 4 of U14 3 is grounded, a port 1 is connected to the port IN3 of U3, a port D3 and a port D3 are connected to R3 and grounded through a C3, a port 3 of U16 3 is grounded, a port 4 is connected to the-5V power supply, a port 8 is connected to the +5V power supply, a port 2 is connected to the ground through a positive electrode C3 of R3, a capacitor R3, a positive electrode of the terminal 3 is connected to the ground, and the port 3, the port is connected to the ground through the capacitor R36, the port 6 is connected with the anode of a capacitor C31 through R53, and is connected with the port 7 of a U16B through a capacitor C32, the port 7 of the U16B is connected with the anode of a capacitor C31 through a resistor R54, and the output end of the pulse width detection module 13 is marked as a port Sined;

the structure of the detection module 14 is that a port RMS of U17 is connected with a port IBFOUT and a port IBUFIN through a capacitor C37, the port IBUFIN + is connected with a port IGND through a capacitor C36 and a resistor R55, the port OGND is grounded, a port OUT is grounded through a capacitor C35 and a port OBUFIN +, the port CAVG is connected with a +5V power supply through a capacitor C34, the port CCF is connected with a +5V power supply through a capacitor C33, the port VCC, the port IBV +, the port OBUFV + are connected with a +5V power supply, the port OBOUT and the port OBUFIN-are connected with a port P01 of a singlechip U1, and the port VEE is connected with a-5V power supply;

the structure of the band-pass filter module 15 includes that a port 4 of a U18A is connected with a-5V power supply, a port 8 is connected with a +5V power supply, a port 2 is connected with a port 1 through a connector R58, is connected with a port P41 of a singlechip U1 through a capacitor C38 and a connector R56, a common point of a capacitor C38 and a capacitor R56 is grounded through a connector R57 and is connected with the port 1 through a connector C39, the port 1 is connected with a port 6 of a U18 through a connector R59 and a connector C40, the port 6 of the U18B is connected with a port 7 through a connector R61, a common point of the R59 and the capacitor C40 is connected with the port 7 through a connector C41 and is grounded through a connector R60, and the port 7 serves as;

the pulse frequency detection module 16 has a structure that a port RST of a U19 is grounded, a port CLK is connected with a port H _ Apulse, a port I0 of a U20, a port Q1 is connected with a port I1 of a U20, a port Q2 is connected with a port I2 of a U20, a port Q3 is connected with a port I3 of a U20, a port Q4 is connected with a port I4 of a U20, a port Q5 is connected with a port I5 of a U20, a port Q6 is connected with a port I6 of a U20, a port Q7 is connected with a port I7 of a U20, a port a of a U20 is connected with a port P35 of a singlechip U1, a port B of a U20 is connected with a port P36 of a singlechip U1, a port C of a U36 is connected with a port P36 of the singlechip U36, and a port is grounded;

in the pulse driver of the semiconductor laser with multiple closed-loop control, the preferable parameters of each element are as follows: 47uF, 100nF/200V Dacron, 100pF, 10nF/150V Dacron, 10pF, 4.7uF, 1nF, 470uF/200V Dacron, 4.7nF/150V Dacron, 47nF, 330nF, 470uF, 39nF, 220nF, 10uF, 3.3uF, 470nF, 3.520nF, 470nF, 520nF, 5200 SB, the types of the diode D2, the diode D3 and the diode D8 are all 1N4148, the types of the Schottky diodes D4-Schottky diodes D7 are all 1N5817, the types of the voltage-stabilizing diode D10 are 2.5V in voltage-stabilizing value, the types of the N-channel field effect tube Q3-N-channel field effect tube Q6, the types of the N-channel field effect tube Q8 and the N-channel field effect tube Q10 are all 2SK1482, the types of the P-channel field effect tube Q7 and the P-channel field effect tube Q9 are all 2SJ507, the type of the resistor R1 is 0.3 omega, the types of the resistor R2-resistor R4 are all 100 omega, the type of the resistor R14, the resistor R20, the type of the resistor R22, the type of the resistor R24, the type of the resistor R26, the resistor R29, the type of the resistor R30, the resistor R32, the type of the resistor R34, the resistor R34 and the type of the resistor R34, the resistor 34 and the type of the resistor 34, the resistor R19, the resistor R21, the resistor R23, the resistor R25, the resistor R27 and the resistor R28 are all 300 omega, the resistor R13 is 400 omega, the resistor R11, the resistor R12, the resistor R16, the resistor R8, the resistor R9, the resistor R44 and the resistor R45 are all 5.1k omega, the resistor R17 is 51k omega, the resistor R6 is 9.1k omega precision resistor, the resistor R42 is 1M omega, the resistor R49 is 6.5k omega, the resistor R51 is 15k omega, the resistor R50 is 4.5k omega, the resistor R54 is 6k omega, the resistor R52 is 3k omega, the resistor R52 is 1.8k omega, the resistor R52 is 2k, the resistor R52 is 10M omega, the resistors R52 and R52 are all 125k omega, the resistor R52 is 600 omega, the resistor R72 is 72 k, the resistor R52 k is 2k, the TLC, the resistor R52 is 10M omega, the TLC 52, the amplifier is a TLC, the resistor R52, the amplifier is a TRX 52, the TLC 72, the type TRX 52, the TRX 52 is a TRX 52, the TRX 52, models of an inverse Schmitt trigger U11A-an inverse Schmitt trigger U11E are SN7414N, models of an operational amplifier U14A and an operational amplifier U14B are AD826, models of an operational amplifier U16A, an operational amplifier U16B, an operational amplifier U18A and an operational amplifier U18B are AD822, models of a D trigger U5A are 74S74, a Pulse transformer T1 is PA2547NL produced by Pulse Electronics, and models of a relay K1 and a relay K2 are HRS4H-S-DC 12V.

Has the advantages that:

1. the pulse peak current detection module can carry out high-precision detection on the peak value of an output pulse current signal when the laser pulse driver drives semiconductor lasers of different models.

2. The pulse width detection module can realize accurate detection of full width at half maximum (FWHM) of output pulse current signals when the laser pulse driver drives semiconductor lasers of different models through a self-adaptive amplitude adjustment technology.

3. The pulse frequency detection module can carry out high-precision detection on the repetition frequency of the pulse current signal output by the laser pulse driver through a high-speed self-adaptive frequency division technology.

4. The invention can correct the output pulse current signal of the laser pulse driver according to the feedback pulse current signal parameter to form closed-loop control, and ensure that the peak current, the repetition frequency and the pulse width of the output pulse current signal of the laser pulse driver are consistent with a set value.

Drawings

Fig. 1 is a block diagram of the overall system of the present invention semiconductor laser pulse driver with multiple closed loop control.

Fig. 2 is a schematic circuit diagram of the one-chip microcomputer module 1.

Fig. 3 is a schematic circuit diagram of the high-voltage energy storage module 2.

Fig. 4 is a schematic circuit diagram of the pulse width adjusting module 3.

Fig. 5 is a schematic circuit diagram of the pulse drive module 4.

Fig. 6 is a schematic circuit diagram of the modulation input module 5.

Fig. 7 is a schematic circuit diagram of the pulse display module 6.

Fig. 8 is a schematic circuit diagram of the indicator light driving module 7.

Fig. 9 is a schematic circuit diagram of the key input module 8.

Fig. 10 is a schematic view of the front panel 9.

Fig. 11 is a schematic circuit diagram of the adaptive sampling module 10.

Fig. 12 is a schematic circuit diagram of the pulse peak current detection module 11.

Fig. 13 is a schematic circuit diagram of the adaptive peak adjustment module 12.

Fig. 14 is a schematic circuit diagram of the pulse width detection module 13.

Fig. 15 is a schematic circuit diagram of the detection module 14.

Fig. 16 is a schematic circuit diagram of the band-pass filter module 15.

Fig. 17 is a schematic circuit diagram of the pulse frequency detection module 16.

Detailed Description

The detailed structure and operation principle of each circuit of the present invention will be described with reference to the accompanying drawings. The parameters indicated in the figures are preferred circuit parameters for the various embodiments.

EXAMPLE 1 Overall System Structure

As shown in fig. 1, the system has a single chip module 1, a high voltage energy storage module 2, a pulse width adjusting module 3, a pulse driving module 4, a modulation input module 5, a pulse display module 6, an indicator light driving module 7, a key input module 8, a front panel 9, an adaptive sampling module 10, a pulse peak current detection module 11, an adaptive peak adjusting module 12, a pulse width detection module 13, a detection module 14, a band-pass filter module 15, and a pulse frequency detection module 16.

Embodiment 2 Single chip module

As shown in fig. 2, the structure of the single chip module 1 is that a port VCC and a port GND of a single chip U1 are respectively connected to a +5V power supply and a digital ground, VCC is grounded through a capacitor C1 and a capacitor C2, a port VCC and a port GND of a level conversion chip U2 are respectively connected to a +5V power supply and a digital ground, a port VDD is connected to a +5V power supply through a capacitor C3, a port VEE is connected to a digital ground through a capacitor C4, a capacitor C5 is connected between a port C2+ and a port C2-, a capacitor C6 is connected between a port C1+ and a port C1-, a port T1IN and a port R1OUT are respectively connected to a port RXD and a port TXD of a single chip U1, a port R1IN and a port T1OUT are respectively connected to a 3 pin and a2 pin of a D interface J3, a 5 pin of a D interface J3 is connected to a digital ground, a model number STC15W408S of the single chip U1, a model of a level conversion chip U2 is a MAX interface 3, and a MAX;

the single chip microcomputer module 1 is responsible for the control work of the whole system, including receiving the key input state; controlling the state of an indicator light on the front panel; controlling the working state of the internal modulation and the external modulation input; displaying the current output pulse parameters; reading the peak current measured by the pulse peak current detection module; adaptively adjusting the attenuation amplitude of a pulse voltage signal of an H _ Vpulse port of a pulse width detection module according to the measured peak current, so that the high level of the pulse voltage signal of the L _ Vpulse port is equal to 5V; reading direct-current voltage which is output by the detection module and represents the pulse width of a pulse current signal output by the driver; according to interruption of a timer T0 provided by a pulse frequency detection module, self-adaptively adjusting the frequency division multiple, and calculating the repetition frequency of a pulse current signal output by a driver; correcting the output pulse current signal of the laser pulse driver according to the measured peak current, repetition frequency and pulse width of the output pulse current signal to form closed-loop control, and ensuring that the peak current, repetition frequency and pulse width of the output pulse current signal of the laser pulse driver are consistent with set values (note: when the driver works in an internal modulation mode, closed-loop control is carried out on the repetition frequency, and when the driver works in an external modulation mode, closed-loop control is not carried out on the repetition frequency); and the function of data communication between the single chip microcomputer and the upper computer is completed.

Embodiment 3 high-voltage energy storage module

As shown IN fig. 3, the structure of the high voltage energy storage module 2 is that a port GND of a switch control chip U3 is connected to an analog ground, a port VCC is connected to a +12V power supply, is connected to a port SWC through a resistor R2 and is connected to the analog ground through a capacitor C7, a port SWE is connected to a gate of an N-channel fet Q1 and is connected to the analog ground through a resistor R4, a port TCAP is connected to the analog ground through a capacitor C8, a port IPK is connected to a dotted terminal of a primary coil of a pulse transformer T1, is connected to a port DRVC through a resistor R3 and is connected to the +12V power supply through a resistor R1, the other end of the primary coil of the pulse transformer T1 is connected to a drain of the N-channel fet Q1, a source of the N-channel fet Q1 is connected to the analog ground, a port-V IN of the switch control chip U3 is connected to a port W of a digital potentiometer U4 and is connected to the analog ground through a resistor R5, a port, the port ADDR and the port VSS are respectively connected with a +5V power supply and a digital ground, the port EXT _ CAP is connected with the digital ground through a capacitor C9, the port SCL is connected with a port P20 of a singlechip U1 through a resistor R9, the port SDA is connected with a port P21 of a singlechip U1 through a resistor R8, and the port ADDR and the port VSS are respectively connected with a +5V power supply and a digital ground

The power supply is connected with a +5V power supply through a resistor R7, the like name of a secondary coil of a pulse transformer T1 is connected with the anode of a Schottky diode D1, the like name of the secondary coil of the pulse transformer T1 is connected with a port A of a digital potentiometer U4 through a resistor R6, the other end of the secondary coil of the pulse transformer T1 is connected with an analog ground, the cathode of the Schottky diode D1 serving as the output end of the high-voltage energy storage module 2 is marked as a port H _ Vpulse, and the Schottky diode D1 is connected with the analog ground through capacitors C10, C11, C12, C13 and C14 which are connected in parallel, the model of the switch control chip U3 is MC34063, and the model of the digital potentiometer U4 is AD;

the high-voltage energy storage module 2 controls the on and off of an N-channel field effect transistor Q1 according to a switching signal output by a port SWE of a switch control chip U3, energy is stored on a primary coil of a pulse transformer T1 when Q1 is switched on, the pulse transformer T1 couples energy to a secondary coil and transmits the stored energy into a capacitor C10-C14 when Q1 is switched off, the energy IN the capacitor is increasingly larger, the voltage on the positive pole of a Schottky diode D1 is increasingly higher, IN order to limit the voltage on the positive pole of the Schottky diode D1 to a fixed value, a feedback is introduced, the voltage is divided by a digital potentiometer U4+ a resistor R6 and a resistor R5 and then input into a port-V IN of the switch control chip U3, the voltage is compared with a standard 1.25V reference voltage inside the switch control chip U3, and when the divided voltage is less than 1.25V, the Q1 is IN a switch working state, the voltage on the positive electrode of the schottky diode D1 is continuously increased, and once the divided voltage is greater than 1.25V, the Q1 is always in a conducting state, so that the voltage on the positive electrode of the schottky diode D1 does not rise any more, and finally the voltage value output by the positive electrode of the schottky diode D1 is:

as can be seen from the above formula, the output voltage at the positive electrode of the schottky diode D1 depends on the resistance value of the digital potentiometer U4, so the output voltage of the high-voltage energy storage module 2 can be adjusted by controlling the resistance value of the digital potentiometer U4 through the single chip microcomputer U1, and in addition, since the voltage at the positive electrode of the schottky diode D1 is gradually increased after the power is turned on, the peak current of the output pulse gradually rises from 0 to a set value, thereby realizing the power-on surge protection function.

Embodiment 4 Key input Module

As shown in fig. 9, the key input module 8 has a structure that the input terminal of the inverted schmitt trigger U11A is connected to +5V power through the resistor R31 and the pin 1 of the socket J5, and is connected to the digital ground through the capacitor C22, the output terminal is connected to the port P15 of the single chip microcomputer U1, the input terminal of the inverted schmitt trigger U11B is connected to the port P16 of the single chip microcomputer U1 through the resistor R33 and the pin 2 of the socket J5, the +5V power through the resistor R32 and is connected to the digital ground through the capacitor C23, the output terminal is connected to the port P16 of the single chip microcomputer U1, the input terminal of the inverted schmitt trigger U11C is connected to the +5V power through the resistor R34 and is connected to the digital ground through the capacitor C24, the output terminal is used as one output terminal of the key input module 8 and is denoted as port Enable, the input terminal of the inverted schmitt trigger U11D is connected to the pin 37 through the resistor R5 and the pin 4 and the capacitor C8653, the output end of the INT0 of the singlechip U1, the input end of the reverse Schmitt trigger U11E is connected with a pin 5 of a plug socket J5 through a resistor R39, a +5V power supply through a resistor R38 and a digital ground through a capacitor C26, and the output end of the INT1 of the singlechip;

the key input module 8 is respectively connected with an output control switch 908, a pulse parameter selection button 905, a parameter adjusting knob 906 and a working mode button 912 on the front panel 9 through a socket J5, and converts the corresponding switch states into high and low levels to be output to a port Enable, a port P06 of a singlechip U1, a port INT0, a port INT1 and a port P07.

Example 5 modulation input Module

As shown in fig. 6, the modulation input module 5 has a structure that a port P25 of the single chip microcomputer U1 is connected to a gate of an N-channel fet Q3, a source of the N-channel fet Q3 is connected to an analog ground, a drain is connected to a pin 5 of the relay K1, a pin 4 of the relay K1 is connected to a +12V power supply, a pin 3 is connected to a port P24 of the single chip microcomputer U1, a pin 1 is used as an output terminal of the modulation input module 5 and is marked as a port Pulse _ Orig, a pin 2 is connected to an anode of a schottky diode D6, a cathode of a schottky diode D7 is connected to an output terminal of the operational amplifier U9A through a resistor R18, a cathode of the schottky diode D6 is connected to the +5V power supply, an anode of the schottky diode D7 is connected to a digital ground, an in-phase input terminal of the operational amplifier U9A is connected to an output terminal of the amplifier U9A through a resistor R17 and is connected to a digital ground through a resistor R16, an anode of the reverse phase input terminal of the schottky diode D4 is connected to a, the cathode of the Schottky diode D4 is connected with a +5V power supply, the anode of the Schottky diode D5 is connected with a digital ground, and the 2 pin of the socket J2 is connected with the digital ground;

the modulation input module 5 determines whether the waveform output from the port Pulse _ origin is from the port P24 of the single chip U1 or from the 1 pin of the socket J2 (the external modulation signal is connected to the socket J2 through the modulation input port 909 on the front panel 9) according to the high-low level input from the port P25 of the single chip U1, so that the conversion between the internal modulation mode and the external modulation mode is realized.

EXAMPLE 6 pulse Width adjustment Module

As shown in FIG. 4, the Pulse width modulation module 3 has a structure that the port D of the D flip-flop U5A is connected to the port Enable of the key input module 8, the port CLK is connected to the port Pulse _ origin of the modulation input module 5, the port CLR is connected to the +5V power supply, and the port CLR is connected to the port

The output end of the Pulse width adjusting module 3 is marked as a port Pulse _ LC, the port PR is connected with a port a of a digital potentiometer U6 and is connected with a digital ground through a capacitor C15, the port Q is connected with a tap end of a potentiometer W1, one fixed end of the potentiometer W1 is connected with a port W of the digital potentiometer U6, a port VDD and a port GND of the digital potentiometer U6 are respectively connected with a +5V power supply and a digital ground, a port ADDR and a port VSS are respectively connected with a +5V power supply and a digital ground, a port EXT _ CAP is connected with a digital ground through a capacitor C16, a port SCL is connected with a port P22 of the singlechip U1 through a resistor R12, a port SDA is connected with a port P23 of the singlechip U1 through a resistor R11, and a

the Pulse width adjusting module 3 is used for adjusting a square wave with a certain frequency output by the port Pulse _ origin of the modulation input module 5 into a signal with the same frequency and adjustable Pulse width, outputting the signal on the port Pulse _ LC, and adjusting the Pulse width of the Pulse signal output by the module by controlling the resistance value of the digital potentiometer U6 through the singlechip U1; the Enable signal input from the port Enable controls whether the pulse width adjusting module 3 outputs pulses, the module is allowed to normally output pulses when the Enable signal is at low level, and the output of the pulse width adjusting module 3 is constantly at low level when the Enable signal is at high level.

Example 7 pulse drive Module and adaptive sampling Module

As shown IN fig. 5, the Pulse driving module 4 has a structure that a tap of a potentiometer W2 is connected to a port Pulse _ LC of the Pulse width adjusting module 3, a fixed end of the potentiometer W2 is connected to analog ground through a capacitor C19 and connected IN parallel to a port IN a and a port IN B of a MOSFET driving chip U7, a port VCC and a port GND of the MOSFET driving chip U7 are respectively connected to +12V power and analog ground, ports EN a and EN B are connected to +12V power and connected to analog ground through a capacitor C17 and a capacitor C18 which are connected IN parallel to each other, ports OUT a and OUT B are connected to an anode of a diode D2 and connected to a base of a PNP transistor Q2, a collector of the PNP transistor Q2 is connected to analog ground, a cathode of a diode D2 is connected to an anode of a diode D3, a cathode of the diode D3 is connected to an emitter resistor R13 and one end of a capacitor C20, and the other ends of a resistor R6 and a capacitor C20 are connected together to a high-speed MOSFET U8 and connected to analog ground, after the pins 1, 3, 4 and 6 of the high-speed MOSFET chip U8 are connected together, the output end of the pulse driving module 4 is marked as a port L _ Apulse, the port D of the high-speed MOSFET chip U8 is connected with the port 2 of the socket J12, and the port 1 of the socket J12 is connected with the port H _ Vpulse; the model of the MOSFET driving chip U7 is IXDD404, and the model of the high-speed MOSFET chip U8 is DE275-201N 25A;

as shown in fig. 11, the adaptive sampling module 10 has a structure that a port P55 of a single chip microcomputer U1 is connected to a gate of an N-channel fet Q10, a source of the N-channel fet Q10 is connected to an analog ground, a drain of the N-channel fet Q10 is connected to a pin 5 of a relay K2, a pin 4 of a relay K2 is connected to a +12V power supply, a pin 3 is connected to a ground through a connection resistor Rs1, a pin 1 is connected to a port L _ Apulse of the pulse driving module 4, and a pin 2 is connected to a ground through a resistor Rs 2; the type of the relay K2 is HRS4H-S-DC 12V;

the Pulse driving module 4 and the adaptive sampling module 10 function to convert the voltage Pulse signal inputted from the port Pulse _ LC into a current Pulse signal with a peak value determined by the voltage level of H _ Vpulse as far as possible, and the current Pulse signal is connected to the current output port 914 on the front panel 9 through the socket J1. 4S of the high-speed MOSFET chip U8 are cascaded together and grounded through a sampling resistor Rs1 or Rs2, the sampling resistor selects Rs1 or Rs2 to be controlled by a relay K2, and the state of the relay K2 is controlled by a P55 port of a single chip microcomputer U1 to match output pulse currents with different sizes. The selection principle of the sampling resistor is as follows: the sampling resistor Rs2 of 0.3 ohm is used for starting, and if the voltage of P00 is larger than 4.5V under the condition that the sampling resistor is 0.3 ohm, the sampling resistor Rs1 of 0.03 ohm is switched to. If the P00 voltage is less than 0.45V at a sampling resistance of 0.03 ohms, the sampling resistance is switched back to 0.3 ohms.

EXAMPLE 8 pulse display Module

As shown in FIG. 7, the pulse display module 6 has a structure that the ports D0-D7 of the display screen U10 are respectively connected with the ports P10-P17 of the singlechip U1, and the ports EN, W/R and RS are respectively connected with the ports P26, P26 and S1 of the singlechip U1

And port

the display screen U10 is located on the front panel 9, is a 16 x2 integrated liquid crystal display screen, is controlled by the singlechip U1, and is used for displaying system working parameters.

Example 9 indicator light drive Module

As shown in fig. 8, the structure of the indicator lamp driving module 7 is that the gate of the N-channel fet Q4 is connected to the port P10 of the monolithic U1 through the resistor R20, the source is connected to digital, the drain is connected to 1 pin of the socket J4 through the resistor R19, the gate of the N-channel fet Q5 is connected to the port P11 of the monolithic U1 through the resistor R22, the source is connected to digital, the drain is connected to 2 pins of the socket J4 through the resistor R21, the gate of the N-channel fet Q6 is connected to the port P12 of the monolithic U1 through the resistor R24, the source is connected to digital, the drain is connected to 3 pins of the socket J4 through the resistor R23, the gate of the P-channel fet Q7 is connected to the port Enable 573 of the key input module 8 through the resistor R5, the source is connected to +5V power supply, and the drain is connected to 4 pins of the socket J4 through; the grid of the N-channel field effect transistor Q8 is connected with the grid of the P-channel field effect transistor Q9 and is connected with a port P25 of a singlechip U1 through a resistor R29, the source is connected with a digital ground, the drain is connected with a pin 5 of a socket J4 through a resistor R27, the source of the P-channel field effect transistor Q9 is connected with a +5V power supply, and the drain is connected with a pin 6 of a socket J4 through a resistor R28;

the indicator light driving module 7 is used for driving the current output indicator light 913, the pulse amplitude indicator light 902, the pulse width indicator light 903, the repetition frequency indicator light 904, the internal modulation indicator light 910 and the external modulation indicator light 911 on the front panel 9 respectively according to the port Enable and the logic states of the port P03, the port P04, the port P05 and the port P25 of the single chip microcomputer.

EXAMPLE 10 front Panel

As shown in fig. 10, the structure of the front panel 9 includes a display 901, a pulse amplitude indicator 902, a pulse width indicator 903, a repetition frequency indicator 904, a pulse parameter selection button 905, a parameter adjustment knob 906, a power switch 907, an output control switch 908, a modulation input port 909, an internal modulation indicator 910, an external modulation indicator 911, an operation mode button 912, a current output indicator 913, and a current output port 914, wherein the display 901 is a display U10 of the pulse display module 6, the model is an LCD1602, the pulse amplitude indicator 902, the pulse width indicator 903, the repetition frequency indicator 904, the current output indicator 913, and the internal modulation indicator 910 are 5 light emitting diodes, the anodes thereof are all connected to a +5V power source, the cathodes thereof are respectively connected to the 1 pin, the 2 pins, the 3 pins, the 4 pins, and the 5 pins of the socket J4 of the indicator driving module 7, the external modulation indicator 911 is also a light emitting diode, the anode of the external modulation indicator is connected with the 6 pin of the socket J4 in the indicator driving module 7, the cathode of the external modulation indicator is connected with the digital ground, one pin of the pulse parameter selection button 905 is connected with the 1 pin of the socket J5 in the key input module 8, the other pin is connected with the digital ground, the parameter adjusting knob 906 is a rotary encoder, the 1 pin of the rotary encoder is connected with the 4 pin of the socket J5 in the key input module 8, the 2 pin of the rotary encoder is connected with the 5 pin of the socket J5 in the key input module 8, the common end of the 3 pins of the rotary encoder is connected with the digital ground, the power switch 907 is a main switch for electrifying the whole device, the output control switch 908 is a key switch, one pin of the key switch is connected with the 3 pin of the socket J5 in the key input module 8, the other pin is connected with the digital ground, the modulation input port 909 is a SMA female connector, the anode, the negative pole is connected with the pin 2 of the socket J2 in the modulation input module 5, one pin of the working mode button 912 is connected with the pin 2 of the socket J5 in the key input module 8, the other pin is connected with the digital ground, the current output port 914 is also an SMA female connector, the positive pole of the SMA female connector is connected with the pin 1 of the socket J1 in the pulse driving module 4, and the negative pole of the SMA female connector is connected with the pin 2 of the socket J1 in the pulse driving module 4.

Embodiment 11 pulse Peak Current detection Module

As shown in fig. 11, the pulse peak current detection module 11 has a structure that a port 4 of an amplifier U12A is grounded, a port 3 is connected to L _ Apulse, a port 8 is connected to a +5V power supply, a port 1 is connected to an input terminal of a D8, an output terminal of a D8 is connected to a capacitor C27 and grounded, a port 2 is connected to R42 and grounded, and an output terminal of a diode D8 is connected to a port P00 of a monolithic computer U1;

the pulse peak current detection module 11 realizes a function of detecting a peak current of a pulse current signal output by the driver. The working principle is as follows: the pulse current signal outputted by the driver is converted into a pulse voltage signal through a sampling resistor Rs1 or Rs2 in the pulse driving module 4, and is inputted into the pulse peak current detection module 11 through a port L _ Apulse. The pulse peak current detection module 11 converts the peak value of the pulse voltage signal into a dc signal and outputs the dc signal on the port P00. The voltage value on the port P00 is obtained by utilizing the A/D conversion function of the port P0.0 of the singlechip U1, and the voltage value is divided by the resistance value of the sampling resistor, so that the size of the peak value of the actual output pulse output current signal can be obtained.

Example 12 band-pass Filter Module, adaptive Peak adjustment Module, pulse Width detection Module, and Detector Module

As shown in fig. 13, the adaptive peak adjustment module 12 has a structure in which a VDD port and a GND port of U13 are respectively connected to a +5V power supply and an analog ground, a port ADDR is connected to a +5V power supply, a port SCL is connected to a port P02 of a chip U1 through a resistor R44, a port SDA is connected to a port P27 of a chip U1 through a resistor R45, and a port

A +5V power supply connected via a resistor R46 and an EXT portCAP is grounded through a capacitor C28, a port VSS is grounded, a port W is connected with a port 6 of a U12B and is grounded through R47, a port 5 of the U12B is connected with L _ Apulse, and a port A is connected with a port 7 of the U12B and then serves as an output end of the self-adaptive peak value adjusting module 12 and is marked as a port H _ Apulse;

as shown IN fig. 14, the pulse width detection module 13 has a structure that a port H _ Apulse is connected to a port 5 of U14B, a port 2 of U14A, a VCC port and a VSS port of U15 are respectively connected to a +5V power supply and a-5V power supply, a port S1 is grounded, a port S3 is connected to Sine1k, a port IN3 is connected to a port 7 of U14 3, a port 8 of U14 3 is connected to a +5V power supply, a positive electrode of D3 is grounded, a negative electrode of D3 is connected to a port 3 of U14 3, a port 6 of U14 3 is connected to a +5V power supply through a resistor R3, a port 4 of U14 3 is grounded, a port 1 is connected to the IN3, a port D3 of U3 and a port D3 are connected to R3 and grounded through a capacitor R3, a positive electrode connected to the port 3 of U16, a terminal 3 is connected to the ground through a capacitor R3, a terminal 3 is connected to the ground through a capacitor R3, a terminal 3 and a terminal 3, the port 6 is connected with the anode of a capacitor C31 through R53, and is connected with the port 7 of a U16B through a capacitor C32, the port 7 of the U16B is connected with the anode of a capacitor C31 through a resistor R54, and the output end of the pulse width detection module 13 is marked as a port Sined;

as shown in fig. 15, the structure of the detector module 14 includes that a port RMS of U17 is connected to a port IBFOUT and a port ibulin "through a capacitor C37, the port ibulin + is connected to a port sine through a capacitor C36, the port IGND is connected to a port IGND through a resistor R55, the port OGND is grounded, a port OUT is grounded through a capacitor C35, the port obin +, the port CAVG is connected to a +5V power supply through a capacitor C34, the port CCF is connected to a +5V power supply through a capacitor C33, the port VCC, the port IBUFV +, the port OBUFV + are connected to a +5V power supply, the port OBUFOUT and the port OBUFIN-are connected to a port P01 of a monolithic computer U1, and the port VEE is connected to a-5V power supply;

as shown in fig. 16, the structure of the band pass filter module 15 includes that port 4 of U18A is connected to a-5V power supply, port 8 is connected to a +5V power supply, port 2 is connected to port 1 by connecting to R58, is connected to port P41 of the monolithic computer U1 by connecting to capacitor C38 and R56, the common point of capacitor C38 and R56 is grounded via R57 and is connected to port 1 by C39, port 1 is connected to port 6 of U18 by R59 and via C40, port 6 of U18B is connected to port 7 by R61, the common point of R59 and capacitor C40 is connected to port 7 by C41 and is grounded by connecting to R60, and the output terminal of port 7 as the band pass filter module 15 is denoted as port Sine1 k;

the pulse width of the pulse current signal output by the pulse driver of the semiconductor laser is very narrow and can reach about 20ns at least, so that the pulse width can not be detected by adopting a common direct measurement method. The invention converts the pulse width of the pulse current signal output by the driver into a direct current voltage signal which changes in a linear relation with the pulse width of the pulse current signal output by the driver through the mutual cooperation of the band-pass filtering module 15, the self-adaptive peak value adjusting module 12, the pulse width detecting module 13 and the wave detecting module 14, thereby realizing the function of detecting the pulse width of the pulse current signal output by the driver. The working principle is as follows: an input signal of the band-pass filtering module 15 is a square wave with the frequency of 1kHz output by a port P41 of the single chip microcomputer U1, and an output signal on a port Sine1k after being processed by the band-pass filtering module is Asin (2 pi ft), wherein a ═ 4.6V is a sinusoidal signal amplitude, and f ═ 1kHz is a sinusoidal signal frequency; the single chip microcomputer U1 adaptively adjusts the amplification factor of the pulse voltage signal of the port L _ Apulse of the adaptive peak value adjusting module 12 according to the peak current measured by the pulse peak value current detecting module 11, so that the high level of the pulse voltage signal on the port H _ Apulse is equal to 5V, and then the high level is compared with the 2.5V reference voltage signal to obtain a standard pulse square wave signal with the pulse width equal to the half-height width of the pulse current signal output by the driver, and after the pulse square wave signal and the Sine signal Asin (2 pi ft) on the port Sine1k are processed by the pulse width adjusting detecting module 13, the expression of the obtained signal on the output port Sine D is 5Adsin (2 pi ft), wherein d is the duty ratio of the pulse square wave signal; the signal of the port Sined is input into the detection module 14, and the direct current voltage on the output port P01 is obtained

The voltage value on the port P01 is obtained by utilizing the A/D conversion function of the port P0.1 of the singlechip U1, the duty ratio D of the pulse square wave signal is calculated, and the pulse width of the pulse current signal output by the laser pulse driver can be calculated according to the repetition frequency of the output pulse current signal.

Example 13 pulse frequency detection Module

As shown in fig. 17, the pulse frequency detection module 16 has a structure that the port RST of U19 is grounded, the port CLK is connected to the port H _ Apulse of the monolithic computer, the port I0 of U20, the port Q1 is connected to the port I1 of U20, the port Q2 is connected to the port I2 of U20, the port Q3 is connected to the port I3 of U20, the port Q4 is connected to the port I4 of U20, the port Q5 is connected to the port I5 of U20, the port Q6 is connected to the port I6 of U20, the port Q7 is connected to the port I7 of U20, the port a of U20 is connected to the port P35 of monolithic computer U1, the port B of U20 is connected to the port P36 of monolithic computer U1, the port C of U20 is connected to the port P37 of monolithic computer U1, the port is grounded, and the port P34 of monolithic computer U1 is connected;

the pulse peak frequency detection module 16 realizes the function of detecting the repetition frequency of the pulse current signal output by the driver. The working principle is as follows: taking the pulse voltage signal on the port H _ Apulse with adjusted amplitude as input, dividing the frequency of the signal by a counter CD4040 to obtain 2 times of the input signalⁿ(n is 1-12) the 12 signals after frequency division, then the data selector 74HC151 is used for selecting the original signal and one of the output ends of Q1-Q7 of CD4040 as the output signal on the port P34, and the output signal is input to the timer interrupt T0 of the singlechip U1, so that the frequency measurement is realized; the condition that the data selector selects the input signal is that the frequency division multiple is increased as long as the measuring frequency of the signal on the port P34 is higher than 8kHz until the measuring frequency of the signal on the port P34 is lower than 8kHz, and the repetition frequency of the pulse current signal output by the laser pulse driver can be obtained by reading the frequency and multiplying the frequency by the frequency division multiple.

EXAMPLE 14 working procedure of the invention

Referring to fig. 1-17, the working process of the present invention is as follows: the pulse parameter selection button 905 selects output pulse parameters to be adjusted, the output pulse parameters are displayed by the display screen 901 at the speed of 30 frames per second, the set values of the parameters are adjusted by the parameter adjusting knob 906, two working modes of internal modulation and external modulation are selected by the working mode button 912, and the on-off state is converted into high and low level signals to be sent to the singlechip module 1 through the key input module 8; when the pulse parameter selection button 905 is pressed to adjust the pulse amplitude, the pulse width and the repetition frequency, the single chip microcomputer U1 controls the output of the indicator lamp driving module 6 through the port P03, the port P04 and the port P05 according to the currently adjusted parameters, so that the pulse amplitude indicator lamp 907, the pulse width indicator lamp 908 and the repetition frequency indicator lamp 909 on the front panel 9 are turned on and off as required to prompt a user which parameter is currently adjusted; when the working mode button 912 is pressed to select the working mode, the singlechip U1 controls the internal modulation indicator lamp 910 and the external modulation indicator lamp 911 to be turned on and off as required through the port P25 according to the current working mode so as to prompt a user to work in the internal modulation mode or the external modulation mode currently; the output control switch 908 determines whether to output a current Pulse on the current output port 914, the switch state is converted into a high-low level on the port Enable through the key input module 8, the high-low level controls whether the port Pulse _ LC of the Pulse width modulation module 3 outputs a Pulse voltage signal, that is, whether to output a Pulse current signal on the load port 914, and in addition, the port Enable also controls the on-off of the current output indicator lamp 913 through the indicator lamp driving module 7 to prompt the user whether to output a Pulse current signal currently; the singlechip U1 compares the actual peak current fed back by the pulse peak current detection module with a pulse peak current set value, adjusts a digital potentiometer U4 in the high-voltage energy storage module 2 through a PID algorithm according to the difference value of the actual value and the set value, changes the voltage of the anode of the Schottky diode D1 and ensures that the pulse current peak value output by the driver is equal to the set value; the singlechip U1 compares the actual Pulse half-height width fed back by the Pulse width detection module and the detection module, and adjusts the digital potentiometer U6 in the Pulse width adjustment module 3 through PID algorithm according to the difference value between the actual value and the set value, changes the Pulse width of the output Pulse of the port Pulse _ LC, and the Pulse width determines the Pulse width of the output Pulse current signal of the final driver, thereby ensuring that the Pulse width of the output Pulse current signal of the driver is equal to the set value; the singlechip U1 controls the high and low level of the port P25 according to the input state of the working mode button 912, and further determines whether the current working is in an internal modulation mode or an external modulation mode through the modulation input module 5; if the current work is in the internal modulation mode, the single chip microcomputer U1 compares the repetition frequency of the actual output signal fed back by the pulse frequency detection module with a repetition frequency set value, and adjusts the frequency of the standard square wave output by the port P24 of the single chip microcomputer U1 through a PID algorithm according to the difference value between the actual value and the set value, wherein the frequency determines the repetition frequency of the final output current pulse, so that the repetition frequency of the pulse current signal output by the driver is ensured to be equal to the set value; if the external modulation mode is currently operating, the repetition frequency of the final output current pulses depends on the frequency of the external modulation signal input at the modulation input port 909, without closed loop control.

Claims

1. A semiconductor laser pulse driver with multiple closed-loop control is structurally provided with a pulse display module (6) and a front panel (9), and is characterized by further comprising a single chip microcomputer module (1), a high-voltage energy storage module (2), a pulse width adjusting module (3), a pulse driving module (4), a modulation input module (5), an indicator lamp driving module (7), a key input module (8), a self-adaptive sampling module (10), a pulse peak current detection module (11), a self-adaptive peak adjusting module (12), a pulse width detection module (13), a detection module (14), a band-pass filtering module (15) and a pulse frequency detection module (16);

the structure of the single chip microcomputer module (1) is that a port VCC and a port GND of a single chip microcomputer U1 are respectively connected with a +5V power supply and a digital ground, VCC is grounded through a capacitor C1 and a capacitor C2, the port VCC and the port GND of a level conversion chip U2 are respectively connected with the +5V power supply and the digital ground, a port VDD is connected with the +5V power supply through a capacitor C3, a port VEE is connected with the digital ground through a capacitor C4, a capacitor C5 is connected between the port C2+ and the port C2-, a capacitor C6 is connected between the port C1+ and the port C1-, a port T1IN and a port R1OUT are respectively connected with a port RXDD and a port TXDD of a single chip microcomputer U1, a port R1IN and a port T1OUT are respectively connected with a pin 3 and a pin 2 of a D-shaped interface J3, a pin 5 of the D-shaped interface J3 is connected with the digital ground, the model number of the single chip U1 is STC15W S, the level conversion chip U2 is a;

the high-voltage energy storage module (2) is structurally characterized in that a port GND of a switch control chip U3 is connected with an analog ground, a port VCC is connected with a +12V power supply, a port SWC is connected with a resistor R2, and the port SWC is connected with an analog ground through a capacitor C7The ground, the port SWE connects the grid of N-channel FET Q1 and connects the analog ground through resistor R4, the port TCAP connects the analog ground through capacitor C8, the port IPK connects the dotted terminal of the primary coil of pulse transformer T1, connects port DRVC through resistor R3 and connects the +12V power supply through resistor R1, the other terminal of the primary coil of pulse transformer T1 connects the drain of N-channel FET Q1, the source of N-channel FET Q1 connects the analog ground, the port-V IN of switch control chip U3 connects the port W of digital potentiometer U4 and connects the analog ground through resistor R5, the port VDD and the port GND of digital potentiometer U4 connect the +5V power supply and the digital ground respectively, the port ADDR and the port VSS connect the +5V power supply and the digital ground respectively, the port EXT _ CAP connects the digital ground through capacitor C9, the port SCL connects the port P6 of single chip U1 through resistor R9, the port P1 of SDA connects the port 1 through resistor R3527, port(s)

The power supply is connected with a +5V power supply through a resistor R7, the like name of a secondary coil of a pulse transformer T1 is connected with the anode of a Schottky diode D1, the like name of the secondary coil of the pulse transformer T1 is connected with a port A of a digital potentiometer U4 through a resistor R6, the other end of the secondary coil of the pulse transformer T1 is connected with an analog ground, the cathode of the Schottky diode D1 serving as the output end of a high-voltage energy storage module (2) is marked as a port H _ Vpulse, and the Schottky diode D1 is connected with the analog ground through capacitors C10, C11, C12, C13 and C14 which are connected in parallel, the model of the switch control chip U3 is 34063, and the model of the digital potentiometer U4 is;

the key input module (8) has the structure that the input end of an inverted Schmitt trigger U11A is connected with a +5V power supply through a resistor R31 through a pin 1 of a socket J5, and is connected with a digital ground through a resistor R30, the output end of the inverted Schmitt trigger U11B is connected with a port P06 of a singlechip U1, the input end of the inverted Schmitt trigger U11B is connected with the +5V power supply through a resistor R32 through a pin 2 of a socket J5 of a resistor R33 and is connected with the digital ground through a capacitor C23, the output end of the inverted Schmitt trigger U11 is connected with a port P07 of a singlechip U1, the input end of the inverted Schmitt trigger U11C is connected with the digital ground through a pin 3 of a resistor R35 through a socket J5, the +5V power supply through a resistor R34 and is connected with the digital ground through a capacitor C24, the output end of the key input end of the inverted Schmitt trigger U11D is used as one output end of the key input module (8) and is connected with the digital ground through a resistor R84, the output end of the INT0 of the singlechip U1, the input end of the reverse Schmitt trigger U11E is connected with a pin 5 of a plug socket J5 through a resistor R39, a +5V power supply through a resistor R38 and a digital ground through a capacitor C26, and the output end of the INT1 of the singlechip;

the structure of the modulation input module (5) is that a port P25 of a singlechip U1 is connected with a grid electrode of an N-channel field effect tube Q3, a source electrode of the N-channel field effect tube Q3 is connected with an analog ground, a drain electrode is connected with a pin 5 of a relay K1, a pin 4 of the relay K1 is connected with a +12V power supply, a pin 3 is connected with a port P24 of the singlechip U1, a pin 1 is used as an output end of the modulation input module (5) and is marked as a port Pulse _ Orig, a pin 2 is connected with an anode of a Schottky diode D6 and a cathode of the Schottky diode D7 and is connected with an output end of an operational amplifier U9A through a resistor R18, a cathode of the Schottky diode D6 is connected with the +5V power supply, an anode of the Schottky diode D7 is connected with a digital ground, a non-inverting input end of the operational amplifier U9 is connected with an output end of the operational amplifier U9A through a resistor R17 and is connected with a digital ground through a resistor R16, an anode of the Schottky diode D4 and a cathode of the Schottky diode D, the cathode of the Schottky diode D4 is connected with a +5V power supply, the anode of the Schottky diode D5 is connected with a digital ground, and the 2 pin of the socket J2 is connected with the digital ground;

the structure of the Pulse width adjusting module (3) is that a port D of the D trigger U5A is connected with a port Enable of the key input module (8), a port CLK is connected with a port Pulse _ origin of the modulation input module (5), a port CLR is connected with a +5V power supply, and a port

The output end of the Pulse width adjusting module (3) is marked as a port Pulse _ LC, the port PR is connected with a port A of a digital potentiometer U6 and is connected with a digital ground through a capacitor C15, a port Q is connected with a tapping end of a potentiometer W1, one fixed end of a potentiometer W1 is connected with a port W of a digital potentiometer U6, a port VDD and a port GND of the digital potentiometer U6 are respectively connected with a +5V power supply and a digital ground, a port ADDR and a port VSS are respectively connected with a +5V power supply and a digital ground, a port EXT _ CAP is connected with a digital ground through a capacitor C16, a port SCL is connected with a port P22 of a singlechip U1 through a resistor R12, and a port SDA is connected with a port P22 of the1, port P23, port

the Pulse driving module (4) is structurally characterized IN that a tap of a potentiometer W2 is connected with a port Pulse _ LC of the Pulse width adjusting module (3), one fixed end of a potentiometer W2 is connected with an analog ground through a capacitor C19 and is connected with a port IN A and a port IN B of a MOSFET driving chip U7 IN parallel, a port VCC and a port GND of the MOSFET driving chip U7 are respectively connected with a +12V power supply and the analog ground, ports EN A and EN B are connected with the +12V power supply and are connected with the analog ground through a capacitor C17 and a capacitor C18 which are mutually connected IN parallel, a port OUT A and a port OUT B are connected with an anode of a diode D2 and are connected with a base of a PNP triode Q2, a collector of the PNP triode Q2 is connected with the analog ground, a cathode of the diode D2 is connected with an anode of a diode D3, a cathode of the diode D3 is connected with an emitter of a PNP triode Q2 and is connected with one end of a resistor R13 and one end of a capacitor C20, and the other end of a resistor R737, after the pins 1, 3, 4 and 6 of the high-speed MOSFET chip U8 are connected together, the output end of the pulse driving module (4) is marked as a port L _ Apulse, a port D of the high-speed MOSFET chip U8 is connected with a port 2 of a socket J12, and a port 1 of a socket J12 is connected with a port H _ Vpulse; the model of the MOSFET driving chip U7 is IXDD404, and the model of the high-speed MOSFET chip U8 is DE275-201N 25A;

the self-adaptive sampling module (10) is structurally characterized in that a port P55 of a single chip microcomputer U1 is connected with a grid electrode of an N-channel field effect tube Q10, a source electrode of an N-channel field effect tube Q10 is connected with an analog ground, a drain electrode of the N-channel field effect tube Q10 is connected with a pin 5 of a relay K2, a pin 4 of a relay K2 is connected with a +12V power supply, a pin 3 is connected with the ground through a connection resistor Rs1, a pin 1 is connected with a port L _ Apulse of a pulse driving module (4), and a pin 2 is connected with the ground; the type of the relay K2 is HRS4H-S-DC 12V;

the pulse display module (6) has the structure that the ports D0-D7 of the display screen U10 are respectively connected with the ports P10-P17 of the singlechip U1, and the ports EN, W/R and RS are respectively connected with the ports P26, P26 and S of the singlechip U1

And port

the structure of the indicator lamp driving module (7) is that the grid of an N-channel field effect tube Q4 is connected with a port P03 of a singlechip U1 through a resistor R20, the source is connected with a digital ground, the drain is connected with a 1 pin of a socket J4 through a resistor R19, the grid of the N-channel field effect tube Q5 is connected with a port P04 of a singlechip U1 through a resistor R22, the source is connected with a digital ground, the drain is connected with a2 pin of a socket J4 through a resistor R21, the grid of the N-channel field effect tube Q6 is connected with a port P05 of a singlechip U1 through a resistor R24, the source is connected with a digital ground, the drain is connected with a 3 pin of a socket J4 through a resistor R23, the grid of the P-channel field effect tube Q7 is connected with a port Enable of a key input module (8) through a resistor R26, the source is connected with a +5V power supply; the grid of the N-channel field effect transistor Q8 is connected with the grid of the P-channel field effect transistor Q9 and is connected with a port P25 of a singlechip U1 through a resistor R29, the source is connected with a digital ground, the drain is connected with a pin 5 of a socket J4 through a resistor R27, the source of the P-channel field effect transistor Q9 is connected with a +5V power supply, and the drain is connected with a pin 6 of a socket J4 through a resistor R28;

the structure of the front panel (9) comprises a display screen 901, a pulse amplitude indicator lamp 902, a pulse width indicator lamp 903, a repetition frequency indicator lamp 904, a pulse parameter selection button 905, a parameter adjusting knob 906, a power switch 907, an output control switch 908, a modulation input port 909, an internal modulation indicator lamp 910, an external modulation indicator lamp 911, an operating mode button 912, a current output indicator lamp 913 and a current output port 914, wherein the display screen 901 is a display screen U10 in a pulse display module (6) and is of the type LCD1602, the pulse amplitude indicator lamp 902, the pulse width indicator lamp 903, the repetition frequency indicator lamp 904, the current output indicator lamp 913 and the internal modulation indicator lamp 910 are 5 light emitting diodes, the anodes of the 5V power supplies are connected, the cathodes of the 5V power supplies are respectively connected with a pin 1, a pin 2, a pin 3, a pin 4 and a pin 5 of a socket J4 in an indicator lamp driving module (7), the external modulation indicator 911 is also a light emitting diode, the anode of the external modulation indicator is connected with 6 pins of a socket J4 in the indicator driving module (7), the cathode of the external modulation indicator is connected with a digital ground, one pin of the pulse parameter selection button 905 is connected with 1 pin of a socket J5 in the key input module (8), the other pin is connected with the digital ground, the parameter adjusting knob 906 is a rotary encoder, the 1 pin of the rotary encoder is connected with 4 pins of a socket J5 in the key input module (8), the 2 pins of the rotary encoder are connected with 5 pins of a socket J5 in the key input module (8), the 3 pins of the rotary encoder are connected with the digital ground in common, the power switch 907 is a master switch for electrifying the whole device, the output control switch is a key switch, one pin of the key switch 908 is connected with 3 pins of a socket J5 in the key input module (8), the other pin is connected with the digital ground, the modulation input port 909 is an SMA master, the anode of the current output port 914 is connected with 1 pin of a socket J2 in the modulation input module (5), the cathode of the current output port is connected with 2 pins of a socket J2 in the modulation input module (5), one pin of the working mode button 912 is connected with 2 pins of a socket J5 in the key input module (8), the other pin is connected with the digital ground, the current output port 914 is also an SMA female connector, the anode of the current output port is connected with 1 pin of a socket J1 in the pulse driving module (4), and the cathode of the current output port is connected with 2 pins of a socket J1 in the pulse driving module (4).

The pulse peak current detection module (11) has the structure that a port 4 of an amplifier U12A is grounded, a port 3 is connected with a port L _ Apulse, a port 8 is connected with a +5V power supply, a port 1 is connected with an input end of a D8, an output end of the D8 is connected with a capacitor C27 and grounded, a port 2 is connected with an R42 and grounded, and an output end of a diode D8 is connected with a port P00 of a single chip microcomputer U1;

the self-adaptive peak value adjusting module (12) has the structure that a VDD port and a GND port of U13 are respectively connected with a +5V power supply and an analog ground, a port ADDR is connected with a +5V power supply, a port SCL is connected with a port P02 of a singlechip U1 through a resistor R44, a port SDA is connected with a port P27 of a singlechip U1 through a resistor R45, and the port SDA is connected with a port P27 of the singlechip U1

A +5V power supply via a resistor R46, a port EXT _ CAP connected to ground via a capacitor C28, a port VSS connected to ground, a port W connected to a port 6 of U12B, anThe output end of the adaptive peak value adjusting module (12) is marked as a port H _ Apulse after the output end is connected with the ground through R47, the port 5 of U12B is connected with L _ Apulse, and the port A is connected with the port 7 of U12B;

the pulse width detection module (13) is structured IN such a way that a port H _ Apulse is connected with a port 5 of a U14B, the port 2 of the U14A is connected, a VCC port and a VSS port of a U15 are respectively connected with a +5V power supply and a-5V power supply, a port S1 is grounded, a port S3 is connected with a Sine1k, a port IN3 is connected with a port 7 of the U14 3, a port 8 of the U14 3 is connected with the +5V power supply, a positive electrode of the D3 is grounded, a negative electrode of the D3 is connected with a port 3 of the U14 3, the port 6 of the U14 3 is connected with the port 6 of the U14 3 and is connected with the +5V power supply through a resistor R3, a port 4 of the U14 3 is grounded, the port 1 is connected with the port IN3 of the U3, a port D3 and a port D3 of the U3 are connected with the R3 and are grounded through the C3, a port 3 of the U16 is grounded, a port 3 is connected with the-5V power supply, a port 4 is connected with the-5V power supply, a port, a positive electrode of the C72, the port 6 is connected with the anode of a capacitor C31 through R53, and is connected with the port 7 of a U16B through a capacitor C32, the port 7 of the U16B is connected with the anode of a capacitor C31 through a resistor R54, and the output end of the pulse width detection module (13) is marked as a port Sined;

the structure of the detection module (14) is that a port RMS of U17 is connected with a port IBFOUT and a port IBUFIN through a capacitor C37, the port IBUFIN + is connected with a port IGND through a capacitor C36 and a resistor R55, the port OGND is grounded, a port OUT is grounded through a capacitor C35 and a port OBUFIN +, the port CAVG is connected with a +5V power supply through a capacitor C34, the port CCF is connected with a +5V power supply through a capacitor C33, the port VCC, the port IBUFV +, the port OBUFV + are connected with a +5V power supply, the port OBUFOUT and the port OBUFIN-are connected with a port P01 of a singlechip U1, and the port VEE is connected with a-5V power supply;

the structure of the band-pass filtering module (15) comprises that a port 4 of a U18A is connected with a-5V power supply, a port 8 is connected with a +5V power supply, a port 2 is connected with a port 1 through a connector R58, is connected with a port P41 of a singlechip U1 through a capacitor C38 and a connector R56, a common point of a capacitor C38 and a capacitor R56 is grounded through a connector R57 and is connected with the port 1 through a connector C39, the port 1 is connected with a port 6 of a U18 through a connector R59 and a connector C40, the port 6 of the U18B is connected with a port 7 through a connector R61, the common point of the R59 and the capacitor C40 is connected with the port 7 through a connector C41 and is grounded through a connector R60, and the port 7 is used as an;

the pulse frequency detection module (16) has the structure that a port RST of U19 is grounded, a port CLK is connected with a port H _ Apulse and connected with a port I0 of U20, a port Q1 is connected with a port I1 of U20, a port Q2 is connected with a port I2 of U20, a port Q3 is connected with a port I3 of U20, a port Q4 is connected with a port I4 of U20, a port Q5 is connected with a port I5 of U20, a port Q6 is connected with a port I6 of U20, a port Q7 is connected with a port I7 of U20, a port A of U20 is connected with a port P35 of U1, a port B of U20 is connected with a port P36 of U1, a port C of U36 is connected with a port P36 of U36, and a port ground is connected with a port P36 of Z singlechip U36.

2. A semiconductor laser pulse driver with multiple closed-loop control as claimed in claim 1 wherein the parameters of each element are: 47uF, 100nF/200V Dacron, 100pF, 10nF/150V Dacron, 10pF, 4.7uF, 1nF, 470uF/200V Dacron, 4.7nF/150V Dacron, 47nF, 330nF, 470uF, 39nF, 220nF, 10uF, 3.3uF, 470nF, 3.520nF, 470nF, 520nF, 5200 SB, the types of the diode D2, the diode D3 and the diode D8 are all 1N4148, the types of the Schottky diodes D4-Schottky diodes D7 are all 1N5817, the types of the voltage-stabilizing diode D10 are 2.5V in voltage-stabilizing value, the types of the N-channel field effect tube Q3-N-channel field effect tube Q6, the types of the N-channel field effect tube Q8 and the N-channel field effect tube Q10 are all 2SK1482, the types of the P-channel field effect tube Q7 and the P-channel field effect tube Q9 are all 2SJ507, the type of the resistor R1 is 0.3 omega, the types of the resistor R2-resistor R4 are all 100 omega, the type of the resistor R14, the resistor R20, the type of the resistor R22, the type of the resistor R24, the type of the resistor R26, the resistor R29, the type of the resistor R30, the resistor R32, the type of the resistor R34, the resistor R34 and the type of the resistor R34, the resistor 34 and the type of the resistor 34, the resistor R19, the resistor R21, the resistor R23, the resistor R25, the resistor R27 and the resistor R28 are all 300 omega, the resistor R13 is 400 omega, the resistor R11, the resistor R12, the resistor R16, the resistor R8, the resistor R9, the resistor R44 and the resistor R45 are all 5.1k omega, the resistor R17 is 51k omega, the resistor R6 is 9.1k omega precision resistor, the resistor R42 is 1M omega, the resistor R49 is 6.5k omega, the resistor R51 is 15k omega, the resistor R50 is 4.5k omega, the resistor R54 is 6k omega, the resistor R52 is 3k omega, the resistor R52 is 1.8k omega, the resistor R52 is 2k, the resistor R52 is 10M omega, the resistors R52 and R52 are all 125k omega, the resistor R52 is 600 omega, the resistor R72 is 72 k, the resistor R52 k is 2k, the TLC, the resistor R52 is 10M omega, the TLC 52, the amplifier is a TLC, the resistor R52, the amplifier is a TRX 52, the TLC 72, the type TRX 52, the TRX 52 is a TRX 52, the TRX 52, models of an inverse Schmitt trigger U11A-an inverse Schmitt trigger U11E are SN7414N, models of an operational amplifier U14A and an operational amplifier U14B are AD826, models of an operational amplifier U16A, an operational amplifier U16B, an operational amplifier U18A and an operational amplifier U18B are AD822, a model of a D trigger U5A is 74S74, a model of a pulse transformer T1 is PA25 2547NL, and models of a relay K1 and a relay K2 are HRS4H-S-DC 12V.