CN112988653B - Data processing circuit, device and method - Google Patents
Data processing circuit, device and method Download PDFInfo
- Publication number
- CN112988653B CN112988653B CN201911290285.6A CN201911290285A CN112988653B CN 112988653 B CN112988653 B CN 112988653B CN 201911290285 A CN201911290285 A CN 201911290285A CN 112988653 B CN112988653 B CN 112988653B
- Authority
- CN
- China
- Prior art keywords
- data
- data packet
- packet
- circuit
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title abstract description 13
- 238000003672 processing method Methods 0.000 claims abstract description 12
- 230000005540 biological transmission Effects 0.000 claims description 21
- 230000004048 modification Effects 0.000 claims description 21
- 238000012986 modification Methods 0.000 claims description 21
- 230000004044 response Effects 0.000 claims description 9
- 238000004458 analytical method Methods 0.000 claims description 3
- 230000003139 buffering effect Effects 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 15
- 230000006870 function Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000004590 computer program Methods 0.000 description 3
- 230000009365 direct transmission Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000013528 artificial neural network Methods 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The embodiment of the disclosure discloses a data processing circuit, a data processing device and a data processing method. Wherein the data processing circuit comprises: a data packet receiving circuit and a data packet output circuit; the data packet receiving circuit is used for receiving a source data packet and determining a first sending direction of the source data packet according to a target chip address of a source packet head in the source data packet; the data packet output circuit is used for transmitting the source data packet according to the first transmitting direction. By the method, the technical problems of increased chip cost, affected chip formation and high difficulty in chip layout and wiring caused by using the network on chip as a relay for transmitting data in the prior art are solved.
Description
Technical Field
The present disclosure relates to the field of data processing, and in particular, to a data processing circuit, apparatus, and method.
Background
With the development of science and technology, human society is rapidly entering the intelligent era. The chip is a basic stone for data processing, and fundamentally determines the capability of people for processing the data. From the application field, the chip has two main routes: one is a general chip route, such as a central processing unit (Central Processing Unit, CPU) or the like, which provides great flexibility but is relatively low in terms of effective algorithms in processing domain-specific algorithms; the other is a special chip route, such as tensor processor (Tensor Processing Unit, TPU) and the like, which can exert higher effective calculation force in certain specific fields, but faces the flexible and changeable more general fields, and has relatively poor processing capability or even cannot process. Because of the large variety and huge number of data in the intelligent age, the chip is required to have extremely high flexibility, can process algorithms in different fields and in daily life and in a very strong processing capacity, and can rapidly process extremely large and rapidly growing data volume.
In neural networks or high performance computing, to achieve higher computational power, it is often necessary to implement a multi-chip component system to meet the needs of the application. Fig. 1a is a scheme of multi-chip interconnection in the prior art, in which a total of MxN chips are arranged in M rows and N columns to form a chip array, and one or more tasks are completed together or in groups. When a certain source chip needs to send data to a destination chip, the data can be transmitted through other intermediate chips in a relay mode. When the source chip C (1, 1) sends data to the destination chip C (2, 2), the C (1, 1) may send data to the C (2, 1), and the C (2, 1) relays the data packet to the destination chip C (2, 2). The intermediate chip is used as a relay chip, and a plurality of interfaces are arranged in the intermediate chip, but the number of the interfaces is not fixed, and the number of the interfaces can be T (T is more than or equal to 1 and T is a natural number). Taking the example that the intermediate chip comprises 4 interfaces, the 4 interfaces are respectively 4 interfaces of southeast, southwest and northwest, and the layout of the interfaces is shown in fig. 1 b. For best performance of the chip on the PCB (Printed Circuit Board ) of the final product, 4-way interface pins are arranged in 4-way directions, southwest and northwest of the chip, to facilitate routing on the PCB without affecting performance. And four interface circuits connected with pins in 4 directions inside the chip are also arranged in the nearest place of each pin according to the rule of nearby so as to obtain the best performance. In the prior art, noC (network-on-chip) is generally used to implement direct transmission of data between interfaces, as shown in fig. 1 c. The interfaces in 4 directions are uniformly connected to the same NoC, so that direct interconnection among all interface circuits is realized. For example, there is data to be relayed from if_w to if_e, if_w sends the data directly to if_e through NoC, and if_e then sends the data out. However, such a solution has a number of drawbacks: 1. when the area of the chip is relatively large, the connecting line from the IF to the NoC is very long, and enough buffer units are needed to be inserted into the connecting line to meet the time sequence requirement, so that the cost of the chip is increased; 2. since all data lines, control lines and clock lines of the NoC are inserted into the buffer units at the same time, it is difficult to achieve consistent delay, which affects the performance of the chip; 3. in order to balance the distances from the NoC to the IF, the NoC is usually placed in the middle of the chip, so that the connection between the NoC and the IF needs to span a large number of circuits, which affects the performance of other circuits, leaves wiring positions, increases the area of the chip, and increases the difficulty of the layout and wiring of the chip; 4. nocs also need to be used for other circuits, and IF data interaction between the IF is frequent, the data size is relatively large, which can greatly increase the blocking degree of the NoC and affect the performance of the chip.
Disclosure of Invention
This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
In order to solve the technical problems of increased chip cost, affected chip formation and high difficulty in chip layout and wiring caused by using NoC to relay data transmission in the prior art, the embodiment of the disclosure provides the following technical scheme:
in a first aspect, an embodiment of the present disclosure provides a data processing circuit disposed inside a chip, including: a data packet receiving circuit and a data packet output circuit; the data packet receiving circuit is used for receiving a source data packet and determining a first sending direction of the source data packet according to a target chip address of a source packet head in the source data packet; the data packet output circuit is used for transmitting the source data packet according to the first transmitting direction.
Further, the data packet output circuit comprises a data packet output interface; the data packet output interface includes: a first output interface and a second output interface; the first output interface is used for sending a first data packet, and the first data packet is a source data packet to be sent to the chip; the second output interface is configured to send a second data packet, where the second data packet is a source data packet to be sent to other chips.
Further, the data packet receiving circuit comprises a data packet receiving interface; the data packet receiving interface includes: an internal data receiving interface, an external data receiving interface, a first data receiving interface and a second data receiving interface; the internal data receiving interface is used for receiving data packets sent from the chip to the other chips; the external data interface is used for receiving data packets sent from the other chips to the chip; the first data receiving interface and the second data receiving interface are respectively used for receiving data packets sent to the data processing circuit by other data processing circuits on the chip.
Further, the data packet receiving circuit further includes: a data buffer memory and a packet header analysis circuit; the data buffer memory is used for buffering the source data packet received by the data packet receiving interface; the packet header analyzing circuit is used for reading the source data packet in the data buffer memory and analyzing the target chip address of a source packet header in the source data packet; the packet header parsing circuit is further configured to generate a switch control signal related to the first transmission direction according to the target chip address.
Further, the data output circuit further includes: a first switching circuit; the first switch circuit is used for selecting a first output interface to output the source data packet or selecting a second output interface to output the source data packet according to the switch control signal.
Further, the packet header parsing circuit is further configured to: responding to the target chip address as the chip, the packet header analyzing circuit generates a first switch control signal, wherein the first switch control signal is used for indicating the first switch circuit to select the first output interface; and in response to the target chip address not being the chip, the packet header parsing circuit generates a second switch control signal for instructing the first switch circuit to select the second output interface.
Further, the second output interface includes: an external data output interface, a first data output interface and a second data output interface; the data packet output circuit further includes: a packet header modification circuit and a second switching circuit; the first switch circuit is used for sending the source data packet to the packet header modification circuit and the second switch circuit in response to the second switch control signal generated by the packet header parsing circuit; the packet header modification circuit is used for generating a third switch control signal according to path selection control information of a source packet header in the source data packet; the packet header modification circuit is further configured to update the path selection control information in the source packet header according to the path selection control information to generate a new data packet; the second switch circuit selects one of the external data output interface, the first data output interface or the second data output interface to send the new data packet according to the third switch control signal.
Further, the path selection control information includes: and the path control bit is used for indicating the second sending direction of the source data packet.
In a second aspect, an embodiment of the present disclosure provides a data processing method, which is used in a chip, and includes: receiving a source data packet, wherein the source data packet comprises a source packet head and source data; determining a first sending direction of the source data packet according to a target chip address of a source packet head in the source data packet; and transmitting the source data packet according to the first transmitting direction.
Further, the sending the source data packet according to the first sending direction includes: responding to the target chip address as the chip, and sending the source data packet to the chip; and transmitting the source data packet to other chips in response to the target chip address not being the chip.
In a third aspect, embodiments of the present disclosure provide a chip, which includes at least one data processing circuit according to the first aspect.
In a fourth aspect, an embodiment of the present disclosure provides an electronic device, including: a memory for storing computer readable instructions; and one or more processors configured to execute the computer-readable instructions such that the processor, when executed, performs any of the data processing methods of the third aspect.
In a fifth aspect, embodiments of the present disclosure provide a non-transitory computer readable storage medium, characterized in that the non-transitory computer readable storage medium stores computer instructions for causing a computer to perform any one of the data processing methods of the foregoing third aspect.
In a sixth aspect, embodiments of the present disclosure provide a computer program product, wherein: comprising computer instructions which, when executed by a computing device, may perform the data processing method of any of the preceding third aspects.
An eighth aspect, an embodiment of the present disclosure provides a computing device, including a chip as described in the third aspect.
The embodiment of the disclosure discloses a data processing circuit, a data processing device and a data processing method. Wherein the data processing circuit comprises: a data packet receiving circuit and a data packet output circuit; the data packet receiving circuit is used for receiving a source data packet and determining a first sending direction of the source data packet according to a target chip address of a source packet head in the source data packet; the data packet output circuit is used for transmitting the source data packet according to the first transmitting direction. By the method, the technical problems of increased chip cost, affected chip formation and high difficulty in chip layout and wiring caused by using the network on chip as a relay for transmitting data in the prior art are solved.
The foregoing description is only an overview of the disclosed technology, and may be implemented in accordance with the disclosure of the present disclosure, so that the above-mentioned and other objects, features and advantages of the present disclosure can be more clearly understood, and the following detailed description of the preferred embodiments is given with reference to the accompanying drawings.
Drawings
The above and other features, advantages, and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. The same or similar reference numbers will be used throughout the drawings to refer to the same or like elements. It should be understood that the figures are schematic and that elements and components are not necessarily drawn to scale.
FIGS. 1a-1c are schematic diagrams illustrating prior art schemes for transferring data between multiple chips;
fig. 2 is an application scenario schematic diagram of a data processing circuit according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a data processing circuit in an embodiment of the present disclosure;
FIG. 4 is a detailed schematic diagram of the data processing circuit in an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a chip including a data processing circuit according to an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of coordinates of a chip array provided by an embodiment of the disclosure;
Fig. 7 is a schematic diagram of a packet transmission process according to an embodiment of the present disclosure.
Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.
It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order and/or performed in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below.
It should be noted that the terms "first," "second," and the like in this disclosure are merely used to distinguish between different devices, modules, or units and are not used to define an order or interdependence of functions performed by the devices, modules, or units.
It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those of ordinary skill in the art will appreciate that "one or more" is intended to be understood as "one or more" unless the context clearly indicates otherwise.
The names of messages or information interacted between the various devices in the embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.
Fig. 2 is an application scenario diagram of a data processing circuit in an embodiment of the disclosure. A chip comprising the data processing circuitry of the present disclosure is shown in fig. 2. The chip 200 includes 4 data processing circuits 201, 202, 203 and 204, two adjacent data processing circuits are mutually connected, and a data packet can enter from one data processing circuit and be output from an adjacent data processing circuit, but cannot be directly output from a data processing circuit opposite to the adjacent data processing circuit, but can be output from a data processing circuit opposite to the adjacent data processing circuit only by being transferred through the adjacent data processing circuit. For example, a data packet needs to be input from the data processing circuit 201 of the chip and output from the data processing circuit 203, then the data processing circuit 201 needs to send the data packet to the data processing circuit 202 adjacent thereto, and then the data processing circuit 202 sends the data packet to the data processing circuit 203 and outputs the data packet from the data processing circuit 203, where the data flow is shown in fig. 2, the dashed single arrow indicates the logic transmission line of the data packet, the solid single arrow indicates the actual transmission line of the data packet, and of course, the data processing circuit 204 may also be used as a data packet forwarding unit to forward the data packet to the data processing circuit 203, which is not limited herein.
Fig. 3 is a schematic diagram of a data processing circuit in an embodiment of the disclosure. As shown in fig. 3, the data processing circuit 300 includes: a packet receiving circuit 301 and a packet outputting circuit 302; the data packet receiving circuit 301 is configured to receive a source data packet, and determine a first sending direction of the source data packet according to a destination chip address of a source packet header in the source data packet; the packet output circuit 302 is configured to send the source packet according to the first sending direction.
Specifically, as shown in fig. 3, the packet output circuit includes a packet output interface 303, and the packet output interface 303 includes: a first output interface 3031 and a second output interface 3032; the first output interface 3031 is configured to send a first data packet, where the first data packet is a source data packet to be sent to the chip according to the indication of the first direction; the second output interface 3032 is configured to send a second data packet, where the second data packet is a source data packet to be sent to other chips according to the indication of the first direction.
Specifically, the source packet header of the source packet includes an address of a target chip of the source packet, the packet receiving circuit 301 determines whether the address of the target chip is the same as an address of a chip where the data processing circuit is located, if so, determines that the source packet is a packet to be sent to the chip, and the first sending direction points to the chip; if the data packets are different, the source data packet is determined to be the data packet to be transmitted to other chips, and the first transmitting direction points to the other chips. The packet output circuit selects the first output interface 3031 or the second output interface 3032 to send the source packet according to the first sending direction after receiving the first sending direction information and the source packet sent by the packet receiving circuit. The second output interface 3032 further includes: an external data output interface d_w_out, a first data output interface d_wn and a second data output interface d_ws, wherein the external data output interface is used for transmitting a source data packet to other chips; the first data output interface and the second data output interface are respectively used for sending the source data packet to other data processing circuits on the chip.
Specifically, as shown in fig. 3, the packet receiving circuit 301 includes a packet receiving interface 304, and the packet receiving interface 304 includes: an internal data receiving interface i_w_in, an external data receiving interface d_w_in, a first data receiving interface d_nw, a second data receiving interface d_sw; the internal data receiving interface is used for receiving source data packets sent from the chip to the other chips; the external data interface is used for receiving source data packets sent from the other chips to the chip; the first data receiving interface and the second data receiving interface are respectively used for receiving source data packets sent to the data processing circuit by other data processing circuits on the chip.
Fig. 4 is a detailed structural diagram of a data processing circuit in an embodiment of the present disclosure. As shown in fig. 4, the data receiving circuit 301 further includes: a data buffer memory 401 and a packet header parsing circuit 402; wherein, the data buffer 401 is configured to buffer the source data packet received by the data packet receiving interface 304; the packet header parsing circuit 402 is configured to read the source data packet in the data buffer 401, and parse the target chip address of the source packet header in the source data packet; the packet header parsing circuit 402 is further configured to generate a switch control signal related to the first transmission direction according to the target chip address. Wherein the switch control signal determines whether the first transmission direction is directed to the chip or to the other chip.
Correspondingly, as shown in fig. 4, the packet output circuit 302 further includes: the first switch circuit 403 is configured to select the first output interface 3031 to output the source data packet or select the second output interface 3032 to output the source data packet according to the switch control signal.
Further, the header parsing circuit 402 is further configured to: in response to the target chip address being the present chip, the packet header parsing circuit generates a first switch control signal, where the first switch control signal is used to instruct the first switch circuit 403 to select the first output interface 3031; in response to the target chip address not being the present chip, the packet header parsing circuit generates a second switch control signal for instructing the first switching circuit 403 to select the second output interface.
Specifically, as shown in fig. 4, the first switch circuit 403 includes a bidirectional switch, when the switch is closed to the position 1, the source packet is output from the first output interface 3031, when the switch is closed to the position 2, the source packet is output from the second output interface 3032, and the first switch control signal controls the switch of the first switch circuit to be closed to the position 1, and the second switch control signal controls the switch of the first switch circuit to be closed to the position 2, so that two different switch control signals can be generated by the destination chip address of the source packet header in the source packet to control the switch closing position of the first switch circuit.
As shown in fig. 4, the second output interface 3032 includes: an external data output interface, a first data output interface and a second data output interface; the packet output circuit 302 further includes: a packet header modification circuit 404 and a second switching circuit 405; in response to the second switch control signal generated by the packet header parsing circuit 402, the first switch circuit 403 is configured to send the source data packet to the packet header modification circuit 404 and the second switch circuit 405; the packet header modification circuit 404 is configured to generate a third switch control signal according to path selection control information of a source packet header in the source data packet; the packet header modification circuit 404 is further configured to update the path selection control information in the source packet header according to the path selection control information to generate a new data packet; the second switching circuit 405 selects one of the external data output interface, the first data output interface, or the second data output interface to transmit the new data packet according to the third switching control signal.
Specifically, as shown in fig. 4, when the packet header parsing circuit 402 generates the second switch control signal, the switch of the first switch circuit is closed to the position 2, and then the source data is sent to the packet header modification circuit 404 and the second switch circuit, and the packet header modification circuit 404 parses the path selection control information of the source packet header in the source data packet, where the path selection control information includes a path control bit, and the path control bit is used to indicate the second sending direction of the source data packet. Wherein the second transmission direction indicates one of the external data output interface, the first data output interface or the second data output interface in the above embodiments. The packet header modification circuit 404 generates a third switch control signal according to the path selection control information, where the third switch control signal includes three states corresponding to a switch closed to a position 1, a switch closed to a position 2, and a switch closed to a position 3 in the second switch circuit, respectively, so that the second switch circuit can be controlled to select one of an external data output interface, the first data output interface, and the second data output interface. In addition, the packet header modification circuit 404 updates the path selection information in the source packet header in the source packet according to the parsed path selection control information to generate a new packet, so that the next data processing circuit determines the transmission direction of the new packet.
The above describes the structure of the data processing circuit and the transmission mode of the source data packet, and the following describes the flow of forwarding the source data packet.
As shown in fig. 5, a chip with 4 data processing circuits is provided, and the 4 data processing circuits are respectively named as if_ W, IF _ N, IF _ E, IF _s according to azimuth. Taking one of the data processing circuits if_w as an example, it has 4 receiving interfaces and 4 output interfaces, wherein the 4 output interfaces comprise: d_w_in (external data receiving interface), d_nw (first data receiving interface), d_sw (second data receiving interface), i_w_in (internal data receiving interface), wherein d_w_in is used for receiving source data packets sent by other chips, d_nw is used for receiving source data packets sent by the data processing circuit if_n, d_sw is used for receiving source data packets sent by the data processing circuit if_s, and i_w_in is used for receiving source data packets to be sent out inside the chip. The 4 output interfaces include: d_ w_out (external data output interface), d_wn (first data output interface), d_ws (second data output interface), i_w_out (first output interface). The transmission direction of the source packet has the following possibilities: 1. d_w_in- > i_w_out: representing source packets received from other chips, the target chip is the own chip, and thus is directly sent to the inside of the own chip through i_w_out (first output interface); 2. d_w_in- > d_wn/d_ws: indicating the source data packet received from other chips, the target chip is not the own chip, so the source data packet is forwarded to other data processing circuits of the own chip, namely, the source data packet is sent out through an output interface D_WN/D_WS; 3. dnw/d_sw- > d_ws/d_wn: the source data packet received from other data processing circuits of the chip is represented, the target chip is not the chip, and the other data processing circuits which are required to be transferred to the chip by the data processing circuits are required to be transferred, namely the source data packet is sent out through an output interface D_WS/D_WN; 4. dnw/d_sw- > d_w_out: the source data received from other data processing circuits of the chip are indicated, the target chip is not the chip, and the source data packet needs to be sent out from the data processing circuit, namely, the source data packet is sent out through an output interface D_W_out.
As described above, there are many possibilities for the transmission direction of the source packet, so the data processing circuit needs to determine the transmission direction of the source packet after receiving the source packet, and in the embodiment of the present disclosure, the determination of the transmission direction of the source packet is implemented according to the destination chip address and/or the path selection control information of the source packet header in the source packet.
Illustratively, the source packet format is as follows:
| Reserved[4:0] | Dir_P[1:0] | Addr_C[5:0] | Addr[18:0] | Data[63:0] |
| reserved bits | Path selection control information | Target chip address | On-chip address | Data |
The path selection control information comprises two-bit path control bits, and the coding rule of the path control bits is as follows:
addr_C [5:0] refers to the address of the target chip in the whole chip array, and the address may be an absolute address or a relative address (i.e. the relative coordinates of the target chip and the own chip of the source data packet).
Illustratively, in absolute address mode, the encoding rule of the target chip address is as follows:
| Addr_C[5:0] | meaning of |
| [5:3] | Y-coordinate of target chip in chip array |
| [2:0] | X-coordinate of target chip in chip array |
For example, the chip array includes 64 chips, which form an 8×8 array, and the coordinates of each chip are assigned as shown in fig. 6. The coordinates of the chip in the upper left corner are (1, 1), the coordinates of the chip in the lower right corner are (8, 8), and the coordinates of the other chips are ordered in sequence according to the positions of the other chips in the array.
The whole process of processing the received source data packet by the data processing circuit in the embodiment of the present disclosure will be described with reference to the detailed schematic diagram of the data processing circuit in fig. 4 and the format of the source data packet.
For the packet receiving circuit 301, it may receive a source packet input from a plurality of input sources, if the packet receiving circuit 301 receives the source packet, the source packet is stored in the data buffer 401, then the source packet is read out from the data buffer 401 and put on the bus d_c, and the packet header parsing circuit 402 reads the destination chip address addr_c indicated by a predetermined position in the source packet header in the source packet, the packet header parsing circuit 402 compares the destination chip address with the address addr_c0 of the chip, if the two are equal, the source packet is a packet sent to the chip, the packet header parsing circuit generates a first switch control signal, and sends the first switch control signal to a first switch circuit of the packet output circuit, so that a switch in the first switch circuit is closed to position 1, and the source packet is directly sent to the inside of the chip through i_w_out.
If the two are not equal, the packet header analysis circuit generates a second switch control signal and sends the second switch control signal to a first switch circuit of the packet output circuit, so that a switch in the first switch circuit is closed to a position 2 to send the source packet to a packet header modification circuit and a second switch circuit of the packet output circuit, and the packet header modification circuit reads a target chip address addr_C and path selection control information dir_P in the source packet and then performs the following processing according to the path selection control information: 1. when dir_p [1:0] = '00': the source data packet is sent from the data processing circuit to other chips, and the packet header modification circuit generates a third switch control signal to control the switch of the second switch circuit to be closed to the position 1, so that the source data is sent from the D_W_out; meanwhile, the packet header modification circuit updates dir_p in the source packet header according to the target chip address, and the updating rule is as follows: if the X coordinate value of the target chip is smaller than the X coordinate value of the next chip, updating dir_P= '11', wherein in the transmission process of the specified data packet, the data packet is firstly transmitted in the X axis direction, namely, the data packet is firstly transmitted to a transit chip in the same column with the target chip, and then is transmitted in the Y axis direction until the data packet reaches the target chip; since if_w is taken as an example here, the data packet is transmitted from if_w, the X coordinate of its target chip can only be smaller than the X coordinate of the present chip, because IF the X coordinate of the target chip is larger than the X coordinate of the present chip, the data packet will be sent from if_e; if the X coordinate of the target chip is equal to the X coordinate of the next chip, judging the sizes of the Y coordinate of the target chip and the Y coordinate of the next chip, if the Y coordinate of the target chip is larger than the Y coordinate of the next chip, updating dir_P= '10', and if the Y coordinate of the target chip is smaller than the Y coordinate of the next chip, updating dir_P= '01'; 2. when dir_p [1:0] = '01': indicating that the source data packet is a data packet forwarded by the data processing circuit, and the forwarding direction is to send the data packet to the next data processing circuit, namely if_s, in a counterclockwise direction, wherein the packet header modifying circuit generates a third switch control signal to control the switch of the second switch circuit to be closed to a position 2, and send the source data from d_ws; meanwhile, it will directly update dir_p, after updating dir_p [1:0] = '00', that is, the next data processing circuit needs to send the source data packet out of the chip; 3. when dir_p [1:0] = '10': indicating that the source data packet is a data packet forwarded by the data processing circuit, and forwarding the source data packet in a direction of clockwise rotation by the data processing circuit, namely, if_n, wherein the packet header modifying circuit generates a third switch control signal to control the switch of the second switch circuit to be closed to a position 3 and send the source data from d_wn; meanwhile, it will directly update dir_p, after updating dir_p [1:0] = '00', that is, the next data processing circuit needs to send the source data packet out of the chip; 4. when dir_p [1:0] = '11': indicating that the source data packet is a data packet forwarded via the data processing circuit, and the target data processing circuit is if_e, but since there is no direct transmission path from the data processing circuit to if_e, the source data packet needs to be first turned by one IF, i.e. if_n, clockwise, at which time the packet header modification circuit generates a third switch control signal to control the switch of the second switch circuit to be closed to position 3 and send the source data from d_wn; at the same time, it will update dir_p directly, and dir_p [1:0] = '10' after updating, that is, the next data processing circuit needs to forward the source data packet to another data processing circuit.
Fig. 7 illustrates a data forwarding process of the data processing circuit in an embodiment of the present disclosure in a transmission process of a data packet from a source chip to a target chip. As shown in fig. 7, source data is transmitted from the chip C (1, 1) to the chip C (3, 2), wherein the dotted arrow indicates the logical transmission line of the source packet, and the solid single arrow indicates the actual transmission line of the source packet. The entire transmission process of the source packet is as follows: 1. the source chip C (1, 1) packages a source packet to be transmitted, and transmits the source packet through the data processing circuit if_e because the X coordinate of the target chip C (3, 2) is greater than the X coordinate of the own chip (1, 1), and sets dir_p= '11' in the source packet header of the source packet because the X coordinate of the target chip C (3, 2) is greater than the X coordinate of the next transit chip C (2, 1), which means that the data processing circuit of the chip C (2, 1) needs to transmit the source packet to the data processing circuit opposite thereto after receiving the source packet; 2. the data processing circuit if_w of the chip C (2, 1) receives the source data packet, firstly judges that the target chip address is not equal to the chip address, then knows that the source data packet needs to be sent to the next data processing circuit if_n of the chip according to dir_p= '11', updates dir_p= '10', and finally sends the source data packet with updated packet header to the data processing circuit if_n of the chip; 3. the data processing circuit if_n of the chip C (2, 1) receives the source data packet, firstly judges that the target chip address is not equal to the chip address, then knows that the source data packet needs to be sent to the next data processing circuit if_e of the chip according to dir_p= '10', updates dir_p= '00', and finally sends the source data packet with updated packet header to the data processing circuit if_e of the chip; 4. the data processing circuit IF_E of the chip C (2, 1) receives the source data packet, firstly judges that the target chip address is not equal to the chip address, then knows that the source data packet needs to be sent to the next chip C (3, 1) according to Dir_P= '00', the data processing circuit IF_E checks that the X coordinate of the C (3, 1) is equal to the X coordinate of the target chip C (3, 2), the Y coordinate of the C (3, 1) is smaller than the Y coordinate of the target chip C (3, 2), the Dir_P= '01' is updated, and finally the source data packet with the updated packet header is sent to the next chip C (3, 1); 5. the data processing circuit if_w of the chip C (3, 1) receives the source data packet, firstly judges that the target chip address is not equal to the chip address, then knows that the source data packet needs to be sent to the next data processing circuit if_s of the chip according to dir_p= '01', updates dir_p= '00', and finally sends the source data packet with updated packet header to the data processing circuit if_s of the chip; 6. the data processing circuit IF_S of the chip C (3, 1) receives the source data packet, firstly judges that the target chip address is not equal to the chip address, then knows that the source data packet needs to be sent to the next chip C (3, 2) according to Dir_P= '00', and the data processing circuit IF_S checks that the chip C (3, 2) is the destination chip, so that Dir_P is not updated any more and the source data packet is directly sent to the next chip C (3, 2); 7. the data processing circuit if_w of the chip C (3, 2) receives the source data packet, finds that the target chip address is equal to the present chip address, so the data processing circuit if_w sends the source data packet to the inside of the present chip, and the whole data transmission is completed.
It should be understood that the format of the data packet is merely exemplary, and in particular, the number of bits and the specific meaning of dir_p therein may be set according to the specific situation, and the foregoing specific embodiments of the disclosure are merely illustrative examples of the technical solutions of the disclosure, and do not constitute limitation of the disclosure.
The data processing circuits of the embodiment of the disclosure are directly connected by a circuit, so that data congestion is not generated by sharing NoC, and the computing power of a chip can be improved; because the two data processing circuits are relatively close in physical, overlong NoC wiring is avoided, the area of a chip is reduced, the cost is reduced, and the interconnection performance between the two data processing circuits can be exerted to the greatest extent; the connections between the data processing circuits can be placed in relatively fragmented corners, which are generally unsuitable for use with other functional modules, thereby effectively utilizing the area of the chip; the data processing short circuit is short in connection, and can be positioned in the edge corner area of the chip, so that other functional modules are not affected.
The embodiment of the disclosure also provides a chip, which is characterized by comprising at least one data processing circuit.
An embodiment of the disclosure provides a computing device comprising a chip as described in any of the preceding embodiments.
The embodiment of the disclosure also provides a data processing method, which is characterized by comprising the following steps: receiving a source data packet, wherein the source data packet comprises a source packet head and source data; determining a first sending direction of the source data packet according to a target chip address of a source packet head in the source data packet; and transmitting the source data packet according to the first transmitting direction.
Further, the sending the source data packet according to the first sending direction includes: responding to the target chip address as the chip, and sending the source data packet to the chip; and transmitting the source data packet to other chips in response to the target chip address being not the own chip.
An embodiment of the present disclosure provides an electronic device, including: a memory for storing computer readable instructions; and one or more processors configured to execute the computer-readable instructions such that the processors, when executed, implement any of the data processing methods of the previous embodiments.
In a fifth aspect, embodiments of the present disclosure provide a non-transitory computer readable storage medium, characterized in that the non-transitory computer readable storage medium stores computer instructions for causing a computer to perform any one of the data processing methods of the previous embodiments.
Embodiments of the present disclosure provide a computer program product, wherein: comprising computer instructions which, when executed by a computing device, can perform any of the data processing methods of the previous embodiments.
The flowcharts and block diagrams in the figures of this disclosure illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units involved in the embodiments of the present disclosure may be implemented by means of software, or may be implemented by means of hardware. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.
The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a Complex Programmable Logic Device (CPLD), and the like.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
Claims (10)
1. A data processing circuit disposed within a chip, comprising:
a data packet receiving circuit and a data packet output circuit;
the data packet receiving circuit is used for receiving a source data packet and determining a first sending direction of the source data packet according to a target chip address of a source packet head in the source data packet;
the data packet output circuit is used for transmitting the source data packet according to the first transmitting direction;
the data packet receiving circuit comprises a data packet receiving interface, wherein the data packet receiving interface comprises an internal data receiving interface, an external data receiving interface, a first data receiving interface and a second data receiving interface, the internal data receiving interface is used for receiving data packets sent from the chip to other chips, the external data receiving interface is used for receiving data packets sent from other chips to the chip, and the first data receiving interface and the second data receiving interface are respectively used for receiving data packets sent from other data processing circuits on the chip to the data processing circuit;
the data packet output circuit comprises a data packet output interface, the data packet output interface comprises a first output interface and a second output interface, the first output interface is used for sending a first data packet, the first data packet is a source data packet to be sent to the chip, the second output interface is used for sending a second data packet, the second data packet is a source data packet to be sent to other chips, the second output interface comprises an external data output interface, a first data output interface and a second data output interface, the external data output interface is used for sending the source data packet to the other chips, and the first data output interface and the second data output interface are respectively used for sending the source data packet to other data processing circuits on the chip so as to send the source data packet to the other chips through the other data processing circuits.
2. The data processing circuit of claim 1, wherein the data packet receiving circuit further comprises: a data buffer memory and a packet header analysis circuit;
the data buffer memory is used for buffering the source data packet received by the data packet receiving interface;
the packet header analyzing circuit is used for reading the source data packet in the data buffer memory and analyzing the target chip address of a source packet header in the source data packet;
the packet header parsing circuit is further configured to generate a switch control signal related to the first transmission direction according to the target chip address.
3. The data processing circuit of claim 2 wherein the data packet output circuit further comprises: a first switching circuit;
the first switch circuit is used for selecting a first output interface to output the source data packet or selecting a second output interface to output the source data packet according to the switch control signal.
4. A data processing circuit according to claim 3, wherein the packet header parsing circuit is further operable to:
responding to the target chip address as the chip, the packet header analyzing circuit generates a first switch control signal, wherein the first switch control signal is used for indicating the first switch circuit to select the first output interface;
And in response to the target chip address not being the chip, the packet header parsing circuit generates a second switch control signal for instructing the first switch circuit to select the second output interface.
5. The data processing circuit of claim 4 wherein the data packet output circuit further comprises: a packet header modification circuit and a second switching circuit;
the first switch circuit is used for sending the source data packet to the packet header modification circuit and the second switch circuit in response to the second switch control signal generated by the packet header parsing circuit;
the packet header modification circuit is used for generating a third switch control signal according to path selection control information of a source packet header in the source data packet;
the packet header modification circuit is further configured to update the path selection control information in the source packet header according to the path selection control information to generate a new data packet;
the second switch circuit selects one of the external data output interface, the first data output interface or the second data output interface to send the new data packet according to the third switch control signal.
6. The data processing circuit of claim 5 wherein the path selection control information comprises:
and the path control bit is used for indicating the second sending direction of the source data packet.
7. A chip characterized in that it comprises at least one data processing circuit according to any one of claims 1-6.
8. A data processing method for a data processing circuit in a chip, comprising:
receiving a source data packet, wherein the source data packet comprises a source packet head and source data;
determining a first sending direction of the source data packet according to a target chip address of a source packet head in the source data packet;
transmitting the source data packet according to the first transmitting direction;
responding to the first sending direction to point to the chip, and sending the source data packet to the chip through a first output interface;
responding to the first sending direction to other chips, and sending a source data packet to the other chips through an external data output interface; or alternatively
Responding to the first sending direction to point to other chips, and sending the source data packet to other data processing circuits on the chip through a first data output interface and a second data output interface so as to send the source data packet to other chips through the other data processing circuits;
The receiving source data packet includes:
responding to the source data packet as a data packet sent from the chip to other chips, and receiving the source data packet through an internal data receiving interface; or alternatively
Responding to the source data packet as a data packet sent from other chips to the chip, and receiving the source data packet through an external data receiving interface; or alternatively
And responding to the source data packet as the data packet sent to the data processing circuit by other data processing circuits on the chip, and respectively receiving the source data packet through a first data receiving interface and a second data receiving interface.
9. A non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the data processing method of claim 8.
10. A computing device comprising the chip of claim 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911290285.6A CN112988653B (en) | 2019-12-16 | 2019-12-16 | Data processing circuit, device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911290285.6A CN112988653B (en) | 2019-12-16 | 2019-12-16 | Data processing circuit, device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112988653A CN112988653A (en) | 2021-06-18 |
| CN112988653B true CN112988653B (en) | 2024-04-12 |
Family
ID=76342948
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911290285.6A Active CN112988653B (en) | 2019-12-16 | 2019-12-16 | Data processing circuit, device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112988653B (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5151986A (en) * | 1987-08-27 | 1992-09-29 | Motorola, Inc. | Microcomputer with on-board chip selects and programmable bus stretching |
| JPH04367989A (en) * | 1991-06-14 | 1992-12-21 | Mitsubishi Electric Corp | Input/output circuit of microcomputer |
| US5390173A (en) * | 1992-10-22 | 1995-02-14 | Digital Equipment Corporation | Packet format in hub for packet data communications system |
| US6041378A (en) * | 1996-10-31 | 2000-03-21 | Sgs-Thomson Microelectronics Limited | Integrated circuit device and method of communication therewith |
| CN101291546A (en) * | 2008-06-11 | 2008-10-22 | 清华大学 | Switching structure coprocessor of core router |
| CN101753388A (en) * | 2008-11-28 | 2010-06-23 | 中国科学院微电子研究所 | Router and interface device suitable for the extending on and among sheets of polycaryon processor |
| CN103595627A (en) * | 2013-11-28 | 2014-02-19 | 合肥工业大学 | NoC router based on multicast dimension order routing algorithm and routing algorithm thereof |
| CN105095150A (en) * | 2015-08-14 | 2015-11-25 | 中国电子科技集团公司第五十八研究所 | Network interface supporting network-on-chip |
| CN105593830A (en) * | 2013-10-30 | 2016-05-18 | 英特尔公司 | A method, apparatus and system for measuring latency in a physical unit of a circuit |
| CN107113227A (en) * | 2014-12-17 | 2017-08-29 | 英特尔公司 | Pipelining mixing packet/circuit switching network-on-chip |
| EP3392767A1 (en) * | 2017-04-21 | 2018-10-24 | Aerobits Sp. z o.o. | A method for real time processing of fast analogue signals and a system for application thereof |
| CN109408257A (en) * | 2018-11-09 | 2019-03-01 | 北京灵汐科技有限公司 | Data transmission method, device and electronic equipment for network-on-chip NOC |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7716725B2 (en) * | 2002-09-20 | 2010-05-11 | Fortinet, Inc. | Firewall interface configuration and processes to enable bi-directional VoIP traversal communications |
| US7184360B2 (en) * | 2005-06-15 | 2007-02-27 | Infineon Technologies, Ag | High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips |
| WO2014209391A1 (en) * | 2013-06-28 | 2014-12-31 | Intel Corporation | A method, apparatus and system for a source-synchronous circuit-switched network on a chip (noc) |
-
2019
- 2019-12-16 CN CN201911290285.6A patent/CN112988653B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5151986A (en) * | 1987-08-27 | 1992-09-29 | Motorola, Inc. | Microcomputer with on-board chip selects and programmable bus stretching |
| JPH04367989A (en) * | 1991-06-14 | 1992-12-21 | Mitsubishi Electric Corp | Input/output circuit of microcomputer |
| US5390173A (en) * | 1992-10-22 | 1995-02-14 | Digital Equipment Corporation | Packet format in hub for packet data communications system |
| US6041378A (en) * | 1996-10-31 | 2000-03-21 | Sgs-Thomson Microelectronics Limited | Integrated circuit device and method of communication therewith |
| CN101291546A (en) * | 2008-06-11 | 2008-10-22 | 清华大学 | Switching structure coprocessor of core router |
| CN101753388A (en) * | 2008-11-28 | 2010-06-23 | 中国科学院微电子研究所 | Router and interface device suitable for the extending on and among sheets of polycaryon processor |
| CN105593830A (en) * | 2013-10-30 | 2016-05-18 | 英特尔公司 | A method, apparatus and system for measuring latency in a physical unit of a circuit |
| CN103595627A (en) * | 2013-11-28 | 2014-02-19 | 合肥工业大学 | NoC router based on multicast dimension order routing algorithm and routing algorithm thereof |
| CN107113227A (en) * | 2014-12-17 | 2017-08-29 | 英特尔公司 | Pipelining mixing packet/circuit switching network-on-chip |
| CN105095150A (en) * | 2015-08-14 | 2015-11-25 | 中国电子科技集团公司第五十八研究所 | Network interface supporting network-on-chip |
| EP3392767A1 (en) * | 2017-04-21 | 2018-10-24 | Aerobits Sp. z o.o. | A method for real time processing of fast analogue signals and a system for application thereof |
| CN109408257A (en) * | 2018-11-09 | 2019-03-01 | 北京灵汐科技有限公司 | Data transmission method, device and electronic equipment for network-on-chip NOC |
Non-Patent Citations (2)
| Title |
|---|
| NoC路由单元的***级设计;万玉鹏;吴宁;;苏州科技学院学报(工程技术版)(02);全文 * |
| 基于FPGA的NoC源路由设计;吴玉龙;;国外电子测量技术(04);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112988653A (en) | 2021-06-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10838787B2 (en) | Processing system with interspersed processors with multi-layer interconnect | |
| KR900006792B1 (en) | Load balancing for packet switching nodes | |
| US20140115218A1 (en) | ASYMMETRIC MESH NoC TOPOLOGIES | |
| US8825986B2 (en) | Switches and a network of switches | |
| WO2021105728A1 (en) | Efficient parallelized computation of a benes network configuration | |
| CN116383114B (en) | Chip, chip interconnection system, data transmission method, electronic device and medium | |
| CN112988653B (en) | Data processing circuit, device and method | |
| RU159583U1 (en) | MULTI-PROCESSOR DIGITAL SIGNAL PROCESSING MODULE | |
| CN105224501A (en) | Improve anchor ring network and determine the method and apparatus in data packet transmission path | |
| US8300635B2 (en) | Programmable crossbar structures in asynchronous systems | |
| CN110825689B (en) | Electronic chip and implementation method thereof | |
| GB2521121A (en) | A method and apparatus use with interrupts | |
| US7561584B1 (en) | Implementation of a graph property in a switching fabric for fast networking | |
| CN114095289B (en) | Data multicast circuit, method, electronic device, and computer-readable storage medium | |
| US12010042B2 (en) | Efficient parallelized computation of a Benes network configuration | |
| CN113852574B (en) | Network-on-chip router | |
| CN110895649B (en) | Integrated circuit back-end wiring management system, wiring management method and chip | |
| CN117421268A (en) | Interconnection system, equipment and network | |
| JP2000287230A (en) | Crossbar switch |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Country or region after: China Address after: Room 201, No. 6 Fengtong Heng Street, Huangpu District, Guangzhou City, Guangdong Province, 510530 Applicant after: Guangzhou Ximu Semiconductor Technology Co.,Ltd. Address before: 100080 202-24, building 6, yard 1, gaolizhang Road, Haidian District, Beijing Applicant before: Beijing SIMM Computing Technology Co.,Ltd. Country or region before: China |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |