CN112988228A - Control method and architecture for processor interrupt - Google Patents
Control method and architecture for processor interrupt Download PDFInfo
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- CN112988228A CN112988228A CN201911310640.1A CN201911310640A CN112988228A CN 112988228 A CN112988228 A CN 112988228A CN 201911310640 A CN201911310640 A CN 201911310640A CN 112988228 A CN112988228 A CN 112988228A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
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- G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
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Abstract
The invention provides a control method and a framework for processor interrupt, wherein the control method comprises the following steps: receiving an interrupt sent to a main processor, and judging whether the interrupt meets a preset condition or not; and filtering the interrupt meeting the preset condition, and sending the interrupt not meeting the preset condition to the main processor. According to the control method for processor interrupt, the main processor can be helped to filter out a part of interrupt, so that the number of interrupt entering the main processor is reduced fundamentally, and an interference source for awakening the main processor from a CPU idle state is reduced, thereby reducing the dynamic power consumption of the main processor.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a method and an architecture for controlling processor interrupts.
Background
In order to reduce the dynamic power consumption of the processor, a CPU idle mode is commonly used in the industry, the CPU enters a power-down state when running an idle thread, and wakes up the CPU to execute an interrupt handler when an interrupt comes. However, entering and exiting the cpu idle state consumes extra power, and frequent interrupt responses cause the processor to frequently enter and exit the cpu idle, which wastes more dynamic power.
For optimizing the CPU, a commonly used strategy in the industry is to arrange System interrupts (i.e., "heartbeat synchronization") so that the System interrupts enter a Main CPU System more regularly, and the operating System estimates the stay time of the CPU in the idle state more accurately, thereby performing power consumption management better (calculating the power consumption of the Main CPU in the idle state to calculate how long the Main CPU needs to earn the power consumption in the idle state). However, this approach has two inherent drawbacks:
"heartbeat synchronization" requires delaying the interrupt sent to the Main CPU, which undoubtedly reduces the interrupt response speed of the real-time device and affects the system performance. The worse condition can cause the interruption and loss of the equipment, thereby causing the equipment to be abnormal and leading the system to be dead.
The heartbeat synchronization cannot reduce the number of interrupts generated by equipment, cannot fundamentally reduce the times of awakening the Main CPU System from the idle state, and cannot well achieve the purpose of reducing the dynamic power consumption of the processor.
Disclosure of Invention
The invention provides a method and a structure for controlling processor interrupt, which aims to solve the technical problem of effectively reducing the power consumption of a processor.
The method for controlling the processor interrupt according to the embodiment of the invention comprises the following steps:
receiving an interrupt sent to a main processor, and judging whether the interrupt meets a preset condition or not;
and filtering the interrupt meeting the preset condition, and sending the interrupt not meeting the preset condition to the main processor.
According to the control method for processor interrupt, provided by the embodiment of the invention, the main processor can be helped to filter out a part of interrupt, so that the number of the interrupt entering the main processor is reduced fundamentally, and an interference source for awakening the main processor from a CPU idle state is reduced, thereby reducing the dynamic power consumption of the main processor.
According to some embodiments of the invention, the filtering operation comprises: and filtering or processing the interrupt meeting the preset condition.
In some embodiments of the invention, prior to receiving the interrupt to the host processor, the method further comprises:
and closing an interrupt path of the main processor and operating an interrupt filtering function.
According to some embodiments of the invention, the preset conditions comprise: the occurrence frequency of the interruption is greater than the preset frequency, or the interruption is invalid interruption.
The control architecture of processor interrupts according to an embodiment of the present invention comprises: a main processor and an interrupt processor; the interrupt handler is to:
receiving an interrupt sent to a main processor, and judging whether the interrupt meets a preset condition or not;
and filtering the interrupt meeting the preset condition, and sending the interrupt not meeting the preset condition to the main processor.
According to the control architecture of the processor interrupt, the interrupt processor is creatively introduced to help the main processor filter out a part of interrupts, the interrupt processor is used as a preceding stage interrupt of the main processor to filter out invalid interrupts, and the interrupts which can be independently processed are completed, so that the number of interrupts entering the main processor is fundamentally reduced, an interference source for awakening the main processor from a cpu idle state is reduced, the main processor stays in the cpu idle power-off state for a long time as possible, and the dynamic power consumption of the main processor is reduced.
According to some embodiments of the invention, the interrupt handler is configured to filter or process the interrupt meeting the preset condition.
In some embodiments of the invention, the architecture further comprises: the filtering function control module is interrupted, and the filtering function control module is interrupted,
and the interrupt filtering module is used for closing an interrupt path of the main processor and running an interrupt filtering function before receiving the interrupt sent to the main processor.
According to some embodiments of the invention, the preset conditions comprise: the occurrence frequency of the interruption is greater than the preset frequency, or the interruption is invalid interruption.
In some embodiments of the invention, the main processor and the interrupt handler are homogeneous processors.
According to some embodiments of the invention, the main processor and the interrupt handler are heterogeneous processors and the power consumption of the interrupt handler is less than the power consumption of the main processor.
Drawings
FIG. 1 is a flow chart of a method for controlling processor interrupts according to an embodiment of the present invention;
FIG. 2 is a block diagram of a control architecture for processor interrupts, according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating processor interrupt filtering according to an embodiment of the present invention;
FIG. 4 is a flow diagram of a device driver initialization phase enable interrupt filtering function according to an embodiment of the present invention;
FIG. 5 is a flow chart illustrating an interrupt handler control interrupt according to an embodiment of the present invention.
Detailed Description
To further explain the technical means and effects of the present invention adopted to achieve the intended purpose, the present invention will be described in detail with reference to the accompanying drawings and preferred embodiments.
The method for controlling the processor interrupt according to the embodiment of the invention comprises the following steps:
s100: receiving an interrupt sent to a main processor, and judging whether the interrupt meets a preset condition or not;
s200: and filtering the interrupt meeting the preset condition, and sending the interrupt not meeting the preset condition to the main processor.
According to the control method for processor interrupt, provided by the embodiment of the invention, the main processor can be helped to filter out a part of interrupt, so that the number of the interrupt entering the main processor is reduced fundamentally, and an interference source for awakening the main processor from a CPU idle state is reduced, thereby reducing the dynamic power consumption of the main processor.
As shown in fig. 5, according to some embodiments of the invention, the filtering operation includes: and filtering or processing the interrupt meeting the preset condition. That is to say, filtering operation is performed on the interrupt meeting the preset condition, for example, the filtering operation may filter part of invalid interrupts (for example, infrared remote key values invalid for the device) that do not meet the condition; the filtering operation can also directly process the interrupt meeting the preset condition.
As shown in fig. 4, in some embodiments of the invention, prior to receiving the interrupt directed to the host processor, the method further comprises: and closing an interrupt path of the main processor and running an interrupt filtering function.
It should be noted that whether the interrupt filtering function is enabled or not may be selected in the device driver initialization phase. When the interrupt filtering function needs to be enabled, the interrupt filtering function is operated and an interrupt channel of the main processor is closed; when the interrupt filtering function is not required to be enabled, the interrupt filtering function is closed and an interrupt processing path of the main processor is opened.
According to some embodiments of the invention, the preset conditions comprise: the occurrence frequency of the interrupt is larger than the preset frequency, or the interrupt is invalid interrupt. For example, the peripheral interrupt with a high trigger frequency may be selected to be migrated to the low power consumption processor for filtering; the filtering operation may also be performed on illegal code values. For example, the infrared receiving interrupt may preliminarily determine whether the received infrared code value is a legal code value, and if the received infrared code value is the legal code value, the interrupt is sent to the input/output subsystem of the main processor for further processing; if the code value is illegal, the code value is directly filtered, and an interrupt signal is not sent to wake up the main processor.
As shown in fig. 2, the architecture for controlling processor interrupts according to an embodiment of the present invention includes: a main processor and an interrupt processor.
Wherein the interrupt handler is to: receiving an interrupt sent to a main processor, and judging whether the interrupt meets a preset condition or not; and filtering the interrupt meeting the preset condition, and sending the interrupt not meeting the preset condition to the main processor.
According to the control architecture of the processor interrupt, the interrupt processor is creatively introduced to help the main processor filter out a part of interrupts, the interrupt processor is used as a preceding stage interrupt of the main processor to filter out invalid interrupts, and the interrupts which can be independently processed are completed, so that the number of interrupts entering the main processor is fundamentally reduced, an interference source for awakening the main processor from a cpu idle state is reduced, the main processor stays in the cpu idle power-off state for a long time as possible, and the dynamic power consumption of the main processor is reduced.
According to some embodiments of the invention, the interrupt handler is configured to filter or process eligible interrupts. That is to say, filtering operation is performed on the interrupt meeting the preset condition, for example, the filtering operation may filter part of invalid interrupts (for example, infrared remote key values invalid for the device) that do not meet the condition; the filtering operation can also directly process the interrupt meeting the preset condition.
In some embodiments of the invention, the architecture further comprises: and the interrupt filtering function control module is used for closing an interrupt path of the main processor and running the interrupt filtering function before receiving the interrupt sent to the main processor.
It should be noted that whether the interrupt filtering function is enabled or not may be selected in the device driver initialization phase. When the interrupt filtering function needs to be enabled, the interrupt filtering function is operated and an interrupt channel of the main processor is closed; when the interrupt filtering function is not required to be enabled, the interrupt filtering function is closed and an interrupt processing path of the main processor is opened.
According to some embodiments of the invention, the preset conditions comprise: the occurrence frequency of the interrupt is larger than the preset frequency, or the interrupt is invalid interrupt. For example, the peripheral interrupt with a high trigger frequency may be selected to be migrated to the low power consumption processor for filtering; the filtering operation may also be performed on illegal code values. For example, the infrared receiving interrupt may preliminarily determine whether the received infrared code value is a legal code value, and if the received infrared code value is the legal code value, the interrupt is sent to the input/output subsystem of the main processor for further processing; if the code value is illegal, the code value is directly filtered, and an interrupt signal is not sent to wake up the main processor.
In some embodiments of the present invention, the main processor and the interrupt processor are homogeneous processors, such as Cortex a7 and Cortex a15, and it may be selected to migrate peripheral interrupts with a higher trigger frequency to the low power processor Cortex a7, so as to avoid excessive interrupts from interrupting the cpu idle process of the high power processor Cortex a15, so that the high power processor Cortex a15 stays in the cpu idle state for as long as possible, and reduce the dynamic power consumption of the system.
According to some embodiments of the invention, the main processor and the interrupt processor are heterogeneous processors and power consumption of the interrupt processor is less than power consumption of the main processor. The interrupt processor can filter out invalid broadcast information in the environment, and only sends effective interrupt signals which cannot be processed independently to the main processor, so that the main processor is only awakened when needed, the time of being in a CPU state is prolonged, and the running power consumption of the system is reduced.
The following describes a control method and architecture of processor interrupts according to an embodiment of the present invention in detail with reference to the accompanying drawings. It is to be understood that the following description is only exemplary, and not a specific limitation of the invention.
The significance of the invention lies in that: an Interrupt Processor is creatively introduced to help the Main CPU System filter a part of interrupts, thereby fundamentally reducing the number of interrupts entering the Main CPU System, reducing the 'interference source' for awakening the Main CPU System from the CPU state, leading the Main CPU System to stay in the CPU power-off state for as long as possible, and further reducing the dynamic power consumption of the Processor.
In the related art, the "heartbeat synchronization" scheme cannot fundamentally reduce the number of interrupts sent to the Main CPU System, and thus cannot achieve the purpose of reducing the dynamic power consumption of the processor well.
Starting from interrupt filtering, the invention can fundamentally reduce the number of interrupts sent to the Main CPU System and reduce the times of awakening the Main CPU System from idle state, thereby reducing the dynamic power consumption of the processor.
The invention creatively designs an Interrupt Processor to filter the Interrupt of the Main CPU System, filters out part of invalid interrupts which do not meet the conditions (such as infrared remote key values invalid for the equipment), processes the Interrupt which can be processed by the Interrupt Processor, only sends the remaining Interrupt which needs the processing of the Main CPU to the Main CPU System for processing, and reduces the frequency of waking up the Main CPU System by the Interrupt, thereby reducing the dynamic power consumption when the Processor runs.
As shown in fig. 2, the main architecture of the control system for processor interrupt according to the present invention includes: the system comprises a main processor, a Dream storage unit and on-chip peripherals.
Specifically, a processor subsystem, comprising:
a Main CPU System (System Main CPU) for executing an operating System software Main body;
gic (main CPU system) for serving as an interrupt controller.
The Interrupt Processor is mainly used to take over the upper half of the Interrupt processing program of the system.
Interrupt Controller: interrupt controller for Interrupt Processor.
And the Dram storage unit is used for storing the operating system execution code and data.
And (4) an on-chip peripheral. Generally, most of the on-chip peripherals need to register a relevant interrupt processing program to an operating system, and relevant processing is performed when peripheral interrupts are generated. The on-chip peripheral Interrupt may be sent to the GIC or to the Interrupt Controller.
If the Interrupt Processor and the Main CPU are homogeneous processors, such as Cortex A7 and Cortex A15, the peripheral Interrupt with high trigger frequency can be selected to be migrated to the low-power Processor Cortex A7, the phenomenon that the CPU process of the high-power Processor Cortex A15 is interrupted by excessive interrupts is avoided, the high-power Processor Cortex A15 is left in a CPU idle state for as long as possible, and the dynamic power consumption of the system is reduced.
The Interrupt Processor may choose to use heterogeneous low power microcontrollers. The Interrupt Processor is mainly used for processing the upper half of the Interrupt handler. For example, the infrared receiving interruption can preliminarily judge whether the received infrared code value is a legal code value, and if the received infrared code value is the legal code value, the interruption is sent to the Main CPU System input/output subsystem for further processing; and if the code value is the illegal code value, directly filtering, and not sending an interrupt signal to wake up the Main CPU System. Therefore, the Interrupt Processor can filter out invalid broadcast information in the environment and only send effective Interrupt signals which cannot be processed independently to the Main CPU System, so that the Main CPU System is only awakened when needed, the time of the Main CPU System in a CPU state is prolonged, and the running power consumption of the System is reduced.
As shown in fig. 3, in the Interrupt processing, the Interrupt Processor filters the Interrupt sent to the Main CPU System, filters out the Interrupt that does not meet the set condition, processes the Interrupt that can be processed by the Interrupt Processor, and sends the remaining Interrupt to the Main CPU System, thereby greatly reducing the probability of awakening the Main CPU System by the Interrupt, and saving the dynamic power consumption of the Processor.
The flow of the interrupt filtering function enabled in the device driver initialization stage is shown in fig. 4, and includes the following steps:
the device driver initialization selects whether the interrupt filter function is enabled.
If yes, the Interrupt path of the device- > Main CPU System is closed, and the Interrupt path of the device- > Interrupt Processor is opened.
If not, the Interrupt path of the device- > Main CPU System is opened, and the Interrupt path of the device- > Interrupt Processor is closed.
The Interrupt generation flow of the Interrupt Processor is shown in fig. 5, and includes the following steps:
it is determined whether the interrupt needs to be filtered out.
If yes, directly interrupting the return; if not, continuing to judge whether the Interrupt can be completed independently by the Interrupt Processor.
If the Interrupt can be independently completed by the Interrupt Processor, the Interrupt service program is completed; if not, sending a corresponding interrupt to the Main CPU System for carrying out corresponding interrupt processing.
In conclusion, the Interrupt Processor is creatively introduced to help the Main CPU System filter a part of interrupts, the Interrupt Processor is used as a preceding stage Interrupt of the Main CPU System, filters invalid interrupts and completes independently processed interrupts, so that the number of interrupts entering the Main CPU System is fundamentally reduced, an interference source for awakening the Main CPU from a CPU state is reduced, the Main CPU System stays in a CPU power-off state for a long time as possible, and the dynamic power consumption of the Main CPU System is reduced.
While the invention has been described in connection with specific embodiments thereof, it is to be understood that it is intended by the appended drawings and description that the invention may be embodied in other specific forms without departing from the spirit or scope of the invention.
Claims (10)
1. A method for controlling processor interrupts, comprising:
receiving an interrupt sent to a main processor, and judging whether the interrupt meets a preset condition or not;
and filtering the interrupt meeting the preset condition, and sending the interrupt not meeting the preset condition to the main processor.
2. The method of claim 1, wherein said filtering operation comprises: and filtering or processing the interrupt meeting the preset condition.
3. The method of claim 1, wherein prior to receiving the interrupt to the host processor, the method further comprises:
and closing an interrupt path of the main processor and operating an interrupt filtering function.
4. The method of claim 1, wherein the preset condition comprises: the occurrence frequency of the interruption is greater than the preset frequency, or the interruption is invalid interruption.
5. A control architecture for processor interrupts, comprising: a main processor and an interrupt processor; the interrupt handler is to:
receiving an interrupt sent to a main processor, and judging whether the interrupt meets a preset condition or not;
and filtering the interrupt meeting the preset condition, and sending the interrupt not meeting the preset condition to the main processor.
6. The architecture according to claim 5, wherein the interrupt handler is configured to filter or process the interrupt meeting the predetermined condition.
7. The architecture for control of processor interrupts as set forth in claim 5, further comprising: the filtering function control module is interrupted, and the filtering function control module is interrupted,
and the interrupt filtering module is used for closing an interrupt path of the main processor and running an interrupt filtering function before receiving the interrupt sent to the main processor.
8. The architecture for controlling processor interrupts as set forth in claim 5, wherein the preset conditions comprise: the occurrence frequency of the interruption is greater than the preset frequency, or the interruption is invalid interruption.
9. The processor interrupt control architecture of claim 5, wherein the main processor and the interrupt handler are homogeneous processors.
10. The architecture of claim 5, wherein the main processor and the interrupt handler are heterogeneous processors and the power consumption of the interrupt handler is less than the power consumption of the main processor.
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