CN112968589B

CN112968589B - Control circuit and multiphase power converter applying same

Info

Publication number: CN112968589B
Application number: CN202110180770.9A
Authority: CN
Inventors: 陈惠强; 王建新
Original assignee: Hangzhou Silergy Semiconductor Technology Ltd
Current assignee: Hangzhou Silergy Semiconductor Technology Ltd
Priority date: 2021-02-08
Filing date: 2021-02-08
Publication date: 2022-05-24
Anticipated expiration: 2041-02-08
Also published as: CN112968589A

Abstract

The application discloses a control circuit and a multiphase power converter applying the same. The control circuit of the embodiment of the invention generates N ramp signals through the same ramp signal generating circuit, wherein the N ramp signals are generated according to N clock signals which are mutually staggered, the multiphase power converter respectively controls the corresponding power level circuits to start a new switching period in response to the N clock signals which are mutually staggered, and adjusts the conduction time of the power switch in each phase of power level circuit according to the corresponding ground current sampling signal and the ramp signal, so that the ramp compensation error between different phases is eliminated, the system stability is improved, and the inductive current between the different phases is controlled to realize current sharing.

Description

Control circuit and multiphase power converter applying same

Technical Field

The invention relates to power electronic technology, in particular to a multiphase power converter and a control circuit thereof.

Background

A power converter is a power conversion circuit capable of converting an input voltage into another fixed output voltage or an adjustable output voltage through different forms of architectures, and thus is widely used in electronic products such as mobile devices. To provide a stable output voltage with high accuracy over a wide range of load conditions, the power converter connects multiphase power stage circuits in parallel to form a multiphase power converter, and employs a multiphase controller to generate clock signals with different phase shifts to drive the multiphase power converter. In the current control mode, the difference between the average inductor current and the sensed inductor current can cause instability under certain operating conditions, which is known as subharmonic oscillation. This instability occurs when the inductor current ripple does not return to its initial value at the beginning of the next switching cycle under steady state operating conditions. Instability is particularly acute when the switches in each phase of the power stage circuit are on for more than 50% of a given switching period. To ensure stability, a ramp signal is added to the current sense signal to compensate to prevent or eliminate subharmonic oscillation.

However, in the multiphase power converter, a separate ramp signal generating circuit is required in each phase current control loop to generate a corresponding ramp signal, so that there is an error in ramp compensation between different phases, and the peak values of the inductive currents of different phases are greatly different, which results in non-uniform inductive currents of different phases on one hand, and on the other hand, because the input currents of different phases are greatly different, the purpose of reducing the input current ripple cannot be achieved, and at the same time, the voltage stress and heat imbalance of the switching devices in each phase are caused.

Disclosure of Invention

In view of the foregoing problems, an object of the present invention is to provide a multiphase power converter and a control circuit thereof, so as to eliminate a slope compensation error between different phases, improve system stability, and control an inductor current between different phases to achieve current sharing.

According to an aspect of the invention, there is provided a control circuit comprising: a ramp signal generation circuit configured to generate N ramp signals; and

n current modulators configured to control switching cycles of respective power stage circuits in response to N clock signals, respectively, and to control on-times of power switches in each phase of the power stage circuits in response to a current sampling signal characterizing inductor current in each phase of the power stage circuits and a respective ramp signal; wherein the ramp signal generation circuit is configured to generate the N ramp signals according to the N clock signals.

Preferably, the N ramp signals are configured to respectively rise at 1/N × Ts of each phase of the power stage circuit with a predetermined slope, Ts is a switching period of each phase of the power stage circuit, and N is larger than or equal to 2.

Preferably, the N ramp signals rise at a fixed slope at each phase of the power stage circuit 1/N × Ts-Ts, respectively.

Preferably, the N ramp signals rise at a first slope at 1/N × Ts-2/N × Ts of each phase of the power stage circuit and rise at a second slope at 2/N × Ts-Ts of each phase of the power stage circuit, respectively.

Preferably, the N ramp signals respectively rise at a first slope at 0-1/N Ts of each phase of the power stage circuit, and rise at a second slope at 1/N Ts-Ts of each phase of the power stage circuit, where N is 2.

Preferably, the ith ramp signal received by the ith current modulator is generated in response to an ith clock signal for controlling the (i + 1) th current modulator, and the Nth ramp signal received by the Nth current modulator is generated in response to a first clock signal for controlling the first current modulator, wherein i ≦ N-1.

Preferably, the ith ramp signal received by the ith current modulator is generated in response to an i +1 th clock signal for controlling the (i + 1) th current modulator and an i +2 th clock signal for controlling the (i + 2) th current modulator, the (N-1) th ramp signal received by the (N-1) th current modulator is generated in response to an N-th clock signal for controlling the Nth current modulator and a first clock signal for controlling the first current modulator, and the N-th ramp signal received by the Nth current modulator is generated in response to a first clock signal for controlling the first current modulator and a second clock signal for controlling the second current modulator, wherein i ≦ N-2.

Preferably, the N ramp signals are configured to have a fixed slope.

Preferably, the N ramp signals are configured to have a variable slope.

Preferably, each current modulator is configured to control the on-time of a power switch in each phase power stage circuit in accordance with a respective current sample signal, a ramp signal, and an error signal, wherein the error signal is generated in accordance with an error between a feedback voltage representing the output voltage of the multiphase power converter and a reference voltage.

Preferably, the control circuit further comprises a switch control signal generation circuit configured to receive the output signals of the N current modulators and generate N switch control signals to drive the N-phase power stage circuit.

Preferably, the ramp signal generating circuit includes:

a first current source, and

n capacitors, wherein each capacitor is coupled in parallel to the first current source, which charges the corresponding capacitor according to the N clock signals to generate the corresponding ramp signal.

Preferably, the ramp signal generating circuit includes:

a first current source for supplying a first current to the substrate,

a second current source, and

the number of the N capacitors is equal to the total number of the capacitors,

each capacitor is respectively coupled in parallel to the first current source and the second current source, and the first current source and the second current source respectively charge the corresponding capacitor according to the N clock signals to generate corresponding ramp signals.

Preferably, the phase difference of the N clock signals is 360 °/N.

According to another aspect of the invention there is provided a multiphase power converter comprising:

n power stage circuits for receiving an input voltage to generate an output voltage; and

any of the control circuits of the first aspect.

The control circuit of the embodiment of the invention generates N ramp signals through the same ramp signal generating circuit, wherein the N ramp signals are generated according to N clock signals which are mutually staggered, the multiphase power converter respectively controls the corresponding power level circuits to start a new switching period in response to the N clock signals which are mutually staggered, and adjusts the conduction time of the power switch in each phase of power level circuit according to the corresponding ground current sampling signal and the ramp signal, so that the ramp compensation error between different phases is eliminated, the system stability is improved, and the inductive current between the different phases is controlled to realize current sharing.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 is a circuit diagram of a multiphase power converter in accordance with an embodiment of the invention;

FIG. 2 is a circuit diagram of a control circuit in the present invention;

fig. 3 is a ramp signal generating circuit according to a first embodiment of the present invention;

fig. 4 is an operation waveform diagram of the ramp signal generating circuit according to the first embodiment of the present invention;

FIG. 5 is another waveform diagram illustrating the operation of the ramp signal generating circuit according to the first embodiment of the present invention;

fig. 6 is a ramp signal generating circuit of a second embodiment of the present invention;

fig. 7 is an operation waveform diagram of a ramp signal generating circuit according to a second embodiment of the present invention.

Detailed Description

The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.

Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

Meanwhile, it should be understood that, in the following description, a "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that the two be absent intermediate elements.

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".

In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.

Fig. 1 is a circuit diagram of a multiphase power converter in an embodiment of the invention. As shown in fig. 1, the multiphase power converter includes a multiphase power module 11 and a control circuit 12 for driving the multiphase power module 11. A multiphase power converter receives an input voltage Vin at an input i and produces an output voltage Vo at an output o for supply to a load. In the present embodiment, multiphase power module 11 includes N-phase power stage circuits P1-PN and N inductors L1-LN, which are driven by switch control signals PWM1-PWMN, respectively. Each power stage circuit includes a set of power switches that are controlled to turn on and off by respective switch control signals to regulate the output voltage Vo. The power level circuit Pi and the inductor Li are coupled between an input end i and an output end o of the multiphase power converter, wherein i is more than or equal to 1 and less than or equal to N. The output capacitor Co is coupled to the output o of the multiphase power converter to filter the output current to maintain the output voltage Vo constant. The output voltage Vo is used to drive the load Ro.

The control circuit 12 includes a ramp signal generating circuit (not shown) and N current modulators CP1-CPN, each corresponding to a phase of the multi-phase current control loop. In the present embodiment, each current modulator receives a corresponding current sampling signal V from the multiphase power module 11 respectively_CS1-V_CSNWherein each current sample signal is representative of an inductor current in each phase. The current modulators CP1-CPN also receive the phase-shifted clock signals CLK1-CLKN, respectively, for controlling the switching period of each phase of the power stage circuit. The ramp signal generating circuit is configured to generate a ramp signal V according to the clock signals CLK1-CLKN_SP1-V_SPN. For example, a first input of the first current modulator CP1 receives a first current sample signal V indicative of an inductor current IL1 of the first phase flowing through an inductor L1_CS1A second input terminal thereof receiving a ramp signal V_SP1The third input terminal receives the first clock signal CLK1 for controlling the power switches of the first phase power stage circuit. In the present embodiment, the clock signals CLK1-CLKN determine the frequency of the switch control signals PWM1-PWMN, respectively, and the current sample signal and the ramp signal determine the duty cycle of the switch control signals PWM1-PWMN, i.e., the percentage period of time that the power switches in each phase of the power stage are on relative to the total period of the switches. The control circuit 12 generates the ramp signal V by only one ramp signal generating circuit in the present embodiment_SP1-V_SPNTherefore, the error of slope compensation between different phases is eliminated, and the inductive current between different phases is controlled to realize current sharing.

In this embodiment, the clock signal may be generated by an internal clock circuit or may be externally provided. For example, the circuit may be internally used by a voltage controlled oscillator to generate the clock signal CLK, which is divided by a clock sequencer to generate the mutually out of phase clock signals CLK 1-CLKN. In the preferred embodiment, the clock signals CLK1-CLKN are 360/N out of phase.

In a preferred embodiment, the duty cycle of the power switch in the N-phase power stage circuit is Ts, and the corresponding ramp signal in each phase current control loop rises with a predetermined slope at 1/N × Ts of each phase power stage circuit. For example, a first ramp signal V_SP1The first phase power stage circuit starts generating at 1/N × Ts with a predetermined slope, where N ≧ 2. In one implementation, the slope of the N ramp signals is fixed, and it rises with a fixed slope at each phase of the power stage circuit 1/N × Ts-Ts, respectively. In another implementation, the slopes of the N ramp signals are variable, and rise at a first slope at 1/N × Ts-2/N × Ts of each phase of the power stage circuit and rise at a second slope at 2/N × Ts-Ts of each phase of the power stage circuit, respectively. It should be understood that the rising slopes of the N ramp signals are not limited to two slope changes, and the slope of the ramp signal may be changed at different times of the cycle of the switch, respectively, using segment control.

In this embodiment, the control circuit 12 adopts a peak current control mode, and the fourth input terminal of each current modulator also receives an error signal V_COMP. Each current modulator is responsive to a corresponding current sampling signal, a ramp signal and an error signal V_COMPAnd controlling the corresponding phase power stage circuit. In a preferred implementation, the control circuit 12 superimposes a ramp signal on the current sample signal to generate a current control signal in a per-phase current control loop, and based on the error signal V_COMPAnd the current control signal controls a power switch in each phase of the power stage circuit. The control circuit 12 is responsive to a feedback voltage V representative of the output voltage Vo_FBAnd a characterization periodReference signal V of desired output voltage_REFError between generates an error signal V_COMP. Feedback voltage V_FBCan be generated by a resistive voltage divider network connected to the output o of the multiphase power converter. In this embodiment, the resistor divider network includes resistors R1 and R2 connected in series. The control circuit 12 comprises an error amplifier GM having a first input receiving a feedback voltage V_FBA second input terminal thereof receiving a reference signal V_REFBy amplifying the feedback voltage V_FBAnd a reference signal V_REFError information between to generate an error signal V_COMPWherein the error signal V_COMPWhich may be a voltage signal or a current signal. In the embodiment, the filter circuit is connected to the output terminal of the error amplifier GM for converting the output current of the error amplifier GM into a voltage signal, so that the error signal V in the embodiment_COMPIs a voltage signal. In this embodiment, the filter circuit includes a resistor R and a capacitor C connected in series

In a preferred implementation, the ramp signal generating circuit is configured to receive the clock signals CLK1-CLKN and generate the ramp signal V_SP1-V_SPN. Ramp signal V_SP1-V_SPNThe slope of (b) is determined by the rising slope and the falling slope of the corresponding phase inductor current, and may be fixed or variable. In one implementation, the ramp signal V_SP1-V_SPNIs fixed, the ith ramp signal received by the ith current modulator is generated in response to the ith clock signal for controlling the (i + 1) th current modulator, and the nth ramp signal received by the nth current modulator is generated in response to the first clock signal for controlling the first current modulator, wherein i ≦ N-1. In another implementation, the ramp signal V_SP1-V_SPNIs generated in response to an i +1 th clock signal for controlling the i +1 th current modulator and an i +2 th clock signal for controlling the i +2 th current modulator, and an N-1 th ramp signal received by the N-1 th current modulator is generated in response to an N-th clock signal for controlling the N-th current modulator and an i +2 th clock signal for controlling the first current modulatorThe first clock signal is generated, and the Nth ramp signal received by the Nth current modulator is generated in response to the first clock signal for controlling the first current modulator and the second clock signal for controlling the second current modulator, wherein i is less than or equal to N-2.

The control circuit 12 further includes a switching control signal generation circuit for generating the switching control signals PWM1-PWMN based on the output signals of the current modulators CP 1-CPN. The switch control signals PWM1-PWMN are used to drive the N-phase power stage circuit. The control circuit 12 regulates the output voltage Vo by controlling the duty cycle of the power switches in each phase of the power stage.

In contrast to the prior art, the control circuit 12 feeds back the voltage V_FBAnd voltage loop control is realized, and current loop control is realized through the current detection signal. The control circuit 12 controls the switching control signal to start a new switching cycle in response to the clock signal, and adjusts the duty cycle of the switching control signal according to the current sampling signal and the ramp signal. The control circuit 12 generates the ramp signals V respectively according to the N clock signals which are mutually staggered by the same ramp signal generating circuit_SP1-V_SPNThe error of slope compensation between different phases is eliminated, and therefore the current sharing of the inductive current between different phases is achieved.

Fig. 2 is a circuit diagram of a control circuit in the present invention. As shown in fig. 2, the control circuit includes the current modulators CP1-CPN and a switch control signal generation circuit. Each current modulator includes a superimposing circuit and an error amplifier. For example, the first current modulator CP1 includes a superimposing circuit 201 and an error amplifier GM 1. The superposition circuit 201 samples the first current signal V_CS1And a first ramp signal V_SP1Are superposed to generate a first current control signal V_C1. A first input (e.g. a non-inverting input) of the error amplifier GM1 receives a first current control signal V_C1A second input terminal (e.g., an inverting input terminal) of which receives the error signal V_COMPBy comparing the first current control signal V_C1And an error signal V_COMPThe error control switch control signal generation circuit therebetween generates the first switch control signal PWM 1. The switch control signal generating circuit comprises N RS triggers. Setting of each RS flip-flopThe terminals receive corresponding clock signals for controlling the switching period of the corresponding switching control signals, and the reset terminals are connected to the output terminals of the corresponding error amplifiers for controlling the duty ratios of the corresponding switching control signals. For example, the set terminal of the first RS flip-flop receives the first clock signal CLK1 for controlling the switching period of the first switching control signal PWM1, and the reset terminal is connected to the output terminal of the error amplifier GM1 for controlling the duty ratio of the first switching control signal PWM 1. Therefore, the duty ratio of the switch control signal is controlled by the current sampling signal and the ramp signal, and the period of the switch control signal is determined by the clock signal. It should be understood that, in the present embodiment, the current control signal is generated by superimposing the ramp signal and the current sampling signal, and other circuits capable of implementing the above functions are within the scope of the present invention. For example, the first input terminal of the error amplifier receives the first current sampling signal V_CS1A second input terminal of which receives an error signal V_COMPAnd a ramp signal V_SP1The difference of (a).

Fig. 3 is a ramp signal generating circuit according to a first embodiment of the present invention. As shown in FIG. 3, the two-phase power converter is taken as an example of the present embodiment, and the ramp signal generating circuit generates the ramp signal V_SP1And V_SP2And a ramp signal V_SP1And V_SP2Is fixed. The ramp signal generating circuit comprises an RS trigger, a set end of the RS trigger receives a first clock signal CLK1 used for controlling the switching period of the first-phase power-stage circuit, a reset end of the RS trigger receives a second clock signal CLK2 used for controlling the switching period of the second-phase power-stage circuit, and output ends of the RS trigger respectively generate a first signal SL1 and a second signal SL 2. The ramp signal generating circuit further comprises a current source I1, a first capacitor C1 and a second capacitor C2. The first capacitor C1 is connected in parallel across the current source I1 through the switch K1, and the second capacitor C2 is connected in parallel across the current source I1 through the switch K2, wherein the switch K1 is controlled by the second signal SL2, and the switch K2 is controlled by the first signal SL 1. The switch K3 is connected in parallel to two ends of the first capacitor C1 and controlled by the first signal SL1, and the switch K4 is connected in parallel to two ends of the second capacitor C2 and the second signal SL 2. When the first clock signal CLK1 is asserted and the second clock signal is de-asserted, the first signal SL1 is switched to be assertedWhen the level is high, the switches K2 and K3 are turned on, the switches K1 and K4 are turned off, and the current source I1 charges the second capacitor C2 to generate the second ramp signal V_SP2While the first ramp signal V_SP1Reset to zero. When the second clock signal CLK2 is asserted and the first clock signal CLK1 is de-asserted, the second signal SL2 is switched to an active level, the switches K1 and K4 are turned on, the switches K2 and K3 are turned off, and the current source I1 charges the first capacitor C1 to generate the first ramp signal V_SP1While the second ramp signal V_SP2Reset to zero. First ramp signal V_SP1The second ramp signal V is generated when the second phase power stage circuit starts to work_SP2Generated when the first phase circuit power stage circuit begins to operate.

Fig. 4 is an operation waveform diagram of the ramp signal generating circuit according to the first embodiment of the present invention. As shown in fig. 4, the switching period length is Ts by dividing the clock signal CLK to generate clock signals CLK1 and CLK2 that are 180 ° out of phase with each other. The first clock signal CLK1 is used to control a first current modulator corresponding to a first phase power stage circuit, and the second clock signal CLK2 is used to control a second current modulator corresponding to a second phase power stage circuit. The first ramp signal V is asserted when the second clock signal CLK2 is asserted_SP1Rising from zero, second ramp signal V_SP2Reset to zero. The first ramp signal V is asserted when the first clock signal CLK1 is asserted_SP1Reset to zero while the second ramp signal V_SP2Starting from zero and rising. First ramp signal V_SP1The second ramp signal V is generated in response to the second clock signal CLK2_SP2Is generated in response to the first clock signal CLK1 such that the first ramp signal V_SP1And a second ramp signal V_SP2The current sampling signals are respectively compensated at 1/2 × Ts corresponding to the power stage circuit, so that the multiphase power converter is prevented from generating secondary slope oscillation when the multiphase power converter is conducted for more than 50% of a given switching period, the system stability is improved, slope compensation errors in the two-phase power stage circuit are eliminated, and the two-phase inductive current sharing is realized.

In a two-phase power converter, ramp compensation is added just at 1/2 × Ts of the corresponding power stage circuit in order to prevent ramp signalThe control circuit may also add ramp compensation from 0-1/2 Ts, as shown in fig. 5, to the delay of the signal generation circuit. In fig. 5, the two-phase power converter adds slope compensation in the whole switching period, so as to avoid slight instability of the two-phase power converter caused by the delay of the slope signal generating circuit. First ramp signal V_SP1And a second ramp signal V_SP2The first slope is provided at 0-1/2 × Ts of the corresponding power stage circuit, and the second slope is provided at 1/2 × Ts-Ts of the corresponding power stage circuit. The first ramp signal V is asserted when the first clock signal CLK1 is asserted_SP1When the first phase power stage circuit rises at a first slope from 0-1/2 × Ts, the first ramp signal V is asserted when the second clock signal CLK2 is asserted_SP1At 1/2 Ts-Ts continues to rise with a second slope. The second ramp signal V is asserted when the second clock signal CLK2 is asserted_SP2When the second phase power stage circuit rises at a first slope from 0 to 1/2 × Ts, the second ramp signal V is asserted when the first clock signal CLK1 is asserted_SP2And the 1/2 × Ts-Ts of the second phase power stage circuit continuously rises with a second slope.

Fig. 6 is a ramp signal generating circuit according to a second embodiment of the present invention. As shown in fig. 6, in the present embodiment, taking a three-phase power converter as an example, the ramp signal generating circuit generates a ramp signal V_SP1、V_SP2And V_SP3And a ramp signal V_SP1、V_SP2And V_SP3Is variable. The ramp signal generating circuit includes three RS flip-flops. The set terminal of the first RS flip-flop RS1 receives a first clock signal CLK1 for controlling the switching period of the first phase power stage circuit, the reset terminal receives a second clock signal CLK2 for controlling the switching period of the second phase power stage circuit, and the output terminal generates a first signal SL 1. The set terminal of the second RS flip-flop RS2 receives a second clock signal CLK2 for controlling the switching period of the second phase power stage circuit, the reset terminal receives a third clock signal CLK3 for controlling the switching period of the third phase power stage circuit, and the output terminal generates a second signal SL 2. The set terminal of the third RS flip-flop RS3 receives a third clock signal CLK3 for controlling the switching period of the third phase power stage circuit, and the reset terminal receives a third clock signal CLK3 for controlling the switching period of the first phase power stage circuitA clock signal CLK1, and an output terminal generates a third signal SL 3.

The ramp signal generating circuit further comprises a first current source I1, a second current source I2, a first capacitor C1, a second capacitor C2 and a third capacitor C3. The first capacitor C1 is connected in parallel to two ends of the current source I1 through a switch K11, the second capacitor C2 is connected in parallel to two ends of the current source I1 through a switch K12, the third capacitor C3 is connected in parallel to two ends of the current source I1 through a switch K13, the switch K14 is connected in parallel to two ends of the first capacitor C1, the switch K15 is connected in parallel to two ends of the second capacitor C2, and the switch K16 is connected in parallel to two ends of the third capacitor C3, wherein the switches K12 and K14 are controlled by a first signal SL1, the switches K13 and K15 are controlled by a second signal SL2, and the switches K11 and K16 are controlled by a third signal SL 3. The second current source I2 is connected in parallel to two ends of the first capacitor C1 through a switch K6, connected in parallel to two ends of the second capacitor C2 through a switch K7, and connected in parallel to two ends of the third capacitor C3 through a switch K8, wherein the switch K7 is controlled by the third signal SL3, the switch K6 is controlled by the second signal SL2, and the switch K8 is controlled by the first signal SL 1.

When the first clock signal CLK1 is active and the second and third clock signals CLK2 and CLK3 are inactive, the first signal SL1 switches to an active level, the switches K8, K12 and K14 are turned on, and the switches K15 and K16 are turned off. The second current source I2 charges the third capacitor C3 to generate a third ramp signal V with a first slope_SP3(ii) a The first current source I1 charges the second capacitor C2 and generates a second ramp signal V with a second slope_SP2(ii) a At the same time, the first capacitor C1 discharges, and the first ramp signal V_SP1And is reduced to zero.

When the second clock signal CLK2 is active and the first clock signal CLK1 and the third clock signal CLK3 are inactive, the second signal SL2 is switched to an active level, the switches K6, K13 and K15 are turned on, and the switches K14 and K16 are turned off. The first current source I1 charges the third capacitor C3 and generates a third ramp signal V with a second ramp rate_SP3(ii) a The second current source I2 charges the first capacitor C1 and generates a first ramp signal V with a first slope_SP1(ii) a At the same time, the second capacitor C2 discharges, and the second ramp signal V_SP2And is reduced to zero.

When it comes toWhen the three clock signal CLK3 is active and the first clock signal CLK1 and the second clock signal CLK3 are inactive, the third signal SL3 switches to an active level, the switches K7, K11, and K16 are turned on, and the switches K14 and K15 are turned off. The second current source I2 charges the second capacitor C2 to generate a second ramp signal V with a first slope_SP2(ii) a The first current source I1 charges the first capacitor C1 and generates a first ramp signal V with a second slope_SP1(ii) a At the same time, the third capacitor C3 discharges, and the third ramp signal V_SP3And is reduced to zero. First ramp signal V_SP1The second ramp signal V is generated when the second phase power stage circuit starts to work_SP2A third slope signal V generated when the power stage circuit of the third phase circuit starts to work_SP3Generated when the next new switching cycle of the first phase power stage circuit begins to operate.

Compared with the ramp signal generating circuit in the first embodiment, the ramp signal generating circuit in the present embodiment adds the second current source, so that the slope of the ramp signal can be controlled to gradually increase, the ramp compensation can be better adjusted, and the system stability can be improved. It should be understood that the ramp signal generating circuit in this embodiment may also generate a ramp signal with a fixed slope. For example, the first current source and the second current source generate the same current, or only the first current source is used to charge the corresponding capacitor to generate the corresponding ramp signal.

Fig. 7 is an operation waveform diagram of a ramp signal generating circuit according to a second embodiment of the present invention. As shown in fig. 7, the clock signals CLK1, CLK2, and CLK3, which are 120 ° out of phase with each other, are generated by dividing the clock signal CLK, and have a period Ts.

The first clock signal CLK1 is used to control a first current modulator corresponding to a first phase power stage circuit, the second clock signal CLK2 is used to control a second current modulator corresponding to a second phase power stage circuit, and the third clock signal CLK3 is used to control a third current modulator corresponding to a third phase power stage circuit. The second ramp signal V is asserted when the second clock signal CLK2 is asserted_SP2Reset to zero while the first ramp signal V_SP1Rising with a first slope from zero, the first slope signal being active when the third clock signal CLK3 is activeNumber V_SP1Continuing to rise with the second slope. The third ramp signal V is asserted when the third clock signal CLK3 is asserted_SP1Reset to zero while the second ramp signal V_SP2Rising with a first slope from zero, the second ramp signal V being active while the first clock signal CLK1 is active_SP2Continuing to rise with the second slope. The first ramp signal V is asserted when the first clock signal CLK1 is asserted_SP1Reset to zero and at the same time a third ramp signal V_SP3Starting from zero and rising with a first slope. The third ramp signal V while the second clock signal CLK2 is active_SP3Continuing to rise with the second slope.

In the present embodiment, the first ramp signal V_SP1The second ramp signal V is generated in response to the second clock signal CLK2 and the third clock signal CLK3_SP2The third ramp signal V is generated in response to the third clock signal CLK3 and the first clock signal CLK1_SP3Is generated in response to the first clock signal CLK1 and the second clock signal CLK2 such that the first ramp signal V_SP1A second ramp signal V_SP2And a third ramp signal V_SP3The current sampling signals are compensated at 1/3 × Ts of the corresponding power stage circuit, so that sub-slope oscillation of the multiphase power converter is avoided when the multiphase power converter is conducted for more than 50% of a given switching period, the system stability is improved, slope compensation errors in the two-phase power stage circuit are eliminated, and current sharing of two-phase inductive current is realized.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A control circuit for a multiphase power converter including N-phase power stage circuits coupled in parallel, the control circuit comprising:

a ramp signal generation circuit configured to generate N ramp signals; and

n current modulators configured to control switching cycles of respective power stage circuits in response to N clock signals, respectively, and to control on-times of power switches in each phase of the power stage circuits in response to a current sampling signal characterizing inductor current in each phase of the power stage circuits and a respective ramp signal; the ramp signal generating circuit is configured to generate the N ramp signals according to the N clock signals, the N ramp signals are configured to respectively rise at a preset slope at 1/N × Ts of each phase of power stage circuit, Ts is a switching period of each phase of power stage circuit, and N is larger than or equal to 2.

2. The control circuit of claim 1, wherein the N ramp signals rise at a fixed slope at 1/N x Ts-Ts per phase of the power stage circuit, respectively.

3. The control circuit of claim 1, wherein the N ramp signals rise at a first slope at 1/NxTs-2/NxTs of each phase of the power stage circuit and at a second slope at 2/NxTs-Ts of each phase of the power stage circuit, respectively, and N ≧ 3.

4. The control circuit of claim 1, wherein the N ramp signals rise at a first slope at 0-1/N Ts of each phase of the power stage circuit and at a second slope at 1/N Ts-Ts of each phase of the power stage circuit, respectively, wherein N is 2.

5. The control circuit of claim 1, wherein the ith ramp signal received by the ith current modulator is generated in response to an ith clock signal for controlling the (i + 1) th current modulator, and the nth ramp signal received by the nth current modulator is generated in response to a first clock signal for controlling the first current modulator, wherein 1 ≦ i ≦ N-1.

6. The control circuit of claim 1, wherein the ith ramp signal received by the ith current modulator is generated in response to an i +1 th clock signal for controlling the (i + 1) th current modulator and an i +2 th clock signal for controlling the (i + 2) th current modulator, wherein the N-1 st ramp signal received by the (N-1) th current modulator is generated in response to an nth clock signal for controlling the nth current modulator and a first clock signal for controlling the first current modulator, and wherein the nth ramp signal received by the nth current modulator is generated in response to a first clock signal for controlling the first current modulator and a second clock signal for controlling the second current modulator, wherein 1 ≦ i ≦ N-2.

7. The control circuit of claim 1, wherein the N ramp signals are configured to have a fixed slope.

8. The control circuit of claim 1, wherein the N ramp signals are configured to have a variable slope.

9. The control circuit of claim 1, wherein each current modulator is configured to control a conduction time of a power switch in each phase power stage circuit according to a corresponding current sample signal, a ramp signal, and an error signal, wherein the error signal is generated according to an error between a feedback voltage representing an output voltage of the multiphase power converter and a reference voltage.

10. The control circuit of claim 1, further comprising a switch control signal generation circuit configured to receive the output signals of the N current modulators and generate N switch control signals to drive the N-phase power stage circuit.

11. The control circuit of claim 1, wherein the ramp signal generating circuit comprises:

a first current source, and

12. The control circuit of claim 1, wherein the ramp signal generating circuit comprises:

a first current source for supplying a first current to the substrate,

a second current source, and

the number of the N capacitors is equal to the total number of the capacitors,

13. The control circuit of claim 1, wherein the N clock signals are 360 °/N out of phase.

14. A multiphase power converter comprising:

a control circuit as claimed in any one of claims 1 to 13.