CN112956023B - 倒装芯片堆叠结构及其形成方法 - Google Patents
倒装芯片堆叠结构及其形成方法 Download PDFInfo
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- CN112956023B CN112956023B CN202180000449.6A CN202180000449A CN112956023B CN 112956023 B CN112956023 B CN 112956023B CN 202180000449 A CN202180000449 A CN 202180000449A CN 112956023 B CN112956023 B CN 112956023B
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Abstract
本公开包括一种半导体封装,所述半导体封装包括具有与输入/输出(I/O)触点接触的第一表面和与第一表面相对的第二表面的再分布层(RDL)。半导体封装还包括形成在RDL的第二表面上并且与RDL电连接的阶梯互连结构。该阶梯互连结构包括阶梯层,所述阶梯层包括第一阶梯层和堆叠在第一阶梯层的顶表面上的第二阶梯层。第二阶梯层覆盖第一阶梯层的顶表面的一部分,使得第一阶梯层的顶表面的剩余部分被暴露。集成电路(IC)芯片经由阶梯互连结构电连接到RDL。IC芯片中的第一IC芯片通过第一阶梯层的顶表面的剩余部分电连接到RDL。
Description
技术领域
本公开总体上涉及半导体技术领域,并且更具体地涉及用于多芯片封装的方法。
背景技术
芯片封装是现代半导体微型化的重要方面。多个集成电路(IC)被装到单个封装中,以实现同构或异构芯片集成。例如,存储芯片和控制逻辑单元可以被集成到单个封装中,以实现更低的制作成本、减小的器件占据空间和改善的器件性能。为了解决平面存储单元中的密度限制,开发出了三维(3D)存储架构。然而,随着器件特征尺寸和封装尺寸接近下限,创建足够数量的输入/输出(I/O)触点变得越来越具有挑战性,尤其是对于通过字线和位线的阵列对存储位寻址的平面存储芯片或3D存储芯片而言。
发明内容
本公开包括半导体封装,该半导体封装包括具有与输入/输出(I/O)触点接触的第一表面和与第一表面相对的第二表面的再分布层(RDL)。该半导体封装还包括形成在RDL的第二表面上并且与RDL电连接的阶梯互连结构。该阶梯互连结构包括阶梯层,所述阶梯层包括第一阶梯层和堆叠在第一阶梯层的顶表面上的第二阶梯层。第二阶梯层覆盖第一阶梯层的顶表面的一部分,使得第一阶梯层的顶表面的剩余部分被暴露。集成电路(IC)芯片经由阶梯互连结构电连接到RDL。IC芯片中的第一IC芯片通过第一阶梯层的顶表面的剩余部分电连接到RDL。
本公开还包括用于形成半导体封装结构的方法。该方法包括:提供载体衬底;以及在载体衬底上形成阶梯互连结构。形成阶梯互连结构包括:形成第一阶梯层;以及在第一阶梯层的顶表面上形成第二阶梯层。第二阶梯层覆盖第一阶梯层的顶表面的一部分,使得第一阶梯层的顶表面的剩余部分被暴露。该方法还包括将集成电路(IC)芯片倒转安装在载体衬底之上和阶梯互连结构上。倒转安装IC芯片包括将IC芯片中的第一IC芯片通过第一阶梯层的顶表面的剩余部分电连接到第一阶梯层。该方法还包括采用再分布层(RDL)代替载体衬底。该方法还包括通过将第一IC芯片通过第一阶梯层的顶表面的剩余部分电连接到RDL而将IC芯片通过阶梯互连结构电连接到RDL。
附图说明
在和附图一起阅读时,根据以下具体实施方式更好地理解本公开的方面。应当指出,根据本行业中的惯例,各种特征并非是按比例绘制的。实际上,为了说明和讨论的清楚起见,可以任意增加或者减小各种特征的尺寸。
图1示出了根据本公开的一些实施例的用于形成堆叠倒装芯片封装的示例性制作工艺。
图2-12示出了根据本公开的一些实施例的并入形成在堆叠芯片的一端上的阶梯互连结构的堆叠倒装芯片封装的截面图。
图13和图14示出了根据本公开的一些实施例的并入形成在堆叠芯片的两端上的阶梯互连结构的堆叠倒装芯片封装的截面图。
图15和图16示出了根据本公开的一些实施例的并入形成在阶梯互连结构之间的接触焊盘的堆叠倒装芯片封装的截面图。
现在将参考附图描述说明性实施例。在附图中,相似的附图标记一般指示等同的、功能上类似的、和/或结构上类似的元件。
具体实施方式
尽管讨论了特定的构造和布置,但是应当理解,这样做仅出于说明的目的。相关领域中的技术人员将认识到,在不脱离本公开的精神和范围的情况下,可以使用其他构造和布置。对于相关领域中的技术人员将显而易见的是,本公开也可以用在多种其他应用中。
注意,说明书中对“一个实施例”、“实施例”、“示例性实施例”、“一些实施例”等的引用指示所描述的实施例可以包括特定的特征、结构、或特性,但每个实施例不一定都包括该特定的特征、结构、或特性。而且,这样的短语不一定指相同的实施例。此外,当结合实施例描述特定的特征、结构或特性时,无论是否明确描述,结合其他实施例来实现这样的特征、结构或特性将在相关领域中的技术人员的知识范围内。
通常,可以至少部分地根据上下文中的使用来理解术语。例如,至少部分地根据上下文,本文所使用的术语“一个或多个”可以用于描述单数意义上的任何特征、结构、或特性,或者可以用于描述复数意义上的特征、结构、或特性的组合。类似地,至少部分地根据上下文,诸如“一个”或“所述”的术语可以同样被理解为表达单数用法或表达复数用法。
应当容易理解,在本公开中“上”、“上方”和“之上”的含义应当以最广义的方式进行解释,使得“上”不仅意味着“直接在某物上”,而且还包括“在某物上”并且其间具有中间特征或层的含义,并且“上方”或“之上”不仅意味着在某物“上方”或“之上”的含义,而且还包括在某物“上方”或“之上”并且其间没有中间特征或层(即,直接在某物上)的含义。
此外,为了便于描述,在本文中可以使用诸如“之下”、“下方”、“下部”、“底部”、“上方”、“之上”、“上部”、“顶部”等空间相对术语,以描述一个元件或特征与另一个(一个或多个)元件或(一个或多个)特征的如图中所示的关系。例如,顶表面和底表面分别指形成在元件的相对侧上的第一和第二主表面。除了在图中描述的取向以外,空间相对术语还旨在涵盖器件在使用或操作中的不同取向。装置可以以其他方式定向(旋转90度或以其他取向),并且在本文使用的空间相对描述语可以以类似方式被相应地解释。
如本文所使用的,术语“衬底”是指在其上添加了后续材料层的材料。衬底包括顶表面和底表面。衬底的顶表面是形成半导体器件的地方,并且因此半导体器件形成在衬底的顶侧处。底表面与顶表面是相对的,并且因此衬底的底侧与衬底的顶侧是相对的。衬底本身可以被图案化。添加到衬底顶部上的材料可以被图案化或可以保持未被图案化。此外,衬底可以包括各种各样的半导体材料,例如硅、锗、砷化镓、磷化铟等。替代性地,衬底可以由非导电材料制成,例如玻璃、塑料、或蓝宝石晶圆。
如本文所使用的,术语“层”是指包括具有厚度的区域的材料部分。层可以在整个下层结构或上覆结构之上延伸,或者可以具有小于下层结构或上覆结构的范围。此外,层可以是均质或不均质连续结构的区域,所述区域具有的厚度小于连续结构的厚度。例如,层可以位于在连续结构的顶表面和底表面之间或在连续结构的顶表面和底表面处的任何一对水平平面之间。层可以水平地、垂直地和/或沿着锥形表面延伸。衬底可以是一层,可以在其中包括一个或多个层,和/或可以在其上、其上方和/或其下方具有一个或多个层。层可以包括多层。例如,互连层可以包括一个或多个导体和接触层(在其中形成触点、互连线、和/或过孔)和一个或多个电介质层。
如本文所使用的,术语“标称的/标称地”是指在产品或工艺的设计阶段期间设置的用于部件或工艺操作的特性或参数的期望值或目标值,以及高于和/或低于期望值的值的范围。值的范围可以归因于制造工艺或公差的微小变化。如本文所使用的,术语“约”指示可以基于与主题半导体器件相关联的特定技术节点而变化的给定量的值。基于特定的技术节点,术语“约”可以指示在例如该值的10%-30%(例如,该值的±10%、±20%或±30%)内变化的给定量的值。
如本文所使用的,术语“3D NAND存储器件(在本文中称为“存储器件”)”是指半导体器件,该半导体器件在横向定向的衬底上具有垂直定向的3D NAND存储单元晶体管串(在本文中称为“存储串”,例如NAND串或3D NAND串),使得存储串相对于衬底在垂直方向上延伸。如本文所使用的,术语“垂直的/垂直地”意味着标称地垂直于衬底的横向表面。
如本文所使用的,例如,术语“设置”是指通过诸如沉积、附接或放置的方法形成或者以其它方式创建或定位的。
在本公开中,术语“水平的/水平地”是指标称地平行于衬底的横向表面。
集成电路封装往往是半导体器件制作的最终阶段。多个集成电路(例如,芯片)被包装到单个封装中,以实现同构或异构芯片集成。封装为包含在封装中的内容提供保护,并且实现对通往和来自外部电路的电源和信号的访问。诸如扇出晶圆级封装(FOWLP)和扇出面板级封装(FOPLP)的扇出封装技术被开发出来,以实现更低的制作成本、减小的器件占据空间和改善的器件性能。在FOWLP工艺中,个体的芯片被设置在晶圆形状的衬底上,所述衬底具有定位在每个管芯之间的空间以用于额外的输入/输出(I/O)连接点。之后,将芯片嵌入在模制化合物内。再分布层(RDL)被形成为从***中的模制化合物区域对芯片上的I/O连接重新布线。切割机能够将芯片与形成在晶圆形状的衬底上的完全封装阵列分开,以形成个体的半导体封装。然而,由于常规的大尺寸晶圆约为300mm,因而能够制造并且封装在晶圆上的半导体器件的量被限制。FOPLP工艺被开发出来,从而相较于FOWLP工艺提供了增加的封装能力。在FOPLP工艺中,芯片被设置在衬底级面板上而非晶圆状衬底上以增加封装能力。例如,衬底级面板可以是具有长度为500mm或600mm的一侧的方形面板。
对于FOWLP工艺和FOPLP工艺两者而言,支持用于堆叠存储器件(例如,3D NAND存储芯片)的I/O连接的量变得越来越具有挑战性。随着对更高存储容量的需求的持续增加,存储单元和阶梯结构的垂直级数也随之增加。例如,64级3D NAND存储器件可以包括两个彼此叠加形成的32级阶梯结构。类似地,128级3D NAND存储器件可以包括两个64级阶梯结构。随着器件临界尺寸的不断缩小,为扇出封装中的存储芯片提供足够量的I/O连接变得越来越具有挑战性。
在本公开中描述的各种实施例并入了用于扇出封装中的存储芯片的堆叠阶梯互连结构。堆叠阶梯互连结构能够通过形成在堆叠阶梯互连结构的每一级上的柱状凸块提供通往堆叠IC芯片中的每个IC芯片的电连接,这继而增加了I/O连接点的数量。本文描述的实施例使用扇出封装作为示例,并且能够应用于其他封装技术。
图1是根据一些实施例的用于制作并入阶梯互连结构的多芯片封装的方法100的流程图。出于说明性目的,将参考制作如图2-12中所示的封装结构200以及图13和图14中的封装结构1300的示例性制作工艺来描述图1中所示的操作。取决于具体的应用,可以按照不同顺序执行操作或者不执行操作。应当指出,方法100可以不生产完整的半导体器件。相应地,应当理解,可以在方法100之前、期间和之后提供额外的工艺,并且本文仅简要描述了一些其他工艺。
根据一些实施例,参考图1,在操作105中,在载体衬底上形成接触焊盘。例如,接触焊盘208形成在载体衬底202上,如参考图2中所示的封装结构200所描述的。出于说明的清楚起见,图2包括封装结构200的各种图示。例如,图2包括示出接触焊盘208和衬底202的侧视图210和对应的平面图220。接触焊盘208可以设置在封装结构200的第一封装204和第二封装206内。第一封装204和第二封装206可以在封装边界205处分开。额外的IC芯片可以设置在封装结构200上,但是为了简单起见在图2中未示出。在一些实施例中,包括在第一封装204和第二封装206中的IC芯片可以是相同或不同的,取决于器件设计和预期功能。
载体衬底202可以包括用于半导体封装的任何适当的材料。例如,衬底载体可以包括玻璃、氮化镓、砷化镓、III-V族化合物、玻璃、塑料板、硅、硅锗、碳化硅、绝缘体上硅(SOI)、绝缘体上锗(GIO)、任何其他适当的材料和/或它们的组合。
接触焊盘208可以使用导电材料形成,并且形成在载体衬底202的顶表面上。接触焊盘208可以用于接下来形成I/O连接。在一些实施例中,可以形成一行或多行接触焊盘208。作为示例,第一封装204包括至少三行接触焊盘208a、208b和208c,而第二封装206则包括至少两行接触焊盘208c和208d,如图2中的平面图220中所示。在一些实施例中,接触焊盘208可以嵌入在载体衬底202内,其中,接触焊盘208的顶表面和载体衬底202的顶表面基本上共面。在一些实施例中,接触焊盘208可以由钨(W)、钴(Co)、铜(Cu)、铝(Al)、银(Ag)、金(Au)、掺杂硅、硅化物、氮化钛(TiN)、氮化钽(TaN)、任何适当的材料和/或它们的组合形成。在一些实施例中,接触焊盘208可以通过毯式(blanket)沉积工艺和随后的图案化工艺来设置。在一些实施例中,接触焊盘208可以从朝向第一封装204和第二封装206的中心延伸的***区域被设置,如图2中所示。在图2中未示出的一些实施例中,接触焊盘208可以形成在第一封装204和第二封装206的中心区域中。在一些实施例中,接触焊盘208可以形成在第一封装204的***区域中,并且形成在第二封装206的中心区域中。在一些实施例中,接触焊盘208可以使用沉积技术被设置,所述沉积技术包括但不限于化学气相沉积(CVD)、可流动CVD(FCVD)、溅射、金属有机CVD(MOCVD)、等离子体增强CVD(PECVD)、低压CVD(LPCVD)、物理气相沉积(PVD)、高密度等离子体(HDP)、任何适当的沉积技术和/或它们的组合。
根据一些实施例,再次参考图1,在操作110中,在载体衬底上形成电介质层和阻隔层。例如,如图3中所示,可以在封装结构200的第一封装204和第二封装206中的载体衬底202上形成电介质层310和阻隔层314。
电介质层310可以通过将电介质材料毯式沉积在载体衬底202上被设置,包括毯式沉积在载体衬底202的顶表面上和接触焊盘208的暴露表面上。可以使用图案化工艺来去除毯式沉积的电介质材料的部分,使得电介质材料的剩余部分能够形成电介质层310。在一些实施例中,电介质层310可以由绝缘材料形成,所述绝缘材料例如氧化硅、氮化硅、氮氧化硅、碳化硅、碳氧化硅、任何适当的绝缘材料和/或其组合。在一些实施例中,设置电介质层310可以包括任何适当的沉积技术,包括但不限于CVD、FCVD、溅射、MOCVD、PECVD、LPCVD、PVD、HDP、任何适当的沉积技术和/或它们的组合。
阻隔层314可以设置在电介质层310之间并且在载体衬底202和接触焊盘208的顶表面上。在一些实施例中,阻隔层314可以通过将电介质材料毯式沉积在电介质层310、载体衬底202的顶表面和接触焊盘208的暴露表面(例如,顶表面和侧壁)上被设置。可以执行图案化工艺或抛光工艺,使得所沉积的材料保留在相邻电介质层310之间,并且使阻隔层314的顶表面和电介质层310的顶表面基本上共面。例如,可以使用化学机械抛光(CMP)工艺。在一些实施例中,阻隔层314和电介质层310由不同材料形成。例如,阻隔层314和电介质层310可以使用针对彼此具有高蚀刻选择性(例如,大于约10)的材料被设置。例如,阻隔层314可以使用氧化硅形成,并且电介质层310可以使用氮氧化硅形成。在一些实施例中,阻隔层314可以由绝缘材料形成,绝缘材料例如氧化硅、氮化硅、氮氧化硅、碳化硅、碳氧化硅、任何适当的绝缘材料和/或它们的组合。在一些实施例中,阻隔层314的沉积工艺可以包括任何适当的沉积技术,包括但不限于CVD、FCVD、溅射、MOCVD、PECVD、LPCVD、PVD、HDP、任何适当的沉积技术和/或它们的组合。在一些实施例中,阻隔层314可以由光刻胶材料形成,并且可以通过旋涂工艺被沉积。在一些实施例中,可以对所沉积的光刻胶材料施加退火工艺,以增强其物理耐久性。
根据一些实施例,再次参考图1,在操作115中,在电介质层中形成第一阶梯层的垂直互连。例如,如图4中所示,可以在封装结构200的第一封装204和第二封装206中的电介质层310中设置垂直互连418。
垂直互连418可以是通过在电介质层310中蚀刻出开口并且在开口中沉积导电材料而设置的导电线。在一些实施例中,垂直互连418可以通过镶嵌工艺或者双重镶嵌工艺被设置。在一些实施例中,垂直互连418可以由导电材料形成,所述导电材料例如铜、钴、钨、铝、金、银、任何适当的导电材料及它们的组合。在一些实施例中,可以毯式沉积该导电材料直到填充开口为止。可以使用平坦化工艺(例如,CMP工艺),使得剩余导电材料的顶表面和电介质层310的顶表面基本上共面。
根据一些实施例,再次参考图1,在操作120中,在电介质层中形成用于第一阶梯层的水平互连。例如,如图5中所示,可以在封装结构200的第一封装204和第二封装206中的电介质层514中设置水平互连518。水平互连518和垂直互连418可以形成阶梯互连结构的最低互连级。阶梯互连结构可以由多个互连级形成,其中,每个互连级在本公开中又被称为阶梯互连结构的“阶梯层”(或“SC层”)。例如,根据一些实施例,第一阶梯层502可以被形成为包括垂直互连418和水平互连518。
电介质层510和阻隔层514可以分别设置在电介质层310和阻隔层314上。在一些实施例中,电介质层510可以使用与电介质层310的那些类似的沉积方法和材料成分被设置。例如,电介质层310和510可以由氧化硅、氮化硅或氮氧化硅形成。类似地,阻隔层514可以使用与阻隔层314的那些类似的沉积方法和材料成分被设置。例如,阻隔层314和514可以由光刻胶材料形成。
水平互连518可以是通过在电介质层510中蚀刻出开口并且在开口中沉积导电材料而设置的导电线。在一些实施例中,水平互连518可以通过镶嵌工艺或者双重镶嵌工艺被设置。在一些实施例中,水平互连518和垂直互连418可以使用类似的导电材料形成,所述导电材料例如铜、钴、钨、铝、金和银。在一些实施例中,水平互连518的宽度可以大于垂直互连418的宽度,以用于提供水平方向上的电连接,并且还为具有垂直互连418的后续互连结构提供了用于电连接的更大的对准公差。在一些实施例中,可以使用平坦化工艺,使得水平互连518、电介质层510和阻隔层514的顶表面基本上共面。
根据一些实施例,再次参考图1,在操作125中,在电介质层中形成用于第二阶梯层的垂直互连和水平互连。例如,如图6中所示,在第一阶梯层502上形成第二阶梯层504。第二阶梯层504的宽度小于第一阶梯层502的宽度,使得来自第一阶梯层502的一个或多个互连结构被暴露并且接下来被阻隔层610和612覆盖。在一些实施例中,用于电介质层602和604的材料成分和沉积方法可以分别类似于电介质层310和510的材料成分和沉积方法。在一些实施例中,阻隔层610和612的材料成分和沉积方法可以分别类似于阻隔层314和514的材料成分和沉积方法。垂直互连618和水平互连620可以分别设置在电介质层602和604中。
根据一些实施例,再次参考图1,在操作130中,形成额外阶梯层。如图7中所示,随后在第二阶梯层504上形成诸如第三阶梯层506和第四阶梯层508的额外阶梯层。第三阶梯层506可以包括分别形成在电介质层702和714中的垂直互连718和水平互连720。类似地,第四阶梯层508可以包括分别形成在电介质层732和754中的垂直互连758和水平互连760。阻隔层710、712、740和742可以与阻隔层314和514类似,并且这里为了简单起见未对其详细描述。后续阶梯层中的每个具有的宽度小于下面的前一阶梯层,使得来自下面的阶梯层的至少一个或多个互连被暴露并且接下来被阻隔层覆盖。例如,阻隔层710与第二阶梯层504的水平互连620接触。类似地,来自第四阶梯层508的阻隔层740与第三阶梯层504的水平互连720接触。
根据一些实施例,再次参考图1,在操作135中,去除阻隔层。如图8中所示,去除来自所有阶梯层的阻隔层,以暴露未被后续阶梯层覆盖的电介质层和水平互连。具体地,可以去除诸如阻隔层314、514、610、612、710、712、740和742的阻隔层,以暴露形成为靠近每个阶梯层的端部的水平互连。在一些实施例中,并非去除所有的阻隔层。暴露的水平互连以及电介质层的部分可以被统称为阶梯互连结构的“台阶”。例如,第一阶梯层502的通过去除阻隔层而被暴露的部分的顶表面被称为台阶519,如图8中所示。因此,通过形成在阶梯层的端部处的台阶使相邻阶梯层偏移。具体地,一对偏移的相邻阶梯层可以包括第一阶梯层和后续形成的第二阶梯层,该第二阶梯层覆盖第一阶梯层的顶表面的一部分而非全部。例如,第一阶梯层502的台阶519被暴露,并且未被第二阶梯层504的电介质层602覆盖。在一些实施例中,阻隔层可以使用诸如等离子体蚀刻工艺或湿法蚀刻工艺的适当蚀刻工艺被去除。在一些实施例中,阻隔层使用光刻胶材料形成,并且去除工艺可以包括光刻胶剥离或等离子体灰化工艺。
根据一些实施例,再次参考图1,在操作140中,在第二阶梯层504中设置倒装芯片。如图9中所示,可以在封装结构200中设置柱状凸块916、936和956。柱状凸块916可以与第二阶梯层504设置在同一水平级处。照此,柱状凸块916在第一阶梯层502上方,并且电耦合到第一阶梯层502的水平互连518。柱状凸块916可以包括柱状基底918和柱状主体920。在一些实施例中,柱状基底918和柱状主体920可以使用类似的导电材料形成。例如,柱状基底918和柱状主体920可以使用铜形成。在一些实施例中,柱状基底918和柱状主体920可以使用电镀、无电镀、溅射、PVD、任何适当的沉积工艺及其组合形成。在一些实施例中,柱状基底918和柱状主体920可以使用不同的导电材料形成。在一些实施例中,柱状基底918和柱状主体920可以使用任何适当的导电材料形成,所述导电材料例如钨、钴、银、金及其组合。柱状凸块936可以包括与接触焊盘208接触的柱状基底938以及形成在柱状基底938上的柱状主体940。在一些实施例中,柱状基底938和柱状主体940可以使用与柱状基底918和柱状主体920的那些类似的材料和沉积工艺形成,并且这里为了简单起见未对其详细描述。柱状凸块936可以用于为设置在与第二阶梯层504相同的水平级上的倒装芯片提供电连接。在一些实施例中,第二阶梯层504可以是直接连接到接触焊盘208的最低芯片放置级。柱状凸块956可以包括与接触焊盘208接触的柱状基底958以及形成在柱状基底958上的柱状主体960。在一些实施例中,柱状基底958和柱状主体960可以使用与柱状基底918和柱状主体920的那些类似的材料和沉积工艺形成,并且这里为了简单起见未对其详细描述。在一些实施例中,单个柱状主体960可以物理连接和电连接到两个或更多个柱状基底958。柱状主体960可以连接到设置在封装结构200中但是未在图9中示出的芯片的端子。
芯片946可以经由柱状凸块936倒转安装在接触焊盘208上。在一些实施例中,芯片946安装在与第二阶梯层504平齐的水平级处。芯片946可以包括附接至载体950的集成电路948。芯片946可以被倒转并且安装在柱状凸块936上,使得来自集成电路948的端子(图9中未示出)能够与柱状主体940的顶表面接触。这种安装配置可以使电源和信号在柱状凸块936和芯片946之间传输,使得能够通过外部电路控制集成电路948。在一些实施例中,芯片946可以包括各种适当的集成电路,例如包括被布置成CMOS电路、RF电路等的晶体管的控制电路。在一些实施例中,可以将诸如晶体管、二极管、电容器、电阻器、电感器等的有源器件和无源器件设置在芯片946上和/或芯片946内。诸如柱状凸块916、936和956的柱状凸块的引入能够减小对线接合连接的需求,这继而减小了寄生电容和电感。尽管图9示出了一行柱状凸块916、936和956,但是可以设置多行/列的柱状凸块以提供电连接。例如,柱状凸块916、936和956被形成为在x方向上延伸的行。额外的柱状凸块可以被设置为在y方向上延伸的列,并且为了简单起见未在图9中示出。例如,柱状凸块可以形成在参考图2的平面图220示出的多行接触焊盘208a-208d上。将柱状凸块的阵列并入封装结构中能够改善产品良率和性能,以及增加可用I/O连接的数量,这继而能够缓解使用线连接(例如,线接合)来形成高良率的多行/列I/O连接的需求。
根据一些实施例,再次参考图1,在操作145中,在第三阶梯层中设置倒装芯片。如图10中所示,芯片1046可以包括附接至载体1050的集成电路1048。设置在与第三阶梯层506相同的水平级上的芯片1046直接连接到较低阶梯层(例如,第二阶梯层504)。芯片1046可以被倒转并且安装在柱状凸块916上,使得来自集成电路1048的端子(图9中未示出)面朝台阶519并且能够与柱状主体920的顶表面接触。这种安装配置可以使电源和信号在柱状凸块916和芯片1046之间传输,使得能够由外部电路通过第一阶梯层502的水平互连和垂直互连来控制集成电路1048。
芯片1046可以包括各种集成电路,例如,存储电路。例如,芯片1046可以包括三维(3D)存储电路,例如,3D NAND闪速存储芯片。3D NAND闪速存储芯片可以包括闪速存储单元的阵列,所述闪速存储单元的阵列包括布置在衬底之上的栅电极的堆叠层,其中半导体沟道穿过字线进入到衬底中并且与字线相交。为了简单起见,在图10中未示出3D NAND闪速存储芯片的详细结构。详细结构可以包括充当底部/下部选择栅的底部/下部栅电极。顶部/上部栅电极充当顶部/上部选择栅。处于顶部/上部选择栅电极和底部/下部栅电极之间的字线/栅电极充当字线。字线与半导体沟道的相交形成存储单元。顶部/上部选择栅连接到字线以用于行选择,并且底部/下部选择栅连接到位线以用于列选择。3D NAND存储芯片可以包括接触结构的阵列以用于提供从外部连接到字线、选择栅或任何适当的端子的电连接。接触结构可以电耦合到半导体封装的外部连接,从而被闪速存储控制器或***访问。可以在名称为“Memory Device and Forming Method Thereof”的美国专利No.10559592中找到3D NAND闪速存储器件及其形成方法的示例,通过引用将该文献全文并入本文。
根据一些实施例,再次参考图1,在操作150中,将额外的倒装芯片设置在各个阶梯层中。倒装芯片可以包括安装在载体上的集成电路。例如,芯片1146可以包括附接至载体1050的集成电路1048。在一些实施例中,可以在没有载体的情况下设置芯片,例如,包括集成电路的芯片1346。如图11中所示,与芯片1046类似,芯片1146、1246和1168中的每个接下来可以被设置在阶梯层上,并且直接电连接到紧邻在阶梯层下方的另一阶梯层。芯片1146、1246和1168还可以通过水平互连和垂直互连电连接到其他阶梯层。例如,芯片1146可以被倒转并安装在柱状凸块926上,使得来自集成电路1148的端子(图11中未示出)能够面对第二阶梯层504的未被第三阶梯层506覆盖的部分(例如,位于该部分正上方),并且与柱状主体930的顶表面接触。这种安装配置可以使电源和信号在柱状凸块926和芯片1146之间传输,使得能够由外部电路通过第一阶梯层502和第二阶梯层504的水平互连和垂直互连来控制集成电路1148。
模制化合物可以被形成在载体衬底上并且包封堆叠互连结构和所设置的芯片。如图11中所示,模制化合物1180可以被设置为使得阶梯层502-508和芯片946-1346嵌入在模制化合物1180内。在一些实施例中,模制化合物1180可以由树脂化合物、环氧树脂模制化合物、任何适当的模制化合物和/或它们的组合形成。
根据一些实施例,再次参考图1,在操作155中,形成再分布层(RDL)和金属凸块。如图12中所示,封装结构200被倒转,并且RDL 1202和金属凸块1204可以被设置在封装结构200的背面上。金属凸块1204可以被用作I/O触点或者任何适当的电触点。在一些实施例中,载体衬底202可以被RDL 1202代替。例如,可以去除载体衬底202,从而暴露电介质层310、垂直互连418、接触焊盘208和模制化合物1180的表面。之后,可以在前述暴露的表面上形成RDL 1202。RDL 1202可以包括水平和垂直导电线,以用于将形成在第一阶梯层502中的垂直互连扇出至更大的占据空间。在一些实施例中,RDL 1202可以包括一个或多个具有嵌入其中的导电线(为了简单起见未在图12中示出)的电介质层。导电线可以使用任何适当的材料形成,所述材料例如铝、铝合金或其他金属。在一些实施例中,RDL 1202还可以包括熔丝。
金属凸块1204可以设置在RDL 1202上并与之电连接。金属凸块1204可以包括焊料凸块,例如,共晶焊料凸块。替代性地,金属凸块1204可以由铜凸块或者由金、银、镍、钨、铝、其他金属和/或其合金形成的其他金属凸块形成。金属凸块1204还可以包括在半导体互连技术(例如,倒装芯片互连)中使用的可控塌陷芯片连接(C4)凸块。在一些实施例中,金属凸块1204可以从RDL 1202的表面突出,如图12中所示。可以在形成金属凸块1204之前设置焊料掩模(未示出),以防止凸块材料形成在非预期区域中。金属凸块1204可以通过任何数量的适当技术形成,所述技术包括PVD、CVD、电化学沉积(ECD)、分子束外延(MBE)、原子层沉积(ALD)、电镀等。
图13和图14示出了根据一些实施例的并入形成在堆叠芯片的两端上的阶梯互连结构的封装结构1300。图2-14中的相似的附图标记一般表示等同的、功能上类似的、和/或结构上类似的元件。
图13示出了形成RDL和金属凸块之前的封装结构1300。封装结构1300包括第一封装1304和第二封装1306。在一些实施例中,第一封装1304和第二封装1306可以是镜像对称的,如图13中所示。包括芯片946、1046、1146和1246的堆叠芯片与图2-12中的那些类似,并且这里为了简单起见未对其详细描述。与图2-12中描述的阶梯互连结构相对,图13和图14中示出的阶梯互连结构连接到堆叠芯片的两端。例如,如图13中所示,柱状凸块916和926连接到芯片1046和1146的一端,而柱状凸块1316和1326连接到芯片1246和1346的相对端。
图14示出了形成RDL和金属凸块之后的封装结构1300。如图14中所示,RDL 1402可以设置在封装结构1300的背面上,并且金属凸块1404可以设置在RDL 1402上。RDL 1402和金属凸块1404可以与RDL 1202和金属凸块1204类似,并且这里为了简单起见未对其详细描述。
可以在将金属凸块设置在图12和图14中所示的封装结构中之后执行额外工艺。例如,可以通过金属凸块执行面板级测试以确定封装特性,例如制作良率、器件性能等。可以使用切割工艺将相邻封装分开。例如,可以通过沿封装边界205切割而将图12的封装204和206分开。可以通过沿封装边界1305切割而将封装1304和1306分开。
图15和图16示出了根据一些实施例的在形成RDL和金属凸块之前的封装结构1500。图15和图16分别是封装结构1500的截面图和平面图。接触焊盘208形成在衬底的中心区域上并且处于阶梯层1502和1504之间。与图6-14中示出的阶梯层类似,阶梯层1502和1504可以具有在x方向上形成的台阶。此外,阶梯层1504还可以具有通过适当的方法在y方向上形成的台阶,例如,该方法可以是在y方向上堆叠具有递减的长度的芯片,如图16中所示。例如,可以在具有较短长度L2的芯片1160上形成具有长度L1的芯片1346。在一些实施例中,安装具有类似长度的芯片也可以通过以递增偏移量安装后续芯片来在y方向上形成台阶。可以在封装结构1500上形成与图12和图14中描述的那些类似的RDL和金属凸块,并且这里为了简单起见未对其详细讨论。
本公开描述了用于扇出封装中的存储芯片的堆叠阶梯互连结构。堆叠阶梯互连结构能够通过形成在堆叠阶梯互连结构中的每个级上的柱状凸块提供通往堆叠芯片中的每个芯片的电连接,这继而增加了I/O连接点的数量。
在一些实施例中,半导体封装包括再分布层(RDL)和形成在RDL的第一表面上的金属凸块。该半导体封装还包括形成在RDL的第二表面上的阶梯互连结构。该阶梯互连结构包括阶梯层,并且每个阶梯层相对于相邻阶梯层发生偏移。该半导体封装还包括电连接到阶梯互连结构的集成电路(IC)芯片。
在一些实施例中,半导体封装包括再分布层(RDL)和与RDL接触的接触焊盘。半导体封装还包括与多个接触焊盘接触的第一多个柱状凸块。半导体封装还包括与RDL接触的阶梯互连结构。该阶梯互连结构包括具有与RDL接触的第一多个互连的第一阶梯层以及与第一阶梯层相邻的第二阶梯层。第二阶梯层包括接触第一多个互连的第二多个互连。阶梯互连结构还包括与第二阶梯层相邻并且具有第三多个互连的第三阶梯层。半导体封装还包括接触第一多个柱状凸块以及与第一阶梯层接触的第二多个柱状凸块的第一集成电路(IC)芯片。半导体封装还包括与第一IC芯片和第二多个柱状凸块接触的第二IC芯片。
在一些实施例中,用于形成半导体封装的方法包括在载体衬底上形成第一阶梯层。形成第一阶梯层包括:在载体衬底之上沉积第一电介质层以及在第一电介质层中形成第一多个互连。该方法还包括在第一阶梯层上沉积阻隔层。该阻隔层接触第一多个互连中的至少一个互连的顶表面。该方法还包括在第一阶梯层上形成第二阶梯层。第二阶梯层接触阻隔层。该方法还包括去除阻隔层并且暴露至少一个互连的顶表面。该方法还包括在至少一个互连的暴露的顶表面上形成柱状凸块。该方法还包括在柱状凸块上安装集成电路(IC)芯片。
特定实施例的前述描述将因此揭示本公开的一般性质,以使得其他人在不脱离本公开的一般概念的情况下,可以通过应用本领域技术内的知识来容易地修改和/或适应于诸如特定实施例的各种应用,而无需过度实验。因此,基于本文提出的教导和指导,这样的改编和修改旨在落在所公开的实施例的等同物的含义和范围内。应当理解,本文中的措词或术语是出于描述而非限制性的目的,使得本说明书的术语或措辞将由技术人员鉴于教导和指导来解释。
上面已经借助于示出特定功能及其关系的实施方式的功能构建块描述了本公开的实施例。为了方便描述,本文已经任意定义了这些功能构建块的边界。只要适当地执行特定功能及其关系,就可以定义交替的边界。
发明内容部分和摘要部分可以阐述(一个或多个)发明人所设想的本公开的一个或多个但不是全部示例性实施例,并且因此,不旨在以任何方式限制本公开和所附权利要求。
本公开的广度和范围不应当由任何上述示例性实施例限制,而应当仅根据所附权利要求及其等同物来定义。
Claims (26)
1.一种半导体封装,包括:
再分布层(RDL),所述再分布层(RDL)包括与多个输入/输出(I/O)触点接触的第一表面以及与所述第一表面相对的第二表面;
阶梯互连结构,所述阶梯互连结构形成在所述RDL的所述第二表面上,并且与所述RDL电连接,其中:
所述阶梯互连结构包括多个阶梯层,其中,所述多个阶梯层包括第一阶梯层和堆叠在所述第一阶梯层的顶表面上的第二阶梯层;并且
所述第二阶梯层覆盖所述第一阶梯层的所述顶表面的一部分,使得所述第一阶梯层的所述顶表面的剩余部分被暴露;以及
多个集成电路(IC)芯片,所述多个集成电路(IC)芯片经由所述阶梯互连结构电连接到所述RDL,其中,所述多个IC芯片中的第一IC芯片通过所述第一阶梯层的所述顶表面的所述剩余部分电连接到所述RDL。
2.根据权利要求1所述的半导体封装,其中,所述多个阶梯层还包括堆叠在所述第二阶梯层的顶表面上的第三阶梯层,并且其中,所述第三阶梯层覆盖所述第二阶梯层的所述顶表面的一部分,使得所述第二阶梯层的所述顶表面的剩余部分被暴露。
3.根据权利要求2所述的半导体封装,其中:
所述第二阶梯层的宽度小于所述第一阶梯层的宽度;并且
所述第三阶梯层的宽度小于所述第二阶梯层的所述宽度。
4.根据权利要求2所述的半导体封装,其中,所述多个IC芯片还包括通过所述第二阶梯层的所述顶表面的所述剩余部分电连接到所述RDL的第二IC芯片。
5.根据权利要求4所述的半导体封装,其中,所述第二IC芯片相对于所述第一IC芯片发生偏移,使得所述第二IC芯片的一个或多个端子在所述第二阶梯层的所述顶表面的所述剩余部分的正上方。
6.根据权利要求4所述的半导体封装,其中,所述第一IC芯片通过一个或多个柱状凸块电连接到所述第一阶梯层。
7.根据权利要求6所述的半导体封装,其中,所述一个或多个柱状凸块与所述第二阶梯层设置在同一水平级处。
8.根据权利要求4所述的半导体封装,其中,所述多个IC芯片还包括倒转安装在一个或多个柱状凸块上的第三IC芯片。
9.根据权利要求8所述的半导体封装,其中,所述一个或多个柱状凸块和所述第一IC芯片与所述第三阶梯层设置在同一水平级处。
10.根据权利要求8所述的半导体封装,其中,所述第三IC芯片通过所述一个或多个柱状凸块电连接到所述第二阶梯层的所述顶表面的暴露部分。
11.根据权利要求4所述的半导体封装,其中,所述第一IC芯片和所述第二IC芯片包括NAND闪速存储芯片。
12.根据权利要求1所述的半导体封装,还包括:
多个接触焊盘,所述多个接触焊盘设置在所述RDL的所述第二表面上;
第二IC芯片,所述第二IC芯片倒转安装在所述接触焊盘上。
13.根据权利要求12所述的半导体封装,其中,所述第一IC芯片相对于所述第二IC芯片发生偏移,使得所述第一IC芯片的一个或多个端子处于所述第一阶梯层的所述顶表面的所述剩余部分的正上方。
14.根据权利要求1所述的半导体封装,其中,所述多个IC芯片通过所述阶梯互连结构倒转安装在所述RDL上。
15.根据权利要求1所述的半导体封装,其中,所述第一阶梯层包括第一多个垂直互连和第一多个水平互连,并且其中,所述第一多个垂直互连包括与所述RDL接触的第一端部以及与所述第一多个水平互连接触的第二端部。
16.根据权利要求15所述的半导体封装,其中,所述第二阶梯层包括第二多个垂直互连和第二多个水平互连,并且其中,所述第二多个垂直互连与所述第一多个水平互连接触。
17.根据权利要求1所述的半导体封装,还包括包封所述阶梯互连结构和所述多个IC芯片的模制化合物。
18.根据权利要求1所述的半导体封装,其中,所述多个I/O触点包括多个金属凸块。
19.一种用于形成半导体封装结构的方法,所述方法包括:
提供载体衬底;
在所述载体衬底上形成阶梯互连结构,包括:
形成第一阶梯层,以及
在所述第一阶梯层的顶表面上形成第二阶梯层,其中,所述第二阶梯层覆盖所述第一阶梯层的所述顶表面的一部分,使得所述第一阶梯层的所述顶表面的剩余部分被暴露;
将多个集成电路(IC)芯片倒转安装在所述载体衬底之上和所述阶梯互连结构上,包括:将所述多个IC芯片中的第一IC芯片通过所述第一阶梯层的所述顶表面的所述剩余部分电连接到所述第一阶梯层;以及
采用再分布层(RDL)代替所述载体衬底;
将所述多个IC芯片通过所述阶梯互连结构电连接到所述RDL,包括将所述第一IC芯片通过所述第一阶梯层的所述顶表面的所述剩余部分电连接到所述RDL。
20.根据权利要求19所述的方法,还包括:
将第三阶梯层堆叠在所述第二阶梯层的顶表面上,并且其中,所述第三阶梯层覆盖所述第二阶梯层的所述顶表面的一部分,使得所述第二阶梯层的所述顶表面的剩余部分被暴露;
在所述第二阶梯层的所述顶表面的所述剩余部分上形成一个或多个柱状凸块;以及
将所述多个IC芯片中的第二IC芯片倒转安装在所述一个或多个柱状凸块上。
21.根据权利要求19所述的方法,其中,形成第一阶梯层包括:将第一电介质层沉积在所述载体衬底上;以及在所述第一电介质层中形成多个垂直互连。
22.根据权利要求21所述的方法,其中,形成所述第一阶梯层还包括:将第二电介质层沉积在所述第一电介质层上;以及在所述第二电介质层中形成多个水平互连。
23.根据权利要求22所述的方法,其中,形成多个水平互连包括:
在所述第二电介质层中形成多个开口,其中,所述多个开口中的至少一个开口暴露所述多个垂直互连中的至少一个垂直互连;以及
在所述多个开口中沉积导电材料。
24.根据权利要求19所述的方法,还包括在所述载体衬底上沉积两行或更多行接触焊盘。
25.根据权利要求24所述的方法,还包括将所述多个IC芯片中的第二IC芯片倒转安装在所述两行或更多行接触焊盘上。
26.根据权利要求25所述的方法,其中,倒转安装所述多个IC芯片包括将所述第一IC芯片倒转安装在所述第二IC芯片上。
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