CN112951844A - Standard unit library of FDSOI device - Google Patents
Standard unit library of FDSOI device Download PDFInfo
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- CN112951844A CN112951844A CN202110076200.5A CN202110076200A CN112951844A CN 112951844 A CN112951844 A CN 112951844A CN 202110076200 A CN202110076200 A CN 202110076200A CN 112951844 A CN112951844 A CN 112951844A
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- 238000000034 method Methods 0.000 claims description 19
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 description 11
- 239000000758 substrate Substances 0.000 description 10
- 239000002184 metal Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000012212 insulator Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention relates to a standard cell library of an FDSOI device, which comprises more than one standard cell and is characterized in that: the heights of the standard units are the same, the standard units are composed of FDSOI devices, the FDSOI devices comprise back gates, and the operation speed and the leakage current of each standard unit are adjusted by using the voltage of the back gates of the FDSOI devices. Applying forward bias and reverse voltage to the back gate can adjust the speed and leakage current of the device, for example, applying forward bias, the speed of the cell bank can be increased, or applying reverse voltage leakage can be decreased. Therefore, in chip design, different speeds and leakage currents can be adjusted by using the cell library with the same height.
Description
Technical Field
The invention relates to the field of semiconductor device preparation, in particular to a standard cell library of an FDSOI device.
Background
As the feature size of core MOS devices in integrated circuits continues to shrink, the conventional planar bulk silicon devices have reached physical limits due to short channel effects. The development and design of the current Standard Cell Library (Standard Cell Library) is mainly focused on the planar Bulk Silicon (Bulk Silicon) process followed by the fin field effect transistor (FinFET) process.
Fully depleted Silicon-On-Insulator (FDSOI) devices are an alternative to bulk Silicon MOS devices after CMOS processes enter the 28nm node. The FDSOI device has small leakage current and can be used in the field with higher requirements on chip power consumption. In addition, compared with the FinFET process, the FDSOI process needs a small number of photoetching plates and is low in process cost.
The selection of the standard cell library is very important, and the selection of a set of suitable libraries is very important for timing convergence and physical convergence of the chip, and the PPA (performance Power area) of the final chip. The height of the cell library is distinguished by the track, such as 7T, 9T, 12T, which means that the height of the standard cell in these libraries is 7 tracks, 9 tracks, 12 tracks. In general, the higher the height, the larger the occupied area, the faster the supply speed, and the higher the power consumption; conversely, the lower the height, the smaller the footprint, the slower the speed of delivery, but the lower the leakage current, and the lower the power consumption. Meanwhile, by changing the thickness of the device gate metal layer, the doping concentration and the like, the standard cell library can be divided into Low Vt (LVT): the speed is fastest, but the electric leakage is maximum; regular Vt (RVT) velocity is centered on leakage; high Vt (VT): the speed is slowest but the leakage is minimal. Therefore, when designing the cell library, in addition to the size of tack, the threshold voltage needs to be considered.
In order to meet the running speed of a device and the requirement on leakage current, a standard cell library provided by a traditional bulk silicon process adopts a plurality of standard cells with different threshold voltages to realize the balance of the running performance and the power consumption of a circuit, namely, the standard cells with different heights are adopted in one standard cell library, thereby invisibly improving the process difficulty and the preparation cost.
Disclosure of Invention
In order to solve the technical problems, the invention provides a standard cell library of an FDSOI device, which can reduce electric leakage and power consumption under the condition of unchanging the speed of the standard cell library with higher height. The invention specifically adopts the following technical scheme:
a standard cell library for FDSOI devices comprising more than one standard cell, characterized in that: the heights of the standard units are the same, the standard units are composed of FDSOI devices, and the FDSOI devices comprise back gates, and voltages are applied to the back gates to adjust the operation speed and the leakage current of the standard units.
Compared with the prior art, the invention has the following beneficial technical effects: the FDSOI technology has the characteristic Back Bias process (Back Bias), so that the influence on the formation of a transistor channel can be realized by adjusting the Back Bias, the electric leakage and the power consumption can be reduced under the condition of unchanging the speed of a standard cell library with higher height, and compared with the traditional bulk silicon process, the FDSOI technology has the advantages of achieving the requirements of small area, high speed and small power consumption increase. In one embodiment, the height of each standard cell in a 28 nanometer process is 9T.
The present invention utilizes RBB and FBB to adjust the speed and leakage current of a device for a fixed track cell bank (these cell banks include long channel and short channel) because the threshold voltage of the device is changed, such as Forward Body Bias (FBB) is applied, the speed of the cell bank can be increased, or Reverse Body Bias (RBB) is applied, the leakage current can be decreased. Therefore, in chip design, different speeds and leakage currents can be adjusted by using the same track cell library, and in the prior art, different track cell libraries are required to realize different speeds and leakage currents.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings.
Fig. 1 is a cross-sectional view of an FDSOI device according to the present invention.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It is to be understood that such description is merely illustrative and not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.
Various structural schematics according to embodiments of the present invention are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present invention, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
Fig. 1 is a schematic cross-sectional view of an FDSOI device. A substrate is provided, and the wafer is an SOI type substrate. An N-well region (N-well) and a P-well region (P-well) are formed in a semiconductor substrate 101, the semiconductor substrate 101 may be made of silicon (silicon) or other semiconductor material, and the semiconductor substrate 101 is a P or N type substrate. The N-type well region may be formed by implanting ions into the semiconductor substrate 101, for example, implanting phosphorus, which is an N-type impurity. A P-well region (P-well) is formed in the semiconductor substrate 101, and may be formed by implanting ions into the semiconductor substrate 101, for example, implanting boron, which is a P-type impurity, to form the P-well region.
Fully depleted silicon-on-insulator (FDSOI) transistor 100 is formed over N-type well region 102 and P-type well region 103. A Buried Oxide (BOX) layer 104 is formed over the N-type well region 102 and the P-type well region 103, and the BOX layer 104 may be formed together with the semiconductor substrate 101. In some embodiments, the Buried Oxide (BOX) layer 104 may be formed of SiO2, SiNX, or a combination thereof. Two P-type doped regions 105 are formed over BOX layer 104 and two N-type doped regions 106 are formed over BOX layer 104, P-type doped regions 105 having the same depth as N-type doped regions 106. A silicon-on-insulator (SOI) layer is formed over BOX layer 104 and between P-type doped regions 105 and N-type doped regions 106, respectively. Metal gates (metal gates) 107 are respectively formed over the SOI layer. The P-type doped regions 105 form the drain and source regions, respectively, of the P-type FDSOI transistor 100, and the N-type doped regions 106 form the drain and source regions, respectively, of the N-type FDSOI transistor 100. The channel of the FDSOI transistor 100 is formed between two P-doped regions 105, between two N-doped regions 106 and under a metal gate 107, over the BOX layer 105. Thus, the preparation of the FDSOI device is completed.
Next, the Buried Oxide (BOX) layer 104 is etched through by an etching process, and a contact wiring 108 for back gate bias, which electrically connects the P-type well region 102 and the N-type well region 103, is led out. To this end, the contact line 108 may be used to back bias the FDSOI transistor.
The greater the forward backpressure (FBB) applied to the FDSOI transistor, the greater the drive capability, the faster the speed; the greater the reverse back pressure (RBB) is applied, the smaller the drive capability and the slower the speed, but the smaller the power consumption and the leakage current. Therefore, the back gate bias voltage can be adjusted according to the requirements on the operation speed and the leakage current of the FDSOI.
The standard cell library is a collection of cells (cells), and in one embodiment, each cell is composed of more than 2 FDSOI transistors, which can perform different logic operations. Several basic cells, such as NOT gate, 2 transistors; NAND gate: 4 transistors; NOR gate: 4 transistors; AND gate: 6 transistors; OR gate: 6 transistors. Therefore, the FDSOI transistor has high operation speed, the unit has high operation speed, the standard unit transistor has small leakage current, and the unit has small leakage current.
In semiconductor fabrication, at least three different speed and leakage devices (devices) are provided. The three different devices are achieved by 3 different manufacturing processes, including changing the thickness of the gate metal layer, the doping concentration, etc. For example, the thicker the gate metal layer, the higher the threshold voltage (Vt) of the transistor, the slower the speed, and the less leakage. Conversely, the thinner the gate metal layer, the lower the threshold voltage (Vt) of the transistor, the faster the speed, and the more current leakage. Therefore, semiconductor devices are classified into three categories according to different threshold voltages:
low Vt (LVT): fastest speed but maximum leakage
Regular Vt (RVT) centering velocity and leakage
High Vtol (HVT): the speed is slowest but the leakage is minimal.
In one embodiment, the standard cell library of 9-track is designed by adopting RVT, and the requirement on the driving capability of 12-track can be met by adjusting the bias voltage of a back gate, for example, the larger the applied forward back pressure (FBB) is, so as to meet the requirement on the speed of the standard cell library; and applying reverse back pressure (RBB) to meet the requirements of 7-track on power consumption and leakage current. Therefore, in chip design, different speeds and leakage currents can be adjusted by using the same track cell library, and in the prior art, different track cell libraries are required to meet the requirements of different speeds and leakage currents, which increases the difficulty and cost of the process in an intangible way.
Therefore, the standard cell library of the 9-track FDSOI device designed by RVT can be replaced by the standard cell library of 7-track or the standard cell library of 12-track through adjustment of back pressure, and the standard cell library of 7-track or the standard cell library of 12-track does not need to be additionally developed, so that the development and generation cost is reduced.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.
Claims (7)
1. A standard cell library for FDSOI devices comprising more than one standard cell, characterized in that: the heights of the standard units are the same, the standard units are composed of FDSOI devices, and the FDSOI devices comprise back gates, and the back gates are used for applying voltage to adjust the threshold voltage of the FDSOI devices so as to adjust the operation speed and the leakage current of the standard units.
2. The standard cell library of claim 1, wherein: the height of each standard unit is the standard moderate height in each nanometer size process.
3. The standard cell library of claim 1, wherein: each standard cell consists of more than 2 FDSOI transistors.
4. The standard cell library of claim 1, wherein: the threshold voltage of the FDSOI device is RVT.
5. The standard cell library of claim 1, wherein: the applied voltage includes a forward bias and a reverse bias.
6. A method for improving the operation speed of a standard cell library is characterized in that: the standard cell library comprises more than one standard cell, the height of each standard cell is the same, each standard cell is composed of an FDSOI device, each FDSOI device comprises a back gate, forward back pressure is applied to the back gate, the threshold voltage of the standard cell is reduced, and the operation speed is improved.
7. A method for reducing standard cell library leakage current, comprising: the standard cell library comprises more than one standard cell, the height of each standard cell is the same, each standard cell is composed of an FDSOI device, each FDSOI device comprises a back gate, reverse bias voltage is applied to the back gate, the threshold voltage of the standard cell is increased, and leakage current is reduced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110076200.5A CN112951844A (en) | 2021-01-20 | 2021-01-20 | Standard unit library of FDSOI device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110076200.5A CN112951844A (en) | 2021-01-20 | 2021-01-20 | Standard unit library of FDSOI device |
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| CN112951844A true CN112951844A (en) | 2021-06-11 |
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| CN202110076200.5A Pending CN112951844A (en) | 2021-01-20 | 2021-01-20 | Standard unit library of FDSOI device |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140176216A1 (en) * | 2012-12-26 | 2014-06-26 | Commissariat à I'énergie atomique et aux énergies alternatives | Integrated circuit comprising a clock tree cell |
| US20170104005A1 (en) * | 2015-09-21 | 2017-04-13 | Globalfoundries Inc. | Contacting soi substrates |
| US20190147948A1 (en) * | 2017-11-13 | 2019-05-16 | International Business Machines Corporation | Enhanced fdsoi physically unclonable function |
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2021
- 2021-01-20 CN CN202110076200.5A patent/CN112951844A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140176216A1 (en) * | 2012-12-26 | 2014-06-26 | Commissariat à I'énergie atomique et aux énergies alternatives | Integrated circuit comprising a clock tree cell |
| US20170104005A1 (en) * | 2015-09-21 | 2017-04-13 | Globalfoundries Inc. | Contacting soi substrates |
| US20190147948A1 (en) * | 2017-11-13 | 2019-05-16 | International Business Machines Corporation | Enhanced fdsoi physically unclonable function |
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Effective date of registration: 20220810 Address after: 510535 building a, 136 Kaiyuan Avenue, Guangzhou Development Zone, Guangzhou City, Guangdong Province Applicant after: Guangdong Dawan District integrated circuit and System Application Research Institute Applicant after: Ruili flat core Microelectronics (Guangzhou) Co.,Ltd. Address before: 510535 building a, 136 Kaiyuan Avenue, Guangzhou Development Zone, Guangzhou City, Guangdong Province Applicant before: Guangdong Dawan District integrated circuit and System Application Research Institute Applicant before: AoXin integrated circuit technology (Guangdong) Co.,Ltd. |