CN112948312B - Chip control method and device, intelligent terminal and computer readable storage medium - Google Patents
Chip control method and device, intelligent terminal and computer readable storage medium Download PDFInfo
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
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- G06F9/4418—Suspend and resume; Hibernate and awake
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Abstract
The invention discloses a chip control method, a chip control device, an intelligent terminal and a computer readable storage medium, wherein the chip control method comprises the following steps: acquiring an I2C device address; when the I2C device address matches the local address, acquiring a target operation based on the I2C device address, wherein the target operation is a read operation or a write operation; when the target operation is a write operation, acquiring target data; and when the target data meet a preset target condition, performing awakening control on the chip. Compared with the prior art, the scheme of the invention further obtains the target operation when the I2C equipment address is matched with the local address, obtains the target data when the target operation is write operation, and performs awakening control on the chip only when the target data meets the preset target condition. The chip clock protection circuit is favorable for avoiding the internal clock and the power supply of the chip from being turned on due to data communication or interference which is irrelevant to the chip on the I2C bus, and reduces the power consumption of the chip.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a chip control method and apparatus, an intelligent terminal, and a computer-readable storage medium.
Background
With the rapid development of science and technology, the performance of electronic products is stronger and stronger, and the power consumption is increased. In order to reduce power consumption as much as possible, it is necessary in some cases to put the chip into a low power consumption mode. For example, when no transaction needs to be processed, a low power consumption chip as an I2C slave needs to enter a low power consumption mode in order to reduce power consumption, and at this time, a power supply and a clock inside the chip are in an off state. When the chip needs to process the transaction, the corresponding chip needs to be controlled and awakened, so that the chip exits the low power consumption mode and works normally.
In the prior art, after the chip enters the low power consumption mode, part of circuits in the chip are awakened when an I2C start flag is detected, an I2C working clock is turned on and the power supply inside the chip is restored, meanwhile, an I2C address packet is continuously received, the chip is awakened completely when the addresses are matched, and otherwise, the low power consumption mode is re-entered. The problem with the prior art is that any data communication or interference on the I2C bus may cause the internal clock and power of the chip to be turned on for a while, resulting in increased power consumption.
Thus, there is still a need for improvement and development of the prior art.
Disclosure of Invention
The invention mainly aims to provide a chip control method, a chip control device, an intelligent terminal and a computer readable storage medium, and aims to solve the problem that in the prior art, when an I2C start mark is detected, a part of circuits in a chip are waken up, an I2C working clock is turned on and power supply inside the chip is recovered, and when any data communication or interference exists on an I2C bus, the internal clock and the power supply of the chip can be turned on and continue for a period of time, so that the power consumption of the chip is not reduced.
In order to achieve the above object, a first aspect of the present invention provides a chip control method, where the method includes:
acquiring an I2C device address;
when the I2C device address matches the local address, acquiring a target operation based on the I2C device address, wherein the target operation is a read operation or a write operation;
when the target operation is a write operation, acquiring target data;
and when the target data meet a preset target condition, performing awakening control on the chip.
Optionally, when the I2C device address matches the local address, the obtaining a target operation based on the I2C device address includes:
when the I2C device address matches the local address, obtaining the lowest bit value of the I2C device address;
and acquiring the target operation based on the value of the lowest bit.
Optionally, after obtaining the target operation based on the I2C device address, the method further includes:
and when the target operation is a read operation, performing awakening control on the chip.
Optionally, after obtaining the I2C device address, the method further includes:
when the I2C device address does not match the local address, the I2C bus is released to enter the idle state.
Optionally, the target data includes a device address, a register address, or an operation command.
Optionally, when the target data meets a preset target condition, performing wakeup control on the chip includes:
and when the value of the target data is equal to a preset target value or the number of the target data is greater than a preset target number, performing awakening control on the chip.
Optionally, the waking up the chip includes:
controlling a power management unit of the chip to recover power supply to a core power domain of the chip;
starting a clock management unit of the chip, and controlling the clock unit to recover a clock required by the chip;
and awakening the central processing unit of the chip.
Optionally, after obtaining the I2C device address, the method further includes:
when the I2C device address does not match the local address, the I2C bus is released to enter the idle state.
A second aspect of the present invention provides a chip control apparatus, wherein the apparatus includes:
the address acquisition module is used for acquiring an I2C device address;
a target operation obtaining module, configured to obtain a target operation based on the I2C device address when the I2C device address matches a native address, where the target operation is a read operation or a write operation;
the target data acquisition module is used for acquiring target data when the target operation is write operation;
and the control module is used for performing awakening control on the chip when the target data meets a preset target condition.
A third aspect of the present invention provides an intelligent terminal, where the intelligent terminal includes a memory, a processor, and a chip control program stored in the memory and executable on the processor, and the chip control program implements any one of the steps of the chip control method when executed by the processor.
A fourth aspect of the present invention provides a computer-readable storage medium, in which a chip control program is stored, and the chip control program, when executed by a processor, implements any one of the steps of the chip control method.
Therefore, in the scheme of the invention, the I2C equipment address is obtained; when the I2C device address matches the local address, acquiring a target operation based on the I2C device address, wherein the target operation is a read operation or a write operation; when the target operation is a write operation, acquiring target data; and when the target data meet a preset target condition, performing awakening control on the chip. Compared with the prior art, the scheme of the invention further obtains the target operation when the I2C equipment address is matched with the local address, obtains the target data when the target operation is write operation, and performs awakening control on the chip only when the target data meets the preset target condition. The chip clock protection circuit is favorable for avoiding the internal clock and the power supply of the chip from being turned on due to data communication or interference which is irrelevant to the chip on the I2C bus, and reduces the power consumption of the chip.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic diagram of a working state of an SOC when waking up the SOC according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a working state of an SOC when the SOC is awakened in another prior art according to an embodiment of the present invention;
fig. 3 is a schematic flowchart of a chip control method according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating the step S200 in FIG. 3 according to an embodiment of the present invention;
FIG. 5 is a flow chart of another chip control method according to an embodiment of the present invention;
FIG. 6 is a block diagram of an SOC according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a chip control flow provided in an embodiment of the present invention;
fig. 8 is a schematic diagram of a working state when the SOC wakes up according to an embodiment of the present invention;
fig. 9 is a schematic diagram of an operating state of an SOC during sleep according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of multi-machine communication in a very low power consumption mode according to an embodiment of the present invention;
fig. 11 is a schematic state diagram of SOC wake-up in a low power consumption mode according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of a chip control device according to an embodiment of the present invention;
fig. 13 is a schematic block diagram of an internal structure of an intelligent terminal according to an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when …" or "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted depending on the context to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings of the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
With the rapid development of science and technology, the performance of electronic products is stronger and stronger, and the power consumption is increased. In order to reduce power consumption as much as possible, it is necessary in some cases to put the chip into a low power consumption mode. The Chip may be a System On Chip (SOC). For example, when no transaction needs to be processed, a low power consumption chip as an I2C slave needs to enter a low power consumption or ultra low power consumption mode to reduce power consumption, and at this time, a power supply and a clock inside the chip are in an off state. When the chip needs to process the transaction, the corresponding chip needs to be controlled and awakened, so that the chip exits the low power consumption mode and works normally. In low power portable device or sensor applications, the I2C protocol is a widely used protocol. When the chip is in a low power consumption mode, the chip can be woken up on the I2C bus by detecting the level jump, but the wakeup time delay is low, the efficiency is low, and the communication of other I2C devices on the bus is influenced.
In the prior art, after the SOC enters the low power consumption mode, part of circuits in the SOC are usually waken up when an I2C start flag is detected, an I2C working clock is turned on and the internal power supply of the SOC is recovered, meanwhile, an I2C address packet is continuously received, the chip is fully waken up when the addresses are matched, otherwise, the low power consumption mode is re-entered. Fig. 1 is a schematic diagram of an operating state of a SOC during waking up the SOC according to an embodiment of the present invention, as shown in fig. 1, which is problematic in that any data communication or interference on an I2C bus may cause an internal clock and a power supply of the SOC to be turned on for a while, so that power consumption increases. Moreover, the I2C bus is frequently pulled due to the time required to start the clock and power supply, which reduces the data transmission efficiency.
Another scheme in the prior art is to add an address detection circuit, and only when the addresses match, a wake-up signal is initiated to recover the internal power supply and clock of the SOC, so as to achieve the purpose of wake-up. However, this scheme has a problem in that, after the address is matched, since it takes a long time to recover the power and turn on the clock, the I2C bus is forcibly pulled during this time, so that the data transfer efficiency is lowered and the power consumption is increased. Particularly, in the derived protocols PMBUS and SMBUS of I2C, due to the existence of a large number of broadcast frames, each time broadcast is initiated, a device in a dormant state must wake up to determine whether to respond, which increases power consumption and reduces communication efficiency. Fig. 2 is a schematic diagram of an operating state of the SOC when waking up the SOC in the solution provided in the embodiment of the present invention, as shown in fig. 2, the host does not initiate access to the current SOC, but the SOC wakes up and operates continuously.
In order to solve the problems in the prior art, the present invention provides a chip control method, in an embodiment of the present invention, an I2C device address is obtained; when the I2C device address matches the local address, acquiring a target operation based on the I2C device address, wherein the target operation is a read operation or a write operation; when the target operation is a write operation, acquiring target data; and when the target data meet a preset target condition, performing awakening control on the chip. Compared with the prior art, the scheme of the invention further obtains the target operation when the I2C equipment address is matched with the local address, obtains the target data when the target operation is write operation, and performs awakening control on the chip only when the target data meets the preset target condition. The chip clock protection circuit is favorable for avoiding the internal clock and the power supply of the chip from being turned on due to data communication or interference which is irrelevant to the chip on the I2C bus, and reduces the power consumption of the chip.
Exemplary method
As shown in fig. 3, an embodiment of the present invention provides a chip control method, specifically, the method includes the following steps:
in step S100, the I2C device address is acquired.
The I2C device address is an I2C address transmitted through an I2C bus. Specifically, the I2C start bit is received, and when the I2C host is detected to issue the I2C start timing, the corresponding I2C address is obtained through the I2C bus. If it is an abnormal state or disturbance, the address is not received. The abnormal state may be that the upper computer (I2C host) sends an error data packet, and the interference may be a glitch or pulse caused by external electromagnetic interference. Furthermore, all signals which do not conform to the frame format of the correct I2C protocol are filtered out, so as to reduce the influence of interference. The I2C host refers to a host specified in the I2C protocol, and may be a main control chip in the system or an upper PC, which is not specifically limited herein.
Step S200, when the I2C device address matches the local address, obtaining a target operation based on the I2C device address, wherein the target operation is a read operation or a write operation.
The local address is an address corresponding to the chip, and optionally, may be an address corresponding to the SOC in the low power consumption mode. Specifically, the received I2C device address is compared with the local address corresponding to the chip, and whether the received I2C device address matches the local address is determined. When the I2C device address matches the native address, a subsequent target operation is obtained based on the received I2C device address.
In step S300, when the target operation is a write operation, target data is acquired.
When the target operation is a write operation, target data continues to be received. The target data is data continuously transmitted through the I2C bus, and the target data may reflect operations specifically required to be executed by the slave chip, so that whether the corresponding slave chip needs to be woken up may be determined according to the target data. The target data immediately follows the I2C device address, so that the acquisition of the target data can continue after the acquisition of the I2C device address is received.
And step S400, when the target data meet a preset target condition, performing awakening control on the chip.
The preset target condition is a preset condition for judging whether the target data meets the requirement of awakening the current chip. For example, the target condition may be preset such that the number of target data reaches a preset number, and the corresponding chip is awakened after receiving the preset number of target data. The method can effectively control when the chip enters the awakening process, avoid the turning on of an internal clock and a power supply of the chip caused by data communication or interference which is irrelevant to the chip on an I2C bus, and reduce the power consumption of the chip. Meanwhile, the efficiency of waking up a chip (SOC) through an I2C bus is effectively improved, the influence of the chip wake-up process on the I2C bus is reduced, and the bus communication efficiency is improved.
As can be seen from the above, the chip control method provided in the embodiment of the present invention obtains the I2C device address; when the I2C device address matches the local address, acquiring a target operation based on the I2C device address, wherein the target operation is a read operation or a write operation; when the target operation is a write operation, acquiring target data; and when the target data meet a preset target condition, performing awakening control on the chip. Compared with the prior art, the scheme of the invention further obtains the target operation when the I2C equipment address is matched with the local address, obtains the target data when the target operation is write operation, and performs awakening control on the chip only when the target data meets the preset target condition. The chip clock protection circuit is favorable for avoiding the internal clock and the power supply of the chip from being turned on due to data communication or interference which is irrelevant to the chip on the I2C bus, and reduces the power consumption of the chip.
The chip control method is used for controlling the working state of a chip which is a slave on an I2C bus, and controlling the slave chip to enter a wake-up state or keep a low power consumption state.
Specifically, in this embodiment, as shown in fig. 4, the step S200 includes:
in step S201, when the I2C device address matches the local address, the lowest bit value of the I2C device address is obtained.
In step S202, a target operation is acquired based on the value of the lowest order bit.
Specifically, in the present embodiment, in the I2C bus protocol, it may be determined whether a subsequent target operation issued by the host is a read operation or a write operation based on whether the lowest order bit value of the I2C device address is 0 or 1, so as to further determine the subsequent operation based on the target operation.
Optionally, in this embodiment, as shown in fig. 5, after the step S200, the method further includes: step S500, when the target operation is a read operation, performing wakeup control on the chip.
In particular, since the I2C protocol is the underlying protocol, in most cases, the next data on the I2C bus after receiving an address will be defined as an application-level address. For example, in the EEPROM, the first data is a page address, and in the SMBUS/PMBUS protocol, the I2C device address is actually a broadcast address, and the first data is a real device address. Thus, if the subsequent target operation is a write operation, the first data is the address to be accessed (at which time the chip does not have to be woken up) and then the data (at which time it does not have to be woken up). If the subsequent target operation is a read operation, the first data is real data, and then the chip has to be awakened.
Specifically, when the target operation is a write operation, the target data is continuously received and acquired. Optionally, the target data includes a device address, a register address, or an operation command.
The target data usually follows the I2C device address, and may be a device address, a low memory address or an operation command, and may include other types of data, which is determined by the actual application protocol, and is not limited herein.
After receiving the target data, it may be determined whether the target data meets a preset target condition. Optionally, the step S400 includes: and when the value of the target data is equal to a preset target value or the number of the target data is greater than a preset target number, performing awakening control on the chip.
The preset target condition is a preset condition for judging whether the target data, i.e. the corresponding target operation, points to the chip, and may be preset, or may be set and adjusted according to actual requirements, which is not specifically limited herein. In this embodiment, the target condition may be that a value of the target data is equal to a preset target value, or that the number of the received target data is greater than a preset target number. The specific target condition may also be set according to the type of the target data. For example, when the target data is a device address or a register address, the target condition may be set to be that the device address or the register address in the target data is specifically the same as a preset certain address (SOC address); when the target data is an operation command, the target condition may be set correspondingly such that the number of the received operation commands is greater than a preset target number.
Optionally, when the target data does not meet the preset target condition, the I2C bus may be released to enter an idle state, or the target data may continue to be received, which may be determined specifically according to an actually set target condition, and is not specifically limited herein. For example, when the target condition is that the value of the target data is equal to a preset target value, in the case that the target data does not satisfy the preset target condition, the I2C bus may be released to enter an idle state; when the target condition is that the number of the target data is larger than the preset target number, the receiving of the target data can be returned to continue under the condition that the target data does not meet the preset target condition.
Optionally, the waking up the chip includes: controlling a power management unit of the chip to recover power supply to a core power domain of the chip; starting a clock management unit of the chip, and controlling the clock unit to recover a clock required by the chip; and awakening the central processing unit of the chip.
Specifically, a wake-up operation is initiated, a wake-up signal is sent to notify a power management unit of the SOC, and a wake-up process is entered. The control power management unit resumes power to an SOC core power domain including an I2C core unit, a clock management unit, and a CPU, and starts a clock management unit. The clock management unit recovers clocks required for providing the SOC, including clocks required for the CPU and clocks required for the I2C core unit. And the CPU wakes up to control the I2C core unit, takes over the I2C input/output control unit and continues to transmit data.
Optionally, after step S100, the method further includes: when the I2C device address does not match the local address, the I2C bus is released to enter the idle state.
Specifically, if the I2C device address does not match the local address, it indicates that the local device does not need to process the transaction, so the I2C bus can be released to enter an idle state, and the bus is prevented from being frequently pulled and affecting the communication of other devices on the bus, thereby improving the bus communication efficiency. Meanwhile, meaningless awakening of the chip is avoided, and power consumption of the chip is reduced.
Fig. 6 is a schematic diagram of a module of an SOC provided in the embodiment of the present invention, where SDA and SCL represent signal lines of an I2C bus, and VCC represents a power supply. Fig. 7 is a schematic diagram of a chip control flow provided in an embodiment of the present invention. As shown in fig. 6 and 7, in the embodiment of the present invention, a multi-stage circuit (including a read-write determining circuit, an I2C data receiving circuit, and a data determining circuit) is added, and after detecting the address matching of I2C, if it is determined to be a write operation, a wake-up signal is not initiated to wake up the SOC, but data continues to be received. When the received data packet meets a preset condition (for example, a valid secondary address or command), the operation of waking up the SOC is actually initiated. Specifically, the I2C IO control circuit is used to control the input/output state of the input/output port. The I2C address receiving circuit receives the I2C start bit and the I2C device address, judges whether the I2C device address sent by the host matches the local address, and returns to the bus idle state when the addresses do not match. When the addresses are matched, the read-write judging circuit further judges whether the subsequent target operation is read operation or write operation according to the received I2C equipment addresses, and when the subsequent target operation is judged to be read operation, the wake-up operation is directly initiated. When it is determined to be a write operation, the I2C data receiving circuit receives the target data, and determines whether the target data satisfies a preset target condition by the data determination circuit. The I2C IO control circuit, the I2C address receiving circuit, the read-write judging circuit, the I2C data receiving circuit and the data judging circuit do not need a clock management circuit to provide a working clock and do not need a power management unit to supply power. As shown in fig. 7, when the target data does not satisfy the preset target condition, the bus idle state may be returned, and in another application scenario, when the target data does not satisfy the preset target condition, the bus idle state may also be returned to receive the target data again, which is not limited in this respect. When the target data meet the preset target conditions, a wake-up operation is initiated, the power management unit recovers to supply power to the SOC core power domain, the clock management circuit is started, the clock management circuit provides a working clock for the SOC core power domain, and the CPU is woken up, so that the CPU controls the I2C core circuit to take over the I2C IO control circuit, controls the state of an I2C interface and receives and sends data. The above circuits may also be implemented by corresponding modules or units to realize the same functions, and are not limited herein. Fig. 8 is a schematic diagram of a working state when the SOC wakes up according to an embodiment of the present invention, and fig. 9 is a schematic diagram of a working state when the SOC sleeps according to an embodiment of the present invention. As shown in fig. 8, in the derived protocol PMBUS/SMBUS protocol of I2C, when target data satisfies a target condition (e.g., an address in the target data matches a preset device address), the SOC wakes up. As shown in fig. 9, when the target data does not satisfy the target condition (for example, the address in the target data does not match the preset device address), the SOC will be in the sleep state all the time, and will not enter into sleep after being frequently awakened. For example, when the master is constantly initiating a broadcast, in the prior art, the slave must receive the broadcast and wake up, but it is possible that the master does not actually want to access the current device. In the embodiment of the invention, the judgment of the target data is added, and the response and the awakening are carried out only when the host really wants to access the current equipment (namely, when the preset target condition is met). Therefore, the judgment on the target data is increased, and the meaningless awakening is avoided. Because the chip wake-up process (such as internal power-on, start-up time and the like) is limited during each wake-up, the bus (pulled bus) is influenced to a greater or lesser extent, and the influence on the communication of other devices on the bus can be reduced by avoiding meaningless wake-up, so that the bus communication efficiency is improved. Meanwhile, the current consumption of the chip during working can be avoided due to meaningless awakening, and the power consumption of the chip can be reduced.
In one application scenario, the chip control method is applied in a very low power consumption mode of the SOC, in which the SOC internal LDO (low dropout linear regulator) is turned off, leaving only a very small number of circuits to remain in operation, such as an I2C interface wake-up circuit for waking up the chip. The whole SOC has extremely low standby power consumption and can be used for sensor or multi-machine communication with low power consumption scenes. Fig. 10 is a schematic diagram of multi-machine communication in an extremely low power consumption mode according to an embodiment of the present invention, based on the chip control method, when an I2C host initiates access through a broadcast address, only a corresponding I2C device (I2C device whose target data meets a target condition) wakes up response, and other I2C devices remain dormant. Compared with the prior art, the power consumption reaches the lowest. In the prior art, all I2 cdevices on the bus are constantly awake.
In another application scenario, the chip control method is applied to a low power consumption mode of the SOC, for example, a shutdown mode, in which the LDO inside the SOC is not turned off, power supply is maintained, and the CPU is merely suspended, and can quickly resume operation as long as the clock is recovered. Fig. 11 is a state diagram of the SOC wake-up in this mode, in which the whole wake-up process is shortened compared to the SOC very low power consumption mode, the power management module does not need to resume power supply, and when the wake-up condition is detected to be satisfied, the wake-up is fast, and the situation that the I2C bus is pulled to wait for the CPU hardly occurs.
Therefore, the chip control method provided by the embodiment of the invention can effectively improve the communication efficiency between the devices on the I2C bus and the dormant devices, obviously reduce the power consumption loss generated during the communication between the dormant devices, enable the application scheme and the product of a user to have longer battery endurance time, and is suitable for the PMBUS/SMBUS protocol based on the I2C multi-host communication scene, and the more devices mounted on the bus, the more obvious power saving effect is.
Exemplary device
As shown in fig. 12, corresponding to the chip control method, an embodiment of the present invention further provides a chip control apparatus, where the chip control apparatus includes:
and an address obtaining module 610, configured to obtain the I2C device address.
The I2C device address is an I2C address transmitted through an I2C bus. Specifically, the I2C start bit is received, and when the I2C host is detected to issue the I2C start timing, the corresponding I2C address is obtained through the I2C bus. If it is an abnormal state or disturbance, the address is not received. The abnormal state may be that the upper computer (I2C host) sends an error data packet, and the interference may be a glitch or pulse caused by external electromagnetic interference. Furthermore, all signals which do not conform to the frame format of the correct I2C protocol are filtered out, so as to reduce the influence of interference. The I2C host refers to a host specified in the I2C protocol, and may be a main control chip in the system or an upper PC, which is not specifically limited herein.
A target operation obtaining module 620, configured to obtain a target operation based on the I2C device address when the I2C device address matches the native address, where the target operation is a read operation or a write operation.
The local address is an address corresponding to the chip, and optionally, may be an address corresponding to the SOC in the low power consumption mode. Specifically, the received I2C device address is compared with the local address corresponding to the chip, and whether the received I2C device address matches the local address is determined. When the I2C device address matches the native address, a subsequent target operation is obtained based on the received I2C device address.
And a target data obtaining module 630, configured to obtain the target data when the target operation is a write operation.
When the target operation is a write operation, target data continues to be received. The target data is data continuously transmitted through the I2C bus, and the target data may reflect operations specifically required to be executed by the slave chip, so that whether the corresponding slave chip needs to be woken up may be determined according to the target data. The target data immediately follows the I2C device address, so that the acquisition of the target data can continue after the acquisition of the I2C device address is received.
And the control module 640 is configured to perform wake-up control on the chip when the target data meets a preset target condition.
The preset target condition is a preset condition for judging whether the target data meets the requirement of awakening the current chip. For example, the target condition may be preset such that the number of target data reaches a preset number, and the corresponding chip is awakened after receiving the preset number of target data. The method can effectively control when the chip enters the awakening process, avoid the turning on of an internal clock and a power supply of the chip caused by data communication or interference which is irrelevant to the chip on an I2C bus, and reduce the power consumption of the chip. Meanwhile, the efficiency of waking up a chip (SOC) through an I2C bus is effectively improved, the influence of the chip wake-up process on the I2C bus is reduced, and the bus communication efficiency is improved.
As can be seen from the above, in the chip control apparatus provided in the embodiment of the present invention, the address obtaining module 610 obtains the address of the I2C device; when the I2C device address matches the native address, obtaining, by a target operation obtaining module 620, a target operation based on the I2C device address, where the target operation is a read operation or a write operation; when the target operation is a write operation, target data is acquired by the target data acquisition module 630; when the target data meets a preset target condition, the chip is awakened and controlled by the control module 640. Compared with the prior art, the scheme of the invention further obtains the target operation when the I2C equipment address is matched with the local address, obtains the target data when the target operation is write operation, and performs awakening control on the chip only when the target data meets the preset target condition. The chip clock protection circuit is favorable for avoiding the internal clock and the power supply of the chip from being turned on due to data communication or interference which is irrelevant to the chip on the I2C bus, and reduces the power consumption of the chip.
The chip control device is used for controlling the working state of a chip which is a slave on the I2C bus, and controlling the slave chip to enter a wake-up state or keep a low power consumption state.
Optionally, the target operation obtaining module 620 is specifically configured to: when the I2C device address matches the local address, obtaining the lowest bit value of the I2C device address; and acquiring the target operation based on the value of the lowest bit.
Specifically, in the present embodiment, in the I2C bus protocol, it may be determined whether a subsequent target operation issued by the host is a read operation or a write operation based on whether the lowest order bit value of the I2C device address is 0 or 1, so as to further determine the subsequent operation based on the target operation.
Optionally, the control module 640 is further configured to: and when the target operation is a read operation, performing awakening control on the chip.
In particular, since the I2C protocol is the underlying protocol, in most cases, the next data on the I2C bus after receiving an address will be defined as an application-level address. For example, in the EEPROM, the first data is a page address, and in the SMBUS/PMBUS protocol, the I2C device address is actually a broadcast address, and the first data is a real device address. Thus, if the subsequent target operation is a write operation, the first data is the address to be accessed (at which time the chip does not have to be woken up) and then the data (at which time it does not have to be woken up). If the subsequent target operation is a read operation, the first data is real data, and then the chip has to be awakened.
Specifically, when the target operation is a write operation, the target data is continuously received and acquired by the target data acquiring module 630. Optionally, the target data includes a device address, a register address, or an operation command.
The target data usually follows the I2C device address, and may be a device address, a low memory address or an operation command, and may include other types of data, which is determined by the actual application protocol, and is not limited herein.
After receiving the target data, it may be determined whether the target data meets a preset target condition. Optionally, the control module 640 is specifically configured to: and when the value of the target data is equal to a preset target value or the number of the target data is greater than a preset target number, performing awakening control on the chip.
The preset target condition is a preset condition for judging whether the target data, i.e. the corresponding target operation, points to the chip, and may be preset, or may be set and adjusted according to actual requirements, which is not specifically limited herein. In this embodiment, the target condition may be that a value of the target data is equal to a preset target value, or that the number of the received target data is greater than a preset target number. The specific target condition may also be set according to the type of the target data. For example, when the target data is a device address or a register address, the target condition may be set to be that the device address or the register address in the target data is specifically the same as a preset certain address (SOC address); when the target data is an operation command, the target condition may be set correspondingly such that the number of the received operation commands is greater than a preset target number.
Optionally, when the target data does not meet the preset target condition, the I2C bus may be released to enter an idle state, or the target data may continue to be received, which may be determined specifically according to an actually set target condition, and is not specifically limited herein. For example, when the target condition is that the value of the target data is equal to a preset target value, in the case that the target data does not satisfy the preset target condition, the I2C bus may be released to enter an idle state; when the target condition is that the number of the target data is larger than the preset target number, the receiving of the target data can be returned to continue under the condition that the target data does not meet the preset target condition.
Optionally, the waking up the chip includes: controlling a power management unit of the chip to recover power supply to a core power domain of the chip; starting a clock management unit of the chip, and controlling the clock unit to recover a clock required by the chip; and awakening the central processing unit of the chip.
Specifically, a wake-up operation is initiated, a wake-up signal is sent to notify a power management unit of the SOC, and a wake-up process is entered. The control power management unit resumes power to an SOC core power domain including an I2C core unit, a clock management unit, and a CPU, and starts a clock management unit. The clock management unit recovers clocks required for providing the SOC, including clocks required for the CPU and clocks required for the I2C core unit. And the CPU wakes up to control the I2C core unit, takes over the I2C input/output control unit and continues to transmit data.
Optionally, the chip control device is further configured to: when the I2C device address does not match the local address, the I2C bus is released to enter the idle state.
Specifically, if the I2C device address does not match the local address, it indicates that the local device does not need to process the transaction, so the I2C bus can be released to enter an idle state, and the bus is prevented from being frequently pulled and affecting the communication of other devices on the bus, thereby improving the bus communication efficiency. Meanwhile, meaningless awakening of the chip is avoided, and power consumption of the chip is reduced.
Based on the above embodiment, the present invention further provides an intelligent terminal, and a schematic block diagram thereof may be as shown in fig. 13. The intelligent terminal comprises a processor, a memory, a network interface and a display screen which are connected through a system bus. Wherein, the processor of the intelligent terminal is used for providing calculation and control capability. The memory of the intelligent terminal comprises a nonvolatile storage medium and an internal memory. The nonvolatile storage medium stores an operating system and a chip control program. The internal memory provides an environment for the operation of the operating system and the chip control program in the nonvolatile storage medium. The network interface of the intelligent terminal is used for being connected and communicated with an external terminal through a network. The chip control program realizes the steps of any one of the chip control methods when being executed by a processor. The display screen of the intelligent terminal can be a liquid crystal display screen or an electronic ink display screen.
It will be understood by those skilled in the art that the block diagram of fig. 13 is only a block diagram of a part of the structure related to the solution of the present invention, and does not constitute a limitation to the intelligent terminal to which the solution of the present invention is applied, and a specific intelligent terminal may include more or less components than those shown in the figure, or combine some components, or have different arrangements of components.
In one embodiment, an intelligent terminal is provided, where the intelligent terminal includes a memory, a processor, and a chip control program stored in the memory and executable on the processor, and the chip control program performs the following operation instructions when executed by the processor:
acquiring an I2C device address;
when the I2C device address matches the local address, acquiring a target operation based on the I2C device address, wherein the target operation is a read operation or a write operation;
when the target operation is a write operation, acquiring target data;
and when the target data meet a preset target condition, performing awakening control on the chip.
The embodiment of the present invention further provides a computer-readable storage medium, where a chip control program is stored on the computer-readable storage medium, and when the chip control program is executed by a processor, the steps of any one of the chip control methods provided in the embodiment of the present invention are implemented.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned functions may be distributed as different functional units and modules according to needs, that is, the internal structure of the apparatus may be divided into different functional units or modules to implement all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art would appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other ways. For example, the above-described embodiments of the apparatus/terminal device are merely illustrative, and for example, the division of the above modules or units is only one logical division, and the actual implementation may be implemented by another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed.
The integrated modules/units described above, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow of the method according to the embodiments of the present invention may also be implemented by a computer program, which may be stored in a computer-readable storage medium and can implement the steps of the embodiments of the method when the computer program is executed by a processor. The computer program includes computer program code, and the computer program code may be in a source code form, an object code form, an executable file or some intermediate form. The computer readable medium may include: any entity or device capable of carrying the above-mentioned computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signal, telecommunication signal, software distribution medium, etc. It should be noted that the contents contained in the computer-readable storage medium can be increased or decreased as required by legislation and patent practice in the jurisdiction.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art; the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein.
Claims (10)
1. A method of chip control, the method comprising:
acquiring an I2C device address;
when the I2C device address matches a native address, obtaining a target operation based on the I2C device address, wherein the target operation is a read operation or a write operation;
when the target operation is a write operation, receiving data after the I2C device address is acquired and serving as target data;
and when the target data meet a preset target condition, performing awakening control on the chip.
2. The chip control method according to claim 1, wherein the obtaining a target operation based on the I2C device address when the I2C device address matches a native address comprises:
when the I2C device address matches a native address, obtaining a value of a lowest bit of the I2C device address;
a target operation is obtained based on the value of the lowest bit.
3. The chip control method according to claim 1, wherein after obtaining a target operation based on the I2C device address, the method further comprises:
and when the target operation is a read operation, performing awakening control on the chip.
4. The chip control method according to claim 1, wherein the target data includes a device address, a register address, or an operation command.
5. The chip control method according to claim 1, wherein the performing wake-up control on the chip when the target data meets a preset target condition includes:
and when the value of the target data is equal to a preset target value or the number of the target data is greater than a preset target number, performing awakening control on the chip.
6. The chip control method according to any one of claims 1 to 5, wherein the performing wake-up control on the chip includes:
controlling a power management unit of the chip to recover power supply to a core power domain of the chip;
starting a clock management unit of the chip, and controlling the clock management unit to recover a clock required by the chip;
and awakening the central processing unit of the chip.
7. The chip control method according to claim 1, wherein after obtaining the I2C device address, the method further comprises:
when the I2C device address does not match the native address, the I2C bus is released into an idle state.
8. A chip control apparatus, the apparatus comprising:
the address acquisition module is used for acquiring an I2C device address;
a target operation obtaining module, configured to obtain a target operation based on the I2C device address when the I2C device address matches a native address, where the target operation is a read operation or a write operation;
a target data acquiring module, configured to receive, as target data, data after acquiring the I2C device address when the target operation is a write operation;
and the control module is used for performing awakening control on the chip when the target data meets a preset target condition.
9. An intelligent terminal, characterized in that the intelligent terminal comprises a memory, a processor and a chip control program stored on the memory and operable on the processor, the chip control program, when executed by the processor, implementing the steps of the chip control method according to any one of claims 1 to 7.
10. A computer-readable storage medium, having stored thereon a chip control program, which when executed by a processor implements the steps of the chip control method according to any one of claims 1 to 7.
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