CN112928156A - Floating p-column reverse-conducting type grooved gate super-junction IGBT - Google Patents
Floating p-column reverse-conducting type grooved gate super-junction IGBT Download PDFInfo
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Abstract
The invention provides a reverse conducting type super-junction IGBT (Insulated Gate Bipolar Transistor) device, wherein a second conductive type semiconductor region in a super-junction voltage-resisting layer is floated, the bottom of a groove-shaped Gate structure is surrounded by a heavily doped second conductive type semiconductor region, and a back groove-shaped insulating medium region is contained, the side surface of the back groove-shaped insulating medium region is surrounded by the second conductive type floating region, and the top of the back groove-shaped insulating medium region is surrounded by a first conductive type stopping ring. The device has lower conduction voltage drop, can eliminate the voltage folding phenomenon along with the current, and can avoid the reduction of breakdown voltage.
Description
Technical Field
The invention belongs to a semiconductor device, in particular to a power semiconductor device.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a medium-high voltage power semiconductor switching device. A Super Junction (SJ) is a voltage-withstanding layer structure in which n columns and p columns are alternately arranged, and can enable the n columns and the p columns to obtain higher breakdown voltage under higher doping concentration. When the IGBT adopts a super-junction voltage-withstanding layer structure, a pn junction formed by the n column/p column can be quickly exhausted in the turn-off process, so that the turn-off speed is increased (or the turn-off power consumption is reduced). However, in the ordinary super junction IGBT, the conductivity modulation effect (or carrier storage effect) of the n-pillar and the p-pillar in the on-state is poor, mainly because the p-pillar easily collects holes and smoothly extracts the collected holes to the emitter, which makes it difficult to effectively store the holes in the n-pillar and the p-pillar, increasing the on-state voltage drop. If the p column floats, the holes enter the p column and then flow to the emitter electrode difficultly in the conduction state, the potential of the p column is raised, the p column is restrained from collecting the holes, the conductivity modulation effect of the n column and the p column is enhanced, and the conduction voltage drop is reduced. However, the breakdown voltage of the super junction IGBT structure of the ordinary floating p-pillar may be reduced. In addition, an IGBT is usually used in combination with an antiparallel diode in application. In order to reduce parasitic effects and improve integration, a Reverse diode may also be integrated in the IGBT, which is called a Reverse Conducting IGBT (RC-IGBT). However, the conventional reverse conducting structure may generate a Snap-back (Snap-back) phenomenon of voltage with current, which may be disadvantageous to reliable operation of the device.
Disclosure of Invention
Compared with the common reverse-conducting super-junction IGBT, the reverse-conducting super-junction IGBT device provided by the invention has lower conduction voltage drop, eliminates the voltage folding phenomenon along with the current, and avoids the reduction of breakdown voltage.
Referring to fig. 3 to 5, the present invention provides an inverse conduction type super junction insulated gate bipolar transistor device, wherein a cell structure of the device includes: a current collecting structure (composed of 10, 11, and 20), a lightly doped auxiliary layer 30 of the first conductivity type located above the current collecting structure (composed of 10, 11, and 20), a super junction voltage withstanding layer (composed of 31 and 32) located above the auxiliary layer 30, a base region (composed of 41 and 43) of the second conductivity type and a well region 42 of the second conductivity type located above the super junction voltage withstanding layer (composed of 31 and 32), a heavily doped emitter region 44 of the first conductivity type in contact with at least part of the base region (composed of 41 and 43), and a trench gate structure (composed of 47 and 49) for controlling a switch in contact with the emitter region 44, the base region (composed of 41 and 43), and the super junction voltage withstanding layer (composed of 31 and 32), characterized in that:
the collection structure (made up of 10, 11 and 20) is made up of at least one collector region 10 of the second conductivity type, at least one collector region 11 of the first conductivity type and at least one buffer region 20 of the first conductivity type; the lower surface of the buffer region 20 is in direct contact with both the collector region 10 of the second conductivity type and the collector region 11 of the first conductivity type, and the upper surface of the buffer region 20 is in direct contact with the auxiliary layer 30;
the cell structure comprises a back groove-shaped insulating medium region 12, and the back groove-shaped insulating medium region 12 extends into the auxiliary layer 30; the side surface of the back groove-type insulating medium region 12 is in direct contact with the collector region 10 of the second conductivity type, the collector region 11 of the first conductivity type and the buffer region 20, and the collector region 10 of the second conductivity type and the collector region 11 of the first conductivity type are isolated from each other by the back groove-type insulating medium region 12; the side surface of the back groove-shaped insulating medium region 12 is indirectly contacted with the auxiliary layer 30 through a floating space region 21 of a second conduction type, and the top of the back groove-shaped insulating medium region 12 is indirectly contacted with the auxiliary layer 30 through a stop ring 22 of a first conduction type; collector conductors 1 are covered on the lower surfaces of the collector region 11 of the first conductivity type, the collector region 10 of the second conductivity type and the back groove-shaped insulating medium region 12 and are connected to a collector C through a lead;
the super junction voltage-withstanding layer (composed of 31 and 32) is composed of first conductivity type semiconductor regions 31 and second conductivity type semiconductor regions 32 which are alternately arranged, and the side surfaces of the first conductivity type semiconductor regions 31 in the super junction voltage-withstanding layer and the side surfaces of the second conductivity type semiconductor regions 32 in the super junction voltage-withstanding layer are in contact with each other; the lower surface of the super junction voltage-resistant layer (composed of 31 and 32) is in direct contact with the auxiliary layer 30;
the lower surface of the base region (composed of 41 and 43) is contacted with the first conduction type semiconductor region 31 in the super junction voltage-resisting layer through a first conduction type carrier storage layer 33; the upper surface of the base region (composed of 41 and 43) is at least partially covered with an emitter conductor 2 and is connected to an emitter E through a lead; at least one heavily doped region 43 of the base region (consisting of 41 and 43) is in direct contact with the emitter conductor 2 so as to form an ohmic contact;
the upper surface of the emitter region 44 is covered with an emitter conductor 2 and connected to the emitter E by a wire;
the lower surface of the well region 42 is in direct contact with the semiconductor region 32 of the second conductivity type in the super junction voltage-resistant layer; the well region 42 and the base region (composed of 41 and 43) are isolated from each other through a first type of emitter-connected trench gate structure (composed of 46 and 48) and/or the trench gate structure (composed of 47 and 49) for controlling the switch;
the trench gate structure (consisting of 47 and 49) for controlling the switch comprises a first insulating dielectric layer 49 and a first conductor region 47 surrounded by the first insulating dielectric layer; the first insulating medium layer 49 is in direct contact with the emitter region 44, the base region (composed of 41 and 43), the carrier storage layer 33, and the first conductivity type semiconductor region 31 in the super junction voltage-withstanding layer, or in direct contact with the emitter region 44, the base region (composed of 41 and 43), the well region 42, the carrier storage layer 33, the first conductivity type semiconductor region 31 in the super junction voltage-withstanding layer, and the second conductivity type semiconductor region 32 in the super junction voltage-withstanding layer; the upper surface of the first conductor region 47 is covered with a gate conductor 3 and connected to the gate G by a wire;
the first emitter-connected trench gate structure (made up of 46 and 48) includes a second insulating dielectric layer 48 and a second conductor region 46 surrounded by the second insulating dielectric layer; the second insulating medium layer 48 is in direct contact with the base region (composed of 41 and 43), the well region 42, the carrier storage layer 33, the first conductivity type semiconductor region 31 in the super junction voltage-resistant layer, and the second conductivity type semiconductor region 32 in the super junction voltage-resistant layer; the upper surface of the second conductor region 46 is covered with an emitter conductor 2 and connected to the emitter E by a wire;
the bottom of the groove-shaped gate structure (composed of 47 and 49) for controlling the switch and the bottom of the first emitter-connected groove-shaped gate structure (composed of 46 and 48) are respectively surrounded by the heavily doped semiconductor region 35 of the second conductivity type; the heavily doped second conductivity type semiconductor region 35 is in direct contact with the super junction voltage-resistant layer (composed of 31 and 32);
the first and second conductor regions 47, 46 are comprised of heavily doped polycrystalline semiconductor material; when the first conduction type is n type, the second conduction type is p type; when the first conductivity type is p-type, the second conductivity type is n-type.
Referring to fig. 6 to 8, a trench-type gate structure (composed of 50 and 51) of the second type for connecting the emitter is contained above the semiconductor region 31 of the first conductivity type in the super junction voltage-resistant layer and/or the semiconductor region 32 of the second conductivity type in the super junction voltage-resistant layer; the second type of emitter-connected trench gate structure (composed of 50 and 51) includes a third insulating medium layer 51 and a third conductor region 50 surrounded by the third insulating medium layer, the third insulating medium layer 51 is in direct contact with the base region (composed of 41 and 43), the carrier storage layer 33 and the first conductivity type semiconductor region 31 in the super junction voltage-withstanding layer, or in direct contact with the well region 42 and the second conductivity type semiconductor region 32 in the super junction voltage-withstanding layer, and the upper surface of the third conductor region 50 is covered with an emitter conductor 2 and is connected to the emitter E through a wire; the bottom of the second emitter-connected trench gate structure (made of 50 and 51) is also surrounded by the heavily doped semiconductor region 35 of the second conductivity type.
Referring to fig. 9, the doping concentration of the well region 42 is higher than the doping concentration of the second conductivity type semiconductor region 32 in the super junction voltage-withstanding layer, or equal to or equivalent to the doping concentration of the second conductivity type semiconductor region 32 in the super junction voltage-withstanding layer.
Referring to fig. 10, the doping concentration of the carrier storage layer 33 is higher than the doping concentration of the first-conductivity-type semiconductor region 31 in the super junction voltage-withstanding layer, or equal to or comparable to the doping concentration of the first-conductivity-type semiconductor region 31 in the super junction voltage-withstanding layer.
Drawings
FIG. 1 is a schematic diagram of a common reverse conducting super junction IGBT structure;
FIG. 2 is a schematic diagram of a common p-column floating reverse-conducting super-junction IGBT structure;
FIG. 3 illustrates the present inventionThe reverse conducting super-junction IGBT is characterized in that a p-type well region is arranged above a p column, the p-type well region is isolated from a p-type base region through a first groove-shaped grid structure connected with an emitter, and the bottom of the groove-shaped grid structure is p-type+A zone enclosure;
FIG. 4 shows another reverse conducting super-junction IGBT of the present invention, in which a p-type well region is disposed above the p-pillar, the p-type well region is isolated from the p-type base region by a trench gate structure of a control switch, and the bottom of the trench gate structure is p-type+A zone enclosure;
FIG. 5 shows another reverse conducting super-junction IGBT according to the present invention, in which a p-type well region is disposed above the p-pillar, the p-type well region is isolated from the p-type base region by a trench-type gate structure of the control switch and a first trench-type gate structure connected to the emitter, and the bottom of the trench-type gate structure is p-type+A zone enclosure;
FIG. 6 shows a further reverse conducting super junction IGBT according to the invention with a second emitter-connected trench gate structure above the p-pillar according to FIG. 3;
FIG. 7 shows a further reverse conducting super junction IGBT according to the invention with a second emitter-connected trench gate structure above the n-pillar according to FIG. 4;
FIG. 8 shows a further reverse conducting super junction IGBT according to the invention, wherein a second trench gate structure for connecting the emitter is arranged above the n-pillar and the p-pillar according to FIG. 4;
FIG. 9 shows a further reverse conducting super junction IGBT according to FIG. 3, wherein the p-type well region and the p-pillar have the same doping concentration, and the p-type well region is a part of the p-pillar;
fig. 10 shows a further reverse conducting super junction IGBT according to fig. 3, in which the doping concentration of the carrier storage layer is equal to the doping concentration of the first conducting type region in the super junction voltage-withstanding layer, so that the carrier storage layer becomes a part of the first conducting type region in the super junction voltage-withstanding layer;
fig. 11 shows forward conduction of two reverse-conducting super-junction IGBTs shown in fig. 3 and 1I-VA curve;
fig. 12 forward breakdown of two reverse conducting super junction IGBTs shown in fig. 3 and 2I-VCurve line.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a common reverse conducting super junction IGBT structure, in which a super junction voltage-withstanding layer is composed of an n-pillar (n-pillar region 31) and a p-pillar (p-pillar region 32) and is used for bearing a main applied voltage, a lightly doped n-type auxiliary layer (n-assist layer 30) also bears a part of the applied voltage, and an n-type buffer region (n-buffer region 20) plays a role of a cut-off electric field. In the reverse conducting state, the gate (G) is shorted to the emitter (E), which applies a positive voltage relative to the collector (C). When the voltage exceeds 0.7V, the base region (p-b region 41 and p)+Region 43) and p-pillar (p-pillar region 32) inject holes into the n-pillar (n-pillar region 31) and n-type assist layer (n-assist layer 30). At the same time, an n-type collector region (n)+Region 11) provides electrons that are injected into the base region (p-b region 41 and p) through the n-pillar (n-pilar region 31) and the n-type assist layer (n-assist layer 30)+Region 43) and p-pillar (p-pilar region 32), the reverse diode is conducting. In the forward conduction state, the gate (G) applies a positive voltage relative to the emitter (E), and when this voltage exceeds the threshold voltage, the base region (formed by p-base region 41 and p)+Region 43) forms an electron channel near the interface with the trench gate structure (comprised of 47 and 49) used to control the switch. At this time, the collector (C) is applied with a positive voltage with respect to the emitter (E), and electrons pass from the emitter (E) through the emitter region (n) by the action of the electric field+Region 44) and electron channel into the n-pillar (n-pillar region 31), n-assist layer (n-assist layer 30), n-buffer region (n-buffer region 20), and then into the n-collector region (n-collector region)+Region 11) the device is in MOSFET conduction mode. When the positive voltage of the collector (C) relative to the emitter (E) continues to increase, the current continuously increases, electrons transversely flow through the n-type buffer region (n-buffer region 20) to generate a potential difference of more than 0.7V on the n-type buffer region (n-buffer region 20), the p-type collector region (p-collector region 10) starts to inject holes into the n-type buffer region (n-buffer region 20), and the device is converted into an IGBT conducting mode. In the IGBT conduction mode, unbalanced carriers can be stored in the n-type auxiliary layer (n-assist layer 30), the n column (n-pilar region 31) and the p column (p-pilar region 32), so that the conductivity modulation effect occurs in vivo, and the resistance of the device is reducedThis results in a voltage folding back phenomenon with current. Further, when the device enters the IGBT conducting mode, since the pn junction of the p-pillar (p-pillar region 32) and the n-pillar (n-pillar region 31) is reverse biased, holes in the n-pillar (n-pillar region 31) easily enter the p-pillar (p-pillar region 32) and pass through the base regions (p-b region 41 and p-pillar region 31)+Region 43) is collected by the emitter (E). This results in a reduced storage effect of non-equilibrium carriers in the n column (n-pillar region 31) and the p column (p-pillar region 32), and an increased on-state voltage drop.
Fig. 2 is a common p-pillar floating reverse conduction type super junction IGBT, in fig. 2, a p-type well region (p-w region 42) is above a p-pillar (p-pilar region 32), and the p-type well region (p-w region 42) is not connected with an electrode. The p-type well region (p-w region 42) is connected with the base region (composed of p-base region 41 and p-base region) through a first emitter-connected trench gate structure (composed of 46 and 48)+Region 43) is formed, the p-type well region (p-w region 42) is a floating region. Because the p-type well region (p-w region 42) has no hole passage flowing to the emitter E, in the forward conduction state, holes are accumulated in the p column (p-pilar region 32) after entering the p column (p-pilar region 32), the potential of the p column (p-pilar region 32) is increased, the p column/n column junction becomes a forward biased junction, the concentration of non-equilibrium carriers near the p column/n column junction is higher, the in-vivo conductivity modulation effect is enhanced, and the conduction voltage drop is reduced.
In fig. 2, an n-type carrier storage layer (n-cs layer 33) is used. Although there is no hole path due to the p-type well region (p-w region 42), if there is no n-type carrier storage layer (n-cs layer 33), the holes of the n-pillar (n-pilar region 31) can flow to the base region (formed by p-base region 41 and p-base region 41) more smoothly+Region 43) so that the conductivity modulation effect in the top region of the n-pillar (n-pilar region 31) is weak, which increases the on-state voltage drop to some extent. When an n-type carrier storage layer (n-cs layer 33) with the doping concentration higher than that of the n column (n-pilar region 31) is introduced, the n-type carrier storage layer (n-cs layer 33) can inhibit holes from entering the base region (formed by the p-base region 41 and the p column region 31)+Region 43) to enhance the conductivity modulation effect in the top region of the n-pillar (n-pilar region 31) to further reduce the turn-on voltage drop.
Although the ordinary p-pillar floating reverse-conducting super-junction IGBT shown in fig. 2 can reduce the turn-on voltage drop, the breakdown voltage thereof is low. In the forward blocking state, the high electric field is applied to the bottom of the p-pillar (p-pillar region 32), the top of the n-pillar (n-pillar region 31), and the side interfaces of the p-pillar (p-pillar region 32)/n-pillar (n-pillar region 31). Holes generated by impact ionization caused by high electric field at the top of the n column (n-pilar region 31) directly flow into the base region (formed by p-base region 41 and p-base region+Region 43) while electrons generated by impact ionization flow toward collector C, which does not significantly affect the breakdown voltage. However, holes generated by impact ionization caused by high electric fields at the bottom of the p-pillar (p-pillar region 32) and at the side of the p-pillar (p-pillar region 32) flow upward through the p-pillar (p-pillar region 32). Since the p-well region (p-w region 42) does not provide a hole path, the holes generated by these impact ionization must flow into the p-base region (formed by p-base region 41 and p-base region) through the bottom of the first emitter-connected trench gate structure (formed by 46 and 48) that isolates the p-well region from the p-base region+Zone 43). The high electric field at the bottom of the first emitter-connected trench gate structure (formed by 46 and 48) increases the number of holes generated by impact ionization again when the holes flow through the bottom, the impact ionization effect is increased, and the breakdown voltage is reduced significantly due to the floating of the p-pillar (p-pilar region 32).
In addition, the common p-pillar floating reverse-conducting super-junction IGBT shown in fig. 2 and the common reverse-conducting super-junction IGBT shown in fig. 1 adopt the same back structure, so that the voltage folding back phenomenon with the current exists in the structure of fig. 2 as in the structure of fig. 1.
The main purpose of the invention is to improve the defect of low breakdown voltage of the ordinary p-column floating reverse-conducting super-junction IGBT shown in fig. 2, improve the defect of voltage folding phenomenon along with current existing in the ordinary reverse-conducting super-junction IGBT structure shown in fig. 1 and the structure shown in fig. 2, and have the advantage of low conduction voltage drop.
FIG. 3 is a schematic diagram of a reverse-conducting super-junction IGBT cell structure, which is mainly different from the ordinary p-floating reverse-conducting super-junction IGBT shown in FIG. 2 in that (1) back surface guiding is performedA groove-shaped insulating medium region (12) on the back surface, a p-type floating space region (p region 21) and an n-type stop ring (n-ring region 22) are arranged in the groove-shaped insulating medium region, so that the folding phenomenon of voltage along with current is eliminated; (2) the bottom of the first type of emitter-connected trench gate structure (composed of 46 and 48) and the bottom of the trench gate structure (composed of 47 and 49) for controlling the switch are heavily doped p-type regions (p)+Region 35) to help eliminate the breakdown voltage drop caused by p-pillar floating (p-pilar region 32).
At zero bias, depletion of the n-type assist layer (n-assist region 30) between two adjacent p-type floating regions (p regions 21) occurs due to the built-in potential, e.g., 0.7V, between the p-type floating region (p region 21) and the n-type assist layer (n-assist layer 30). When the pitch of the adjacent two p-type floating regions (p regions 21) is sufficiently small, the n-type auxiliary layer (n-assist region 30) between them can be completely depleted, which allows the n-type collector region (n-assist region 30) to be reached from the neutral region of the n-type auxiliary layer+Region 11) is closed.
In the forward conduction state, when the positive voltage applied between the gate (G) and the emitter (E) is greater than the threshold voltage of the trench gate structure (composed of 47 and 49) for controlling the switch, (composed of p-base region 41 and p)+Region 43) and a trench gate structure (consisting of 47 and 49) for controlling the switch, an emitter region (n)+Region 44) to the n-pillar (n-pilar region 31). Electrons pass from the emitter (E) through the emitter region (n) due to a positive voltage applied between the collector (C) and the emitter (E)+Region 44) and electron accumulation layer channel into the n-pillar (n-pilar region 31) and n-type assist layer (n-assist layer 30). From the neutral region of the n-type auxiliary layer (n-assist layer 30) to the n-type collector region (n)+Region 11) is turned off, electrons that have entered the n-type auxiliary layer (n-assist layer 30) enter the p-type collector region (p-collector region 10), thereby causing holes to be injected from the p-type collector region (p-collector region 10) into the n-type auxiliary layer (n-assist layer 30), and the device directly enters the IGBT conduction mode, so that the voltage folding back phenomenon with current is eliminated.
In the blocking state, a heavily doped p-type region (p)+Region 35) is substantially not depleted, so the electric field at the bottom of the first emitter-connected trench gate structure (comprised of 46 and 48) is relatively low and the high electric field is shifted to the heavily doped p-type region (p)+Region 35) and the contact surface of the super junction voltage-withstanding layer (composed of n-pilar region 31 and p-pilar region 32). Thus, holes generated by impact ionization at the bottom of the p-pillar (p-pillar region 32) and at the side of the p-pillar (p-pillar region 32) do not undergo impact ionization again while flowing through the bottom of the first emitter-connected trench gate structure (composed of 46 and 48), and the breakdown voltage of the device is not affected by the floating of the p-pillar (p-pillar region 32).
In FIG. 4, the main difference from the structure of FIG. 3 is that the p-type top region (formed by p-top region 42 and p-top region)+Region 45) with the base region (formed by p-b regions 41 and p) by controlling the trench gate structure of the switch (formed by 47 and 49)+Region 43) is formed. In the blocking state, the electric field at the bottom of the trench gate structure (consisting of 47 and 49) for controlling the switch is relatively low. Thus, holes generated by impact ionization at the bottom of the p-pillar (p-pillar region 32) and at the side of the p-pillar (p-pillar region 32) do not undergo impact ionization again while flowing through the bottom of the trench-type gate structure (composed of 47 and 49) for controlling the switch, and the breakdown voltage of the device is not affected by the floating of the p-pillar (p-pillar region 32).
In FIG. 5, the main difference from the structure of FIG. 4 is the p-type top region (formed by p-top region 42 and p-top region)+Region 45) is connected to the base region (formed by p-b regions 41 and p) via the trench gate structure (formed by 47 and 49) of the control switch and the first emitter-connected trench gate structure (formed by 46 and 48)+Region 43) is formed.
In fig. 6, the main difference from the structure of fig. 3 is that there is also a second emitter-connected trench gate structure (consisting of 50 and 51) over the p-pillar (p-pilar region 32). When the density of the groove type grid structure is increased, the electric field concentration effect at the bottom of the groove type grid structure is favorably relieved.
In fig. 7, the main difference from the structure of fig. 4 is that there is also a second emitter-connected trench gate structure (consisting of 50 and 51) over the n-pillar (n-pilar region 31).
In fig. 8, the main difference from the structure of fig. 4 is that there is a second emitter-connected trench gate structure (consisting of 50 and 51) over both the p-pillar (p-pilar region 32) and the n-pillar (n-pilar region 31).
The main difference between the structure of fig. 9 and that of fig. 3 is that the p-well region (p-w region 42) and the p-pillar (p-pillar region 32) have the same doping concentration, and the p-well region (p-w region 42) and the p-pillar (p-pillar region 32) become the same region.
The main difference between the structures of fig. 10 and 3 is that the n-type carrier storage layer (n-cs layer 33) and the n-pillar (n-pilar region 31) have the same doping concentration, and the n-type carrier storage layer (n-cs layer 33) is a part of the n-pillar (n-pilar region 31).
In order to illustrate the superiority of the reverse-conducting superjunction IGBT according to the present invention, the reverse-conducting superjunction IGBT structure according to the present invention shown in fig. 3 is used as an example to compare with the conventional reverse-conducting superjunction IGBT shown in fig. 1 and the conventional p-pillar floating reverse-conducting superjunction IGBT shown in fig. 2 by simulation calculation. The structures in fig. 1, 2 and 3 are all made of Si materials, a symmetrical super junction structure is adopted, minority carrier lifetimes of electrons and holes are both 5 μ s, and a half cell width is 6 μm; the insulating medium layers (48 and 49) adopt SiO2The thickness of the film is 0.1 mu m; (ii) a The insulating medium region (12) adopts SiO2The width and the depth of the film are respectively 1 μm and 5 μm; the thickness and doping concentration of the n-pillar (n-pillar region 31) and the p-pillar (p-pillar region 32)N pillarRespectively 70 μm and 3X 1015 cm-3(ii) a The thickness and peak concentration in the p-type well region (p-w region 42) are 3 μm and 2.5 × 10, respectively17 cm-3(ii) a The thickness and doping concentration of the n-type auxiliary layer (n-assist layer 30) were 20 μm and 5 × 10, respectively13 cm-3(ii) a In order to ensure that punch-through breakdown does not occur, the n-type buffer region (n-buffer region 20) of the structures of FIGS. 2 and 3 has a thickness and a doping concentration peak of 2 μm and 5 × 10, respectively16 cm-3(ii) a In order to facilitate the comparison of the voltage-dependent current foldbackNeglecting the problem of punch-through breakdown, the n-type buffer region (n-buffer region 20) of the structure of FIG. 1 has thickness and doping concentration peaks of 2 μm and 5 × 10, respectively14 cm-3(ii) a The width, thickness and doping concentration peak of the p-type collector region (p-collector region 10) were 4 μm, 1 μm and 3 × 10, respectively18 cm-3(ii) a n type collector region (n)+Region 11) has a width, thickness and doping concentration peak of 1 μm, 1 μm and 3 × 10, respectively18 cm-3(ii) a The peak concentration at the interface of the n-type termination ring (n-ring region 22) and the back groove-type insulating medium region (12) is 3 × 1018 cm-3The diffusion length is 0.3 μm; the peak concentration at the interface of the p-type floating empty region (p region 21) and the back groove-type insulating medium region (12) is 2 multiplied by 1016 cm-3The diffusion length is 0.4 μm; the thickness of the n-type carrier storage layer (n-cs layer 33) was 1.5 μm, and the doping concentration of the n-type carrier storage layer (n-cs layer 33)N csAdopt 3X 1016 cm-3Is uniformly doped.
FIG. 11 is a forward conduction of the structure of FIG. 3 and the structure of FIG. 1I-VCurve of the grid voltageV G= 15V. The conduction drop (current density ofJ C = 150 A/cm2Lower) is only 1.15V, while the conduction voltage drop for the structure of fig. 1 is 4.9V. In addition, the structure of FIG. 3 has no voltage-dependent current foldback, while the peak doping concentration of the n-type buffer region (n-buffer region 20) in the structure of FIG. 1 is only 5 × 1014 cm-3But there is still a voltage folding back with current. If the structure of FIG. 1 is to ensure sufficient withstand voltage, the peak doping concentration of the n-type buffer region (n-buffer region 20) is increased to 1016 cm-3The thickness of the n-type auxiliary layer (n-assist layer 30) is either increased in order to prevent electric field from passing through to the p-type collector region (p-collector region 10). For increasing the peak doping concentration of the n-type buffer region (n-buffer region 20), if the voltage-to-current folding phenomenon is to be eliminated, the width of the p-type collector region (p-collector region 10) is to be greatly increased so as to greatly increase the resistance of the n-type buffer region (n-buffer region 20) in the lateral direction, but this will make the current more concentrated in the n-type buffer region (n-buffer zone 20) vertically narrow regions, which is detrimental to reliability. In the case of increasing the thickness of the n-type auxiliary layer (n-assist layer 30), a further increase in on-voltage and an increase in off-power consumption are caused due to the increase in the thickness of the n-type auxiliary layer (n-assist layer 30). Therefore, the structure of fig. 3 has significant advantages over the structure of fig. 1 in both turn-on voltage and fold-back phenomena.
FIG. 12 is a forward breakdown of the structure of FIG. 3 and the structure of FIG. 2I-VCurve of the grid voltageV G= 0V. The breakdown voltage of the structure of fig. 3 of the invention is obviously higher than that of the reverse conduction type super junction IGBT of the common floating p column shown in fig. 2. The breakdown voltage of the structure of the figure is approximately 1390V, while the breakdown voltage of the structure of figure 2 is only approximately 1130V. Therefore, the structure of fig. 3 has a significant advantage in breakdown voltage over the structure of fig. 2.
In the above description of many embodiments of the present invention, the n-type semiconductor material can be regarded as a first conductive type semiconductor material, and the p-type semiconductor material can be regarded as a second conductive type semiconductor material. Obviously, according to the principle of the present invention, the n-type and the p-type in the embodiments can be interchanged without affecting the content of the present invention. It is obvious to a person skilled in the art that many other embodiments are possible within the inventive idea without going beyond the claims of the invention.
Claims (4)
1. A reverse conducting type super junction insulated gate bipolar transistor device comprises a unit cell structure which comprises: the semiconductor device comprises a current collection structure, an auxiliary layer, a super-junction voltage-withstanding layer, a base region, a well region, a heavily doped emitter region and a groove-shaped gate structure, wherein the auxiliary layer is located above the current collection structure and is of a lightly doped first conductive type, the super-junction voltage-withstanding layer is located above the auxiliary layer, the base region and the well region are located above the super-junction voltage-withstanding layer, the emitter region is at least partially contacted with the base region and is of a heavily doped first conductive type, and the groove-shaped gate structure is contacted with the emitter region, the base region and the super-junction voltage-withstanding layer and is used:
the current collection structure is composed of at least one collector region of a second conduction type, at least one collector region of a first conduction type and at least one buffer region of a first conduction type; the lower surface of the buffer area is in direct contact with the collector area of the second conduction type and the collector area of the first conduction type, and the upper surface of the buffer area is in direct contact with the auxiliary layer;
the cellular structure comprises a back groove-shaped insulating medium region which extends into the auxiliary layer; the side face of the back groove-type insulating medium region is in direct contact with the collector region of the second conduction type, the collector region of the first conduction type and the buffer region, and the collector region of the second conduction type and the collector region of the first conduction type are isolated from each other by the back groove-type insulating medium region; the side surface of the back groove-shaped insulating medium region is in contact with the auxiliary layer through a second conductive type floating space region, and the top of the back groove-shaped insulating medium region is in contact with the auxiliary layer through a first conductive type stopping ring; collector conductors are covered on the lower surfaces of the collector region of the first conduction type, the collector region of the second conduction type and the back groove-shaped insulating medium region and are connected to collectors through wires;
the super-junction voltage-withstanding layer is composed of semiconductor regions of a first conductivity type and semiconductor regions of a second conductivity type which are alternately arranged, and the side surfaces of the semiconductor regions of the first conductivity type in the super-junction voltage-withstanding layer and the side surfaces of the semiconductor regions of the second conductivity type in the super-junction voltage-withstanding layer are in contact with each other; the lower surface of the super junction voltage-resistant layer is in direct contact with the auxiliary layer;
the lower surface of the base region is in contact with the first-conductivity-type semiconductor region in the super-junction voltage-resisting layer through a first-conductivity-type carrier storage layer; at least part of the upper surface of the base region is covered with an emitter conductor and is connected to the emitter through a lead; at least one heavily doped region in the base region is in direct contact with the emitter conductor so as to form ohmic contact;
the upper surface of the emitting region is covered with an emitter conductor and is connected to the emitter through a lead;
the lower surface of the well region is in direct contact with a second conduction type semiconductor region in the super junction voltage-resisting layer; the well region and the base region are mutually isolated through a first groove-shaped grid structure connected with an emitter and/or the groove-shaped grid structure used for controlling a switch;
the groove-shaped grid structure for controlling the switch comprises a first insulating medium layer and a first conductor region surrounded by the first insulating medium layer; the first insulating medium layer is in direct contact with the emitter region, the base region, the carrier storage layer and a first conductive semiconductor region in the super junction voltage-resisting layer, or in direct contact with the emitter region, the base region, the well region, the carrier storage layer, a first conductive semiconductor region in the super junction voltage-resisting layer and a second conductive semiconductor region in the super junction voltage-resisting layer; the upper surface of the first conductor region is covered with a grid conductor and is connected to the grid through a lead;
the first emitter-connected groove-shaped gate structure comprises a second insulating medium layer and a second conductor region surrounded by the second insulating medium layer; the second insulating medium layer is in direct contact with the base region, the well region, the carrier storage layer, the first conduction type semiconductor region in the super junction voltage-resisting layer and the second conduction type semiconductor region in the super junction voltage-resisting layer; the surface on the second conductor region is covered with an emitter conductor and is connected to the emitter through a lead;
the bottom of the groove-shaped grid structure for controlling the switch and the bottom of the first groove-shaped grid structure connected with the emitter are respectively surrounded by heavily doped semiconductor regions of the second conductivity type; the heavily doped semiconductor region of the second conduction type is in direct contact with the super junction voltage-resisting layer;
the first conductor region and the second conductor region are composed of heavily doped polycrystalline semiconductor material; when the first conduction type is n type, the second conduction type is p type; when the first conductivity type is p-type, the second conductivity type is n-type.
2. The device of claim 1, wherein:
a second groove-shaped grid structure connected with an emitter is arranged above the first conduction type semiconductor region in the super junction voltage-resisting layer and/or the second conduction type semiconductor region in the super junction voltage-resisting layer; the second groove-shaped grid structure connected with the emitter comprises a third insulating medium layer and a third conductor region surrounded by the third insulating medium layer, the third insulating medium layer is in direct contact with the first-conductivity-type semiconductor regions in the base region, the carrier storage layer and the super-junction voltage-withstanding layer or in direct contact with the well region and the second-conductivity-type semiconductor regions in the super-junction voltage-withstanding layer, and an emitter conductor covers the upper surface of the third conductor region and is connected to the emitter through a lead; the bottom of the second emitter-connected trench gate structure is also surrounded by the heavily doped semiconductor region of the second conductivity type.
3. The super junction insulated gate bipolar transistor device of claim 1, wherein:
the doping concentration of the well region is higher than that of the second-conductivity-type semiconductor region in the super-junction voltage-resisting layer, or equal to or equivalent to that of the second-conductivity-type semiconductor region in the super-junction voltage-resisting layer.
4. The device of claim 1, wherein:
the doping concentration of the carrier storage layer is higher than that of the first-conductivity-type semiconductor region in the super-junction voltage-resisting layer, or is equal to or equivalent to that of the first-conductivity-type semiconductor region in the super-junction voltage-resisting layer.
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