CN112928066B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN112928066B CN112928066B CN201911244625.1A CN201911244625A CN112928066B CN 112928066 B CN112928066 B CN 112928066B CN 201911244625 A CN201911244625 A CN 201911244625A CN 112928066 B CN112928066 B CN 112928066B
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- 238000000034 method Methods 0.000 title claims abstract description 136
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 239000010410 layer Substances 0.000 claims description 222
- 239000000463 material Substances 0.000 claims description 74
- 238000005530 etching Methods 0.000 claims description 20
- 239000003989 dielectric material Substances 0.000 claims description 19
- 238000002955 isolation Methods 0.000 claims description 19
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 18
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 18
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims description 18
- 229910052739 hydrogen Inorganic materials 0.000 claims description 18
- 239000001257 hydrogen Substances 0.000 claims description 18
- 229910000041 hydrogen chloride Inorganic materials 0.000 claims description 18
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims description 18
- 239000011241 protective layer Substances 0.000 claims description 18
- 239000007789 gas Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Natural products P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- 229910000078 germane Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 8
- -1 silicon carbide nitride Chemical class 0.000 claims description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 7
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 7
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims description 6
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 description 12
- 238000000231 atomic layer deposition Methods 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 230000009286 beneficial effect Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein the substrate comprises a first region and a second region which are adjacent, the first region is provided with a first fin part, and the second region is provided with a second fin part; forming a first epitaxial layer in the first fin part, wherein the first epitaxial layer comprises a first subsection and a second subsection positioned on the first fin part, and the side wall of the second subsection protrudes out of the side wall of the first subsection in the direction parallel to the surface of the substrate; and forming a second epitaxial layer in the second fin portion. The performance of the semiconductor structure formed by the method is improved.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In the field of semiconductor technology, transistors are currently being widely used as the most basic semiconductor devices. The fin field effect transistor is a new Complementary Metal Oxide Semiconductor (CMOS) transistor, which can improve circuit control, reduce leakage current, shorten gate length of the transistor, greatly increase chip processing speed and greatly reduce power consumption, and has been widely used in circuits of various semiconductor devices.
As the fabrication of integrated circuits progresses toward very large scale integrated circuits, the density of circuits therein increases, and as technology nodes decrease, the size of semiconductor structures formed therewith also decreases, and the process difficulty of forming fin field effect transistors of various sizes increases.
The performance of the fin field effect transistor formed by adopting the prior art is to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof to improve the performance of a fin field effect transistor.
In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first region and a second region which are adjacent, the first region is provided with a first fin part, and the second region is provided with a second fin part; forming a first epitaxial layer in the first fin part, wherein the first epitaxial layer comprises a first subsection and a second subsection positioned on the first fin part, and the side wall of the second subsection protrudes out of the side wall of the first subsection in the direction parallel to the surface of the substrate; and forming a second epitaxial layer in the second fin portion.
Optionally, the device formed in the first region is a P-type device, and the device formed in the second region is an N-type device.
Optionally, the material of the first epitaxial layer includes silicon germanium; the material of the second epitaxial layer comprises phosphorus silicon.
Optionally, before forming the first epitaxial layer in the first fin portion, the method further includes: forming a gate structure on the first region and the second region, wherein the gate structure spans the first fin portion and the second fin portion; and after the grid electrode structure is formed, forming a side wall material layer on the surface of the substrate, the surface of the first fin part and the surface of the second fin part.
Optionally, the material of the side wall material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide nitride.
Optionally, the forming method of the first subsection includes: forming a first mask layer on the surface of the substrate, wherein the first mask layer exposes the surface of the side wall material layer on the first region; etching the side wall material layer on the first region back by taking the first mask layer as a mask until the top surface of the first fin part is exposed, and forming a first side wall on the side wall of the first fin part; etching the first fin part, and forming a first opening in the first fin part; a first subsection is formed within the first opening.
Optionally, the process of forming the first subsection within the first opening includes a first epitaxial growth process; the parameters of the first epitaxial growth process include: the gas comprises mixed gas of dichlorosilane, hydrogen chloride, diborane, germane and hydrogen; the flow range of the dichlorosilane is 20-200 standard milliliters per minute, the flow range of the hydrogen chloride is 10-200 standard milliliters per minute, the flow range of the diborane is 20-100 standard milliliters per minute, the flow range of the germane is 50-500 standard milliliters per minute, and the flow range of the hydrogen is 1-200 standard milliliters per minute; the pressure of the cavity is 100-600 torr; the temperature is 500-800 ℃.
Optionally, after forming the first subsection and before forming the second subsection, the method further comprises: forming a dielectric material layer on the surface of the substrate; etching the dielectric material layer until the first subsection surface and part of the first side wall surface are exposed, forming a dielectric layer on the substrate, wherein the top surface of the dielectric layer is lower than the top surface of the first subsection; and removing the first side wall exposed by the dielectric layer.
Optionally, the forming method of the second subsection includes: forming a second subsection on the first fin portion and the first subsection through a second epitaxial growth process; the parameters of the second epitaxial growth process include: the gas comprises mixed gas of dichlorosilane, hydrogen chloride, diborane, germane and hydrogen; the flow range of the dichlorosilane is 20-200 standard milliliters per minute, the flow range of the hydrogen chloride is 10-200 standard milliliters per minute, the flow range of the diborane is 50-300 standard milliliters per minute, the flow range of the germane is 20-400 standard milliliters per minute, and the flow range of the hydrogen is 1-200 standard milliliters per minute; the pressure of the cavity is 100-600 torr; the temperature is 500-800 ℃.
Optionally, after forming the first epitaxial layer in the first fin portion, before forming the second epitaxial layer in the second fin portion, the method further includes: and forming a protective layer on the surface of the substrate.
Optionally, the forming method of the second epitaxial layer includes: forming a second mask layer on the surface of the substrate, wherein the second mask layer exposes the surface of the protective layer on the second region; etching back the protective layer and the side wall material layer by taking the second mask layer as a mask until the top surface of the second fin part is exposed, and forming a second side wall on the side wall of the second fin part; etching the second fin portion, and forming a second opening in the second fin portion; and forming a second epitaxial layer in the second opening.
Optionally, the process of forming the second epitaxial layer in the second opening includes a third epitaxial growth process; the parameters of the third epitaxial growth process include: mixed gas of dichlorosilane, hydrogen chloride, phosphine and hydrogen; the flow range of the dichlorosilane is 30-150 standard milliliters per minute, the flow range of the hydrogen chloride is 10-200 standard milliliters per minute, the flow range of the hydrogen is 200-2000 standard milliliters per minute, and the flow range of the phosphine is 100-2000 standard milliliters per minute; the pressure of the cavity is 150-650 torr; the temperature is 500-850 ℃.
Optionally, the material of the protective layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.
Optionally, before forming the first epitaxial layer in the first fin portion, the method further includes: and forming an isolation layer on the substrate, wherein the isolation layer is positioned on the side wall of the first fin part and the side wall of the second fin part, and the top surface of the isolation layer is lower than the top surfaces of the first fin part and the second fin part.
Correspondingly, the technical scheme of the invention also provides a semiconductor structure formed by adopting any one of the methods, which comprises the following steps: the semiconductor device comprises a substrate, wherein the substrate comprises a first region and a second region which are adjacent, the first region is provided with a first fin part, and the second region is provided with a second fin part; the first epitaxial layer is positioned in the first fin part and comprises a first subsection and a second subsection positioned on the first fin part, and the side wall of the second subsection protrudes out of the side wall of the first subsection in the direction parallel to the surface of the substrate; and the second epitaxial layer is positioned in the second fin part.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the method for forming the semiconductor structure, the first region is used for forming the PMOS device subsequently, the second region is used for forming the NMOS device subsequently, the carrier of the PMOS device is a hole, the carrier of the NMOS device is an electron, and the mobility of the hole is smaller than that of the electron, so that the volume of the first epitaxial layer is required to be increased to generate larger compressive stress on the channel, and the mobility of the hole carrier is improved. The first epitaxial layer is formed in the first fin portion and comprises a first subsection and a second subsection which is positioned on the first fin portion, and the second subsection side wall protrudes out of the first subsection side wall in the direction parallel to the surface of the substrate, so that the volume of the first epitaxial layer is increased, the situation that a device is short-circuited due to bridging with a second epitaxial layer formed in the second fin portion is avoided, and the performance of the semiconductor structure is improved.
Further, before the first epitaxial layer is formed in the first fin portion, a side wall material layer is formed on the surface of the substrate, the surface of the first fin portion and the surface of the second fin portion, and the side wall material layer can protect the second fin portion and prevent the second fin portion from being damaged when the first epitaxial layer is formed in the first fin portion; meanwhile, the first side wall formed by the side wall material layer can limit the position of the first part, and bridging between the first part and the second epitaxial layer is avoided.
Further, after the first epitaxial layer is formed in the first fin portion, before the second epitaxial layer is formed in the second fin portion, a protection layer is formed on the surface of the substrate, the surface of the first fin portion, the surface of the first epitaxial layer and the surface of the second fin portion, and the protection layer plays a role in protecting the first epitaxial layer so as to prevent the first epitaxial layer from being damaged when the second epitaxial layer is formed in the second fin portion.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to one embodiment;
fig. 2 to 12 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of the existing finfet is to be improved. The analysis will now be described with reference to specific examples.
Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment.
Referring to fig. 1, the method includes: a substrate 100, wherein the substrate 100 comprises a first region I and a second region II which are adjacent to each other, the first region I is provided with a first fin portion 101, and the second region II is provided with a second fin portion 102; the first dielectric layer 103 is located on the substrate 100, the first dielectric layer 103 is located on a part of the side wall of the first fin portion 101 and a part of the side wall of the second fin portion 102, and the top surface of the first dielectric layer 103 is lower than the top surfaces of the first fin portion 101 and the second fin portion 102; a first gate structure (not shown) located on the first region I, the first gate structure crossing the first fin 101, a second gate structure (not shown) located on the second region II, the second gate structure crossing the second fin 102; the first epitaxial layer 104 is located in the first fin portion 101 at two sides of the first gate structure; and the second epitaxial layer 105 is positioned in the second fin part 102 at two sides of the second gate structure.
In the semiconductor structure, the first region I is used to form a PMOS device, and the material of the first epitaxial layer 104 is silicon germanium; the second region II is used to form an NMOS device, and the material of the second epitaxial layer 105 is phosphorus silicon. With the progress of semiconductor technology, the size of the semiconductor structure is smaller and smaller, and in order to obtain better PMOS performance, the volume of the first epitaxial layer 104 needs to be increased to generate a larger compressive stress on the channel, so as to improve the mobility of carriers, which causes bridging between the first epitaxial layer 104 in the adjacent first fin 101 and the second epitaxial layer 105 in the second fin 102, so that a device short circuit occurs, and the performance of the semiconductor device is further affected.
In order to solve the above problems, the technical solution of the present invention provides a semiconductor structure and a forming method thereof, by forming a first epitaxial layer in a first fin portion, where the first epitaxial layer includes a first portion and a second portion located on the first fin portion, and in a direction parallel to a surface of a substrate, a sidewall of the second portion protrudes from the sidewall of the first portion, so that a volume of the first epitaxial layer is increased, and meanwhile, a situation of a device short circuit caused by bridging with a second epitaxial layer formed in a second fin portion is avoided, thereby improving performance of the semiconductor structure.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Note that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
Fig. 2 to 12 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the present invention.
Referring to fig. 2, a substrate 200 is provided, the substrate including a first region I and a second region II adjacent to each other, the first region I having a first fin 201 thereon, and the second region II having a second fin 202 thereon.
In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate comprises silicon germanium, silicon-on-insulator, or germanium-on-insulator.
In this embodiment, the device formed in the first region I is a P-type device, and the device formed in the second region II is an N-type device.
Referring to fig. 3, an isolation layer 203 is formed on the substrate 200, the isolation layer 203 is located on the sidewalls of the first fin 201 and the second fin 202, and the top surface of the isolation layer 203 is lower than the top surfaces of the first fin 201 and the second fin 202.
The isolation layer 203 is used to electrically isolate subsequently formed devices.
The method for forming the isolation layer 203 comprises the following steps: forming a spacer material layer (not shown) on the substrate 200; the isolation material layer is etched back to form the isolation layer 203.
The material of the isolation layer 203 includes silicon oxide, silicon nitride, silicon oxynitride or silicon carbide nitride; the process of forming the isolation material layer includes a chemical vapor deposition process or an atomic layer deposition process.
In this embodiment, the material of the isolation layer 203 includes silicon oxide; the process of forming the isolation material layer comprises a chemical vapor deposition process, and the chemical vapor deposition process can form the isolation material layer with compact structure and thicker thickness.
Referring to fig. 4, gate structures (not shown) are formed on the first region I and the second region II, the gate structures crossing the first fin 201 and the second fin 202.
The gate structure includes a gate dielectric layer (not shown) and a gate layer (not shown) on the gate dielectric layer.
The method for forming the gate structure comprises the following steps: forming a gate dielectric material layer (not shown) on the surface of the substrate 200; forming a gate material layer (not shown) over the gate dielectric material layer; forming a patterned mask layer (not shown) over the gate material layer; and etching the gate material layer and the gate dielectric material layer by taking the patterned mask layer as a mask until the surface of the isolation layer 203 is exposed, so as to form the gate structure.
The material of the gate dielectric layer comprises silicon oxide, a low-K (less than 3.9) dielectric material or a high-K (more than 3.9) dielectric material; the material of the gate layer comprises polysilicon or metal; the process for forming the gate dielectric material layer comprises an atomic layer deposition process or a chemical vapor deposition process; the process for forming the gate material layer comprises a physical vapor deposition process or an atomic layer deposition process; the process of etching the gate material layer and the gate dielectric material layer comprises a dry etching process or a wet etching process.
In this embodiment, the material of the gate dielectric layer includes silicon oxide; the material of the gate layer comprises polysilicon; the process for forming the gate dielectric material layer comprises an atomic layer deposition process, wherein the atomic layer deposition process can form the gate dielectric material layer with thinner thickness and compact structure; the process for forming the grid material layer comprises a physical vapor deposition process, wherein the physical vapor deposition process can form the grid material layer with thicker thickness and compact structure; the process of etching the gate material layer and the gate dielectric material layer comprises a dry etching process, and the dry etching process can form a gate structure with good side wall morphology.
With continued reference to fig. 4, after forming the gate structure, a sidewall material layer 204 is formed on the surface of the substrate 200, the surface of the first fin 201, and the surface of the second fin 202.
The material of the sidewall material layer 204 includes one or more of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide nitride. The process of forming the sidewall material layer 204 includes a chemical vapor deposition process or an atomic layer deposition process.
In this embodiment, the material of the sidewall material layer 204 includes silicon nitride; the process of forming the sidewall material layer 204 includes an atomic layer deposition process, which can form the sidewall material layer 204 with a compact structure and a thinner thickness.
A sidewall material layer 204 is formed on the surface of the substrate 200, the surface of the first fin 201 and the surface of the second fin 202, and the sidewall material layer 204 can protect the second fin 202 from being damaged when the first epitaxial layer is formed in the first fin 201 later.
Next, a first epitaxial layer is formed in the first fin 201, the first epitaxial layer including a first portion and a second portion located on the first fin 201, and the second portion sidewall protrudes from the first portion sidewall in a direction parallel to the surface of the substrate 200. The specific process of forming the first epitaxial layer is shown in fig. 5 to 9.
The material of the first epitaxial layer comprises silicon germanium. Since the first region I is used for forming a PMOS device later, the carrier of the PMOS device is a hole, and the mobility of the hole is smaller than that of the electron, so that the volume of the first epitaxial layer needs to be increased to generate a larger compressive stress on the channel, so as to improve the mobility of the hole carrier.
Referring to fig. 5, a first sidewall 206 is formed on the sidewall of the first fin 201.
The first side wall forming method comprises the following steps: forming a first mask layer 205 on the surface of the substrate 200, where the first mask layer 205 exposes the surface of the sidewall material layer 204 on the first region I; and etching the side wall material layer 204 on the first region I by taking the first mask layer 205 as a mask until the top surface of the first fin 201 is exposed, and forming a first side wall 206 on the side wall of the first fin 201.
A first sidewall 206 is formed on the sidewall of the first fin 201, and the first sidewall 206 can limit the position of a first portion formed in the first fin 201 later, so as to avoid bridging between the first portion and a second epitaxial layer formed in the second fin 202 later, and thus, short circuit occurs.
In this embodiment, the material of the first mask layer 205 includes photoresist. In other embodiments, the material of the first mask layer includes a hard mask layer and a photoresist on the hard mask layer, and the material of the hard mask layer includes silicon oxide or silicon nitride.
Referring to fig. 6, after forming the first sidewall 206, the first fin 201 is etched, and a first opening 207 is formed in the first fin 201.
The first opening 207 exposes a sidewall surface of the first sidewall 206.
The process of etching the first fin 201 includes a dry etching process or a wet etching process. In this embodiment, the process of etching the first fin 201 includes a dry etching process, where the dry etching process can form the first opening 207 with a better sidewall morphology, which is beneficial to forming the first epitaxial layer with a uniform size.
Referring to fig. 7, a first subsection 208 is formed in the first opening 207.
The material of the first section 208 comprises silicon germanium.
The process of forming the first subsection 208 within the first opening 207 includes a first epitaxial growth process; the parameters of the first epitaxial growth process include: the gas comprises mixed gas of dichlorosilane, hydrogen chloride, diborane, germane and hydrogen; the flow range of the dichlorosilane is 20-200 standard milliliters per minute, the flow range of the hydrogen chloride is 10-200 standard milliliters per minute, the flow range of the diborane is 20-100 standard milliliters per minute, the flow range of the germane is 50-500 standard milliliters per minute, and the flow range of the hydrogen is 1-200 standard milliliters per minute; the pressure of the cavity is 100-600 torr; the temperature is 500-800 ℃.
The first epitaxial growth process causes the first subsection 208 to be formed within the first opening 207.
After forming the first sub-portion 208, the first mask layer 205 is removed.
In this embodiment, the process of removing the first mask layer 205 includes an ashing process.
Referring to fig. 8, a dielectric layer 209 is formed on the substrate 200, and the top surface of the dielectric layer 209 is lower than the top surface of the first section 208.
The dielectric layer 209 provides structural support for subsequent formation of a second sub-portion on the first fin 201.
The method for forming the dielectric layer 209 includes: forming a dielectric material layer (not shown) on the surface of the substrate 200; the dielectric material layer is etched back until the surface of the first portion 208 and a portion of the sidewall surface of the first sidewall 206 are exposed, and a dielectric layer 209 is formed on the substrate 200.
The material of the dielectric layer 209 includes silicon oxide, silicon nitride, silicon oxynitride or silicon carbide nitride; the process of forming the dielectric material layer comprises a chemical vapor deposition process or an atomic layer deposition process.
In this embodiment, the material of the dielectric layer 209 includes silicon oxide; the process of forming the dielectric material layer comprises a chemical vapor deposition process, and the chemical vapor deposition process can form the dielectric material layer with compact structure and thicker thickness.
The top surface of the dielectric layer 209 is lower than the top surface of the first portion 208, and a portion of the sidewall surface of the first sidewall 206 is exposed, so that the exposed portion of the first sidewall 206 can be removed, so as to facilitate the subsequent lateral growth when forming a second portion on the first fin 201, and the second portion sidewall protrudes from the first portion 208 sidewall in a direction parallel to the surface of the substrate 200, so as to form a first epitaxial layer with a larger volume.
With continued reference to fig. 8, after the dielectric layer 209 is formed, a portion of the first sidewall 206 exposed by the dielectric layer 209 is removed.
The process of removing the portion of the first sidewall 206 exposed by the dielectric layer 209 includes a dry etching process or a wet etching process. In this embodiment, the process of removing the portion of the first side wall 206 includes a dry etching process, where the dry etching process has a larger etching selectivity ratio for the material of the first side wall 206 and the material of the dielectric layer 209 and the first subsection 208, so that the dielectric layer 209 and the first subsection 208 can be less damaged while the first side wall 206 is removed.
Removing the portion of the first sidewall 206 exposed by the dielectric layer 209 facilitates subsequent lateral growth when forming a second portion on the first fin 201, such that the second portion sidewall protrudes from the first portion 208 sidewall in a direction parallel to the surface of the substrate 200, so as to form a first epitaxial layer with a larger volume.
Referring to fig. 9, a second sub-portion 210 is formed on the first fin 201.
The material of the second subsection 210 comprises silicon germanium.
The forming method of the second subsection 210 includes: a second sub-portion 210 is formed on the first fin 201 and on the first sub-portion 208 by a second epitaxial growth process.
The parameters of the second epitaxial growth process include: the gas comprises mixed gas of dichlorosilane, hydrogen chloride, diborane, germane and hydrogen; the flow range of the dichlorosilane is 20-200 standard milliliters per minute, the flow range of the hydrogen chloride is 10-200 standard milliliters per minute, the flow range of the diborane is 50-300 standard milliliters per minute, the flow range of the germane is 20-400 standard milliliters per minute, and the flow range of the hydrogen is 1-200 standard milliliters per minute; the pressure of the cavity is 100-600 torr; the temperature is 500-800 ℃.
The second epitaxial growth process enables the formed second sub-portion 210 to be larger in volume, so that the first epitaxial layer can generate larger compressive stress on the channel, mobility of hole carriers is improved, and performance of the PMOS device formed in the first region is improved; meanwhile, in the direction parallel to the surface of the substrate 200, the side wall of the second subsection 210 protrudes out of the side wall of the first subsection 208, so that the volume of the first epitaxial layer is increased, and meanwhile, the situation that a device is short-circuited due to bridging with a second epitaxial layer formed in the second fin portion later is avoided, and the performance of the semiconductor structure is improved.
The first epitaxial layer formed here includes the first portion 208 and the second portion 210 located on the first fin portion 201, and in a direction parallel to the surface of the substrate 200, the sidewall of the second portion 210 protrudes from the sidewall of the first portion 208, so that the volume of the first epitaxial layer is increased, and meanwhile, a situation that a device is shorted due to bridging with a second epitaxial layer formed in the second fin portion 202 later is avoided, thereby improving performance of the semiconductor structure.
Referring to fig. 10, after the second sub-portion 210 is formed, a protective layer 211 is formed on the surface of the substrate.
The material of the protective layer 211 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. The process of forming the protective layer 211 includes a chemical vapor deposition process or an atomic layer deposition process.
In this embodiment, the material of the protective layer 211 includes silicon nitride; the process of forming the protective layer 211 includes an atomic layer deposition process capable of forming the protective layer 211 having a dense structure and a thin thickness.
Before the second epitaxial layer is formed in the second fin 202, a protective layer 211 is formed on the surface of the substrate 200, the surface of the first fin 201, the surface of the first epitaxial layer and the surface of the second fin 202, and the protective layer 211 protects the first epitaxial layer and the first fin 201 from damage when the second epitaxial layer is formed in the second fin 202.
Next, a second epitaxial layer is formed within the second fin 202. Please refer to fig. 11 and fig. 12 for a specific forming method.
Referring to fig. 11, a second sidewall 213 is formed on a sidewall of the second fin 202.
The method for forming the second side wall 213 includes: forming a second mask layer 212 on the surface of the substrate, wherein the second mask layer 212 exposes the surface of the protective layer 211 on the second region II; and etching back the protective layer 211 and the sidewall material layer 204 by taking the second mask layer 212 as a mask until the top surface of the second fin portion 202 is exposed, and forming a second sidewall 213 on the sidewall of the second fin portion 202.
A second sidewall 213 is formed on the sidewall of the second fin 202, where the second sidewall 213 can limit the position of the second epitaxial layer formed in the second fin 202 later, which is beneficial to forming a second epitaxial layer with uniform size.
In this embodiment, the material of the second mask layer 212 includes photoresist. In other embodiments, the material of the second mask layer includes a hard mask layer and a photoresist on the hard mask layer, and the material of the hard mask layer includes silicon oxide or silicon nitride.
Referring to fig. 12, the second fin 202 is etched, and a second opening (not shown) is formed in the second fin 202; a second epitaxial layer 214 is formed within the second opening.
The process of etching the second fin 202 may include a dry etching process or a wet etching process. In this embodiment, the process of etching the second fin 202 includes a dry etching process, where the dry etching process can form a second opening with a better sidewall morphology, which is beneficial to forming the second epitaxial layer 214 with a uniform size.
The material of the second epitaxial layer 214 includes phosphorus silicon.
The process of forming the second epitaxial layer 214 within the second opening includes a third epitaxial growth process, the parameters of which include: mixed gas of dichlorosilane, hydrogen chloride, phosphine and hydrogen; the flow range of the dichlorosilane is 30-150 standard milliliters per minute, the flow range of the hydrogen chloride is 10-200 standard milliliters per minute, the flow range of the hydrogen is 200-2000 standard milliliters per minute, and the flow range of the phosphine is 100-2000 standard milliliters per minute; the pressure of the cavity is 150-650 torr; the temperature is 500-850 ℃.
The third epitaxial growth process enables the formed second epitaxial layer 214 to be located in the second opening, so that the situation that the second epitaxial layer 214 is too large in volume and is bridged with the first epitaxial layer to cause short circuit of a device is avoided, and performance of the semiconductor structure is improved.
After the second epitaxial layer 214 is formed, the second mask layer 212 is removed.
In this embodiment, the process of removing the second mask layer 212 includes an ashing process.
In this way, in the semiconductor structure formed, bridging is not easy to occur between the first epitaxial layer in the first fin 201 and the second epitaxial layer 214 in the second fin 202, so that performance of the semiconductor structure is improved.
Correspondingly, the embodiment of the invention further provides a semiconductor structure formed by the method, please continue to refer to fig. 12, which includes:
a substrate 200, wherein the substrate 200 comprises a first region I and a second region II which are adjacent to each other, the first region I is provided with a first fin 201, and the second region II is provided with a second fin 202;
a first epitaxial layer within first fin 201, the first epitaxial layer comprising a first portion 208 and a second portion 210 on first fin 201, the second portion 210 sidewalls protruding from the first portion 208 sidewalls in a direction parallel to the surface of substrate 200;
a second epitaxial layer 214 is located within the second fin 202.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (14)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first region and a second region which are adjacent, the first region is provided with a first fin part, and the second region is provided with a second fin part;
forming a gate structure on the first region and the second region, wherein the gate structure spans the first fin portion and the second fin portion;
after forming the grid structure, forming a side wall material layer on the surface of the substrate, the surface of the first fin part and the surface of the second fin part;
forming a first side wall on the side wall of the first fin portion based on the side wall material layer;
etching the first fin part, and forming a first opening in the first fin part, wherein the first opening exposes the surface of the side wall of the first side wall;
forming a first subsection within the first opening;
forming a second part on the first fin part and the first part, wherein the first part and the second part form a first epitaxial layer, and the side wall of the second part protrudes out of the side wall of the first part in the direction parallel to the surface of the substrate; and forming a second epitaxial layer in the second fin portion.
2. The method of forming a semiconductor structure of claim 1, wherein the devices formed in the first region are P-type devices and the devices formed in the second region are N-type devices.
3. The method of forming a semiconductor structure of claim 2, wherein the material of the first epitaxial layer comprises silicon germanium; the material of the second epitaxial layer comprises phosphorus silicon.
4. The method of forming a semiconductor structure of claim 1, wherein the material of the sidewall material layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.
5. The method for forming a semiconductor structure according to claim 1, wherein the method for forming a first sidewall comprises: forming a first mask layer on the surface of the substrate, wherein the first mask layer exposes the surface of the side wall material layer on the first region; and etching the side wall material layer on the first region by taking the first mask layer as a mask until the top surface of the first fin part is exposed, and forming a first side wall on the side wall of the first fin part.
6. The method of forming a semiconductor structure of claim 5, wherein the process of forming a first subsection within the first opening comprises a first epitaxial growth process; the parameters of the first epitaxial growth process include: the gas comprises mixed gas of dichlorosilane, hydrogen chloride, diborane, germane and hydrogen; the flow range of the dichlorosilane is 20-200 standard milliliters per minute, the flow range of the hydrogen chloride is 10-200 standard milliliters per minute, the flow range of the diborane is 20-100 standard milliliters per minute, the flow range of the germane is 50-500 standard milliliters per minute, and the flow range of the hydrogen is 1-200 standard milliliters per minute; the pressure of the cavity is 100-600 torr; the temperature is 500-800 ℃.
7. The method of forming a semiconductor structure of claim 1, further comprising, after forming the first subsection and before forming the second subsection: forming a dielectric material layer on the surface of the substrate; etching the dielectric material layer until the first subsection surface and part of the first side wall surface are exposed, forming a dielectric layer on the substrate, wherein the top surface of the dielectric layer is lower than the top surface of the first subsection; and removing the first side wall exposed by the dielectric layer.
8. The method of forming a semiconductor structure of claim 7, wherein the process of the second subsection comprises: a second epitaxial growth process; the parameters of the second epitaxial growth process include: the gas comprises mixed gas of dichlorosilane, hydrogen chloride, diborane, germane and hydrogen; the flow range of the dichlorosilane is 20-200 standard milliliters per minute, the flow range of the hydrogen chloride is 10-200 standard milliliters per minute, the flow range of the diborane is 50-300 standard milliliters per minute, the flow range of the germane is 20-400 standard milliliters per minute, and the flow range of the hydrogen is 1-200 standard milliliters per minute; the pressure of the cavity is 100-600 torr; the temperature is 500-800 ℃.
9. The method of forming a semiconductor structure of claim 1, further comprising, after forming a first epitaxial layer, before forming a second epitaxial layer within the second fin: and forming a protective layer on the surface of the substrate.
10. The method of forming a semiconductor structure of claim 9, wherein the method of forming a second epitaxial layer comprises: forming a second mask layer on the surface of the substrate, wherein the second mask layer exposes the surface of the protective layer on the second region; etching back the protective layer and the side wall material layer by taking the second mask layer as a mask until the top surface of the second fin part is exposed, and forming a second side wall on the side wall of the second fin part; etching the second fin portion, and forming a second opening in the second fin portion;
and forming a second epitaxial layer in the second opening.
11. The method of forming a semiconductor structure of claim 10, wherein the process of forming a second epitaxial layer within the second opening comprises a third epitaxial growth process; the parameters of the third epitaxial growth process include: mixed gas of dichlorosilane, hydrogen chloride, phosphine and hydrogen; the flow range of the dichlorosilane is 30-150 standard milliliters per minute, the flow range of the hydrogen chloride is 10-200 standard milliliters per minute, the flow range of the hydrogen is 200-2000 standard milliliters per minute, and the flow range of the phosphine is 100-2000 standard milliliters per minute; the pressure of the cavity is 150-650 torr; the temperature is 500-850 ℃.
12. The method of forming a semiconductor structure of claim 11, wherein the material of the protective layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.
13. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the first epitaxial layer: and forming an isolation layer on the substrate, wherein the isolation layer is positioned on the side wall of the first fin part and the side wall of the second fin part, and the top surface of the isolation layer is lower than the top surfaces of the first fin part and the second fin part.
14. A semiconductor structure formed by the method of any of claims 1 to 13, comprising:
the semiconductor device comprises a substrate, wherein the substrate comprises a first region and a second region which are adjacent, the first region is provided with a first fin part, and the second region is provided with a second fin part;
the first side wall is positioned on the side wall of the first fin part;
a first opening in the first fin, the first opening exposing the first sidewall surface;
a first section located within the first opening;
the second part is positioned on the first fin part and the first part, the first part and the second part form a first epitaxial layer, and the side wall of the second part protrudes out of the side wall of the first part in the direction parallel to the surface of the substrate;
and the second epitaxial layer is positioned in the second fin part.
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| CN104733312A (en) * | 2013-12-18 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Fin-type field effect transistor forming method |
| CN107591327A (en) * | 2016-07-06 | 2018-01-16 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin field effect pipe |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104733312A (en) * | 2013-12-18 | 2015-06-24 | 中芯国际集成电路制造(上海)有限公司 | Fin-type field effect transistor forming method |
| CN107591327A (en) * | 2016-07-06 | 2018-01-16 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin field effect pipe |
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