CN112927651A - Pixel driving circuit, active electroluminescent display and driving method - Google Patents

Pixel driving circuit, active electroluminescent display and driving method Download PDF

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Publication number
CN112927651A
CN112927651A CN202110159082.4A CN202110159082A CN112927651A CN 112927651 A CN112927651 A CN 112927651A CN 202110159082 A CN202110159082 A CN 202110159082A CN 112927651 A CN112927651 A CN 112927651A
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transistor
capacitor
voltage
circuit
light emitting
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CN112927651B (en
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吴为敬
邹培安
刘淳
徐延港
梅相霖
徐苗
王磊
彭俊彪
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South China University of Technology SCUT
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South China University of Technology SCUT
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Priority to PCT/CN2021/123678 priority patent/WO2022166246A1/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The invention discloses a pixel driving circuit, an active electroluminescent display and a driving method, comprising a light-emitting element; a current source including a driving transistor connected to the light emitting element, the current source supplying a driving current having different amplitudes to the light emitting element according to a voltage applied to a gate terminal of the driving transistor; the current control circuit is connected with the current source and is used for supplying voltages with different levels to the grid terminal of the driving transistor; a PWM generating circuit for generating a PWM pulse signal for controlling the on-time of the light emitting element; the shaping circuit is used for shaping the PWM pulse signal; and a PWM control circuit for obtaining the duration time for controlling the driving current of the light-emitting element according to the shaped PWM pulse signal and the output voltage of the current control circuit. The invention inputs the ramp signal after the scanning control signal of each row is input, and can realize larger PWM pulse width.

Description

Pixel driving circuit, active electroluminescent display and driving method
Technical Field
The invention relates to the field of photoelectric display, in particular to a pixel driving circuit, an active electroluminescent display and a driving method.
Background
Compared with the traditional Liquid Crystal Display (LCD) and organic light emitting diode display (OLED), the Micro light emitting diode (Micro LED) display technology is praised as the ultimate display technology by virtue of the display advantages of high brightness, high contrast, wide color gamut, long service life and nanosecond-level response speed. However, Micro LED display technology currently encounters some technical challenges, including chip manufacturing, bulk transfer, monolithic integration, colorization implementation, driver circuit design, etc. Compared with the OLED, the Micro LED has very steep I-V characteristics, the luminous efficiency is reduced under low current density, and the problem of color cast of the Micro LED is caused under different current driving conditions, so that a driving circuit of the Micro LED cannot be used for driving the driving circuit of the OLED, and the Micro LED needs to be specially designed again.
Currently, there are many research teams and companies publishing display driving schemes for Micro LEDs, which can be roughly classified into the following categories: passive drive schemes, CMOS active drive schemes and TFT active drive schemes. The passive driving means that the Micro LED does not continuously emit light in a display period of one frame, the brightness of the Micro LED is related to the duty ratio of the Micro LED during column gating in a line scanning period, the light emitting time is shorter and shorter along with the improvement of the resolution of the display screen, and only the driving current can be increased in order to improve the light emitting brightness, which causes the increase of power consumption. Therefore, the passive driving scheme can only be used on small-sized display screens. In contrast, the active driving scheme enables the Micro LED to emit light continuously, and the CMOS or TFT can control each pixel to emit light individually, which is suitable for high resolution and large size display.
Although an active driving scheme of a Micro LED based on PWM (pulse width modulation) has been proposed in the prior art, for the active digital PWM driving scheme, since gray scales are expressed by a method of a molecular frame, the number of gray scales that can be expressed is limited, and an erroneous profile problem is generated. For the active analog PWM driving scheme, the slope setting of the ramp control signal is relatively small, so that the rising time or the falling time of the generated PWM signal is relatively long, and the Micro LED may generate color shift, uneven brightness, and the like during low gray scale display.
Therefore, the PWM signal generated by the active analog PWM driving needs to be shaped to improve the color and brightness uniformity in the case of low gray scale display.
Disclosure of Invention
To overcome the disadvantages and shortcomings of the prior art, a first object of the present invention is to provide a pixel driving circuit of an active electroluminescent display, which can shape an analog PWM pulse signal to ensure display quality at low gray scale.
It is a second object of the present invention to provide a driving method of a pixel driving circuit of an active electroluminescent display.
It is a third object of the invention to provide an active electroluminescent display.
The first purpose of the invention adopts the following technical scheme:
a pixel driving circuit of an active electroluminescent display, comprising:
a light emitting element;
a current source including a driving transistor connected to the light emitting element, the current source supplying a driving current having different amplitudes to the light emitting element according to a voltage applied to a gate terminal of the driving transistor;
the current control circuit is connected with the current source and is used for supplying voltages with different levels to the grid terminal of the driving transistor;
a PWM generating circuit for generating a PWM pulse signal for controlling the on-time of the light emitting element;
the shaping circuit is used for shaping the PWM pulse signal;
and a PWM control circuit for obtaining the duration time for controlling the driving current of the light-emitting element according to the shaped PWM pulse signal and the output voltage of the current control circuit.
Further, the light emitting element is a light emitting diode or an organic light emitting diode.
Further, the PWM generation circuit includes a first capacitor, a second capacitor, a first transistor, a second transistor, and a third transistor; the drain electrode of the first transistor is connected with a first data signal line, the source electrode of the first transistor is connected with a first polar plate of the first capacitor, and the grid electrode of the first transistor is connected with a first scanning control line; the drain electrode of the second transistor is connected with a high-potential power supply, the source electrode of the second transistor is connected with the first pole plate of the second capacitor and the drain electrode of the third transistor, and the grid electrode of the second transistor is connected with the first scanning control line; the source electrode of the third transistor is connected with a low-potential power supply, and the grid electrode of the third transistor is connected with the first polar plate of the first capacitor; the second plate of the first capacitor is connected with a ramp signal data line; and the second plate of the second capacitor is connected with a low-potential power supply.
Further, the on-time of the first transistor is set according to the scanning signal of the grid electrode of the first transistor, and the on-time is used for controlling the voltage amplitude of the PWM pulse to charge the first capacitor;
setting the conduction time of a second transistor according to a scanning signal of the grid electrode of the second transistor, and controlling the voltage amplitude of a PWM pulse to charge the second capacitor;
after the first capacitors and the second capacitors of all the pixels receive data, the second data signal line starts to output a linear rising voltage signal, the linear rising voltage signal is loaded to the second plate of the first capacitor, the voltage of the second plate of the first capacitor is linearly raised through the coupling effect of the first capacitor, and the voltage reaches the threshold voltage V of the third transistorTHAt this time, the voltage of the first plate of the second capacitor is discharged through the third transistor, thereby generating the PWM pulse signal.
Further, the PWM shaping circuit comprises a phase inverter and a positive feedback circuit, one end of the positive feedback circuit is connected with the first polar plate of the second capacitor, the other end of the positive feedback circuit is connected with the input end of the phase inverter, and the output end of the phase inverter is connected with the PWM control circuit.
Further, the phase inverter is an N-type transistor, a P-type transistor or a transistor formed by mixing and integrating N-type and P-type transistors.
Further, the first transistor, the second transistor, and the third transistor are all switching transistors.
Further, the PWM control circuit includes a switching transistor having a gate connected to an output portion of the inverter of the PWM shaping circuit, a drain connected to a cathode portion of the light emitting element, and a source connected to a drain portion of the driving transistor.
The invention adopts a pre-charging and re-discharging type PWM generating circuit and a shaping circuit with a positive feedback circuit structure to realize microsecond PWM rising and falling time control.
The PWM generating circuit pre-charges the storage capacitor to a high potential through the upper transistor in a scanning programming stage, then the voltage of the ramp signal slowly rises, and the lower transistor is gradually conducted to enable the ramp signal to be gradually discharged to a low level, so that a PWM signal is formed. Since the upper transistor is turned off when the capacitor is discharged, the discharge speed is fast compared to the CMOS inverter structure. The shaping circuit shapes the PWM signal through the inverter and the positive feedback circuit structure, the output part of the inverter is connected to the input part of the positive feedback circuit, the capacitor discharge speed of the PWM generating circuit is accelerated, microsecond-level rising and falling time is realized, and therefore accurate constant current PWM control of the light-emitting element is realized.
The second purpose of the invention adopts the following technical scheme:
a method of driving a pixel driving circuit of an active electroluminescent display, comprising the stages of:
(1) initialization: the transistor on the PWM generating circuit is turned on by a scanning signal to charge the capacitor, and then turned off to store a high potential on the capacitor.
(2) A data loading stage: the scan signal controls the transistor to store the data voltage on the capacitor, and then the transistor is turned off to realize the storage of the data voltage. Threshold voltage compensation of a driving transistor and a lower transistor of the PWM generating circuit can be achieved through design of a driving signal at the stage, and after data loading is finished, a slope data line sweep starts to be input and rises linearly.
(3) The light emitting element emits light: the second data signal line starts to input a fixed voltage to the gate of the driving transistor, thereby controlling a current flowing in the light emitting element; a PWM control circuit for receiving the PWM signal controls the duration of the current in the light emitting element, thereby realizing the PWM control of the constant current of the light emitting element.
The third purpose of the invention is to adopt the following technical scheme:
an active light emitting display includes pixel driving circuits arranged in an array.
The invention has the beneficial effects that:
1. the invention utilizes pure N-type transistors or pure P-type transistors to realize the PWM generating circuit effect which is more excellent than the CMOS structure.
2. The pixel driving circuit can realize us-level PWM pulse width control and can realize display control of the light-emitting element under low gray scale.
3. The driving method of the pixel circuit of the active electroluminescent display device can adopt a scanning type slope scheme, namely, a slope signal is input after the scanning control signal of each row is input, and larger PWM pulse width can be realized.
Drawings
FIG. 1 is a block diagram of a pixel driving circuit of an active electroluminescent display according to the present invention;
FIG. 2 is a circuit diagram of FIG. 1;
FIG. 3 is a schematic view of an active electroluminescent display according to embodiment 1 of the present invention;
FIG. 4 is a schematic diagram of a pixel driving circuit according to embodiment 1 of the present invention;
FIG. 5 is a timing diagram of the circuit of FIG. 4 according to embodiment 1 of the present invention;
fig. 6 is a schematic diagram of a pixel drive circuit according to embodiment 2 of the present invention;
FIG. 7 is a timing diagram for the driving of FIG. 7 according to the present invention;
fig. 8 is a schematic view of an active electroluminescent display of embodiment 3 of the present invention;
fig. 9 is a schematic diagram of a pixel drive circuit according to embodiment 3 of the present invention;
FIG. 10 is a timing diagram for the driving of FIG. 10 according to the present invention;
fig. 11 is a schematic view of an active electroluminescent display of embodiment 4 of the present invention;
FIG. 12 is a schematic diagram of a pixel driving circuit according to embodiment 4 of the present invention;
fig. 13 is a driving timing chart of embodiment 4 of the present invention.
Detailed Description
The present invention will be described in further detail with reference to examples and drawings, but the present invention is not limited to these examples.
Example 1
As shown in fig. 3, an active electroluminescent display device is constructed basically by a Pixel array section Pixel, a Scan driver Scan and a DATA input driver DATA, a DATA input driver ba. The pixel array section is connected to SCAN lines SCAN arranged in rows, first data signal lines and second data signal lines arranged in columns, and includes a plurality of power supply lines for supplying a low potential power supply VSS and a high potential power supply VDD required for the operation of the pixels. The first DATA signal line required by the operation of the pixel is used for controlling the pulse width of a PWM signal, the second DATA signal line is used for controlling the output current of a current source, the low-potential power supply VSS is also used for grounding, the high-potential power supply VDD is used for supplying power to the pixel, the first DATA signal line is used for outputting DATA input drivers DATA, the second DATA signal line is used for outputting DATA input drivers ba, the scanning control line is output by a scanning driver Scan, and the slope signal DATA line sweet generates a slope DATA signal.
As shown in fig. 1 and 2, the pixel array section is constituted by N × M pixel driving circuits including
Light-emitting element, in particular light-emitting diode or organic light-emitting diode
A current source including a driving transistor connected to the light emitting element, the current source supplying a driving current having different amplitudes to the light emitting element according to a voltage applied to a gate terminal of the driving transistor;
the current control circuit is connected with the current source and is used for supplying voltages with different levels to the grid terminal of the driving transistor;
a PWM generating circuit for generating a PWM pulse signal for controlling the on-time of the light emitting element;
the shaping circuit is used for shaping the PWM pulse signal;
and a PWM control circuit for obtaining the duration time for controlling the driving current of the light-emitting element according to the shaped PWM pulse signal and the output voltage of the current control circuit.
In this example 1:
the PWM generating circuit comprises a first capacitor C1, a second capacitor C2, a first transistor T1, a second transistor T2 and a third transistor T3; the drain of the first transistor T1 is connected to the first data signal line, the source of the first transistor T1 is connected to the first plate of the first capacitor C1, and the gate of the first transistor T1 is connected to the first scan control line scan (n); the drain of the second transistor T2 is connected to a high potential power supply VDD, the source of the second transistor T2 is connected to the first plate of the second capacitor C2 and the drain of the third transistor T3, and the gate of the second transistor T2 is connected to the first scan control line scan (n); the source electrode of the third transistor T3 is connected with a low potential power supply VSS, and the gate electrode of the third transistor T3 is connected with the first polar plate of the first capacitor; a second plate of the first capacitor C2 is connected with a signal data line sweep; and the second plate of the second capacitor is connected with a low-potential power supply VSS.
The working process is as follows:
setting the conduction time of a first transistor according to a scanning signal of the grid electrode of the first transistor, and controlling the voltage amplitude of a PWM pulse to charge the first capacitor;
setting the conduction time of a second transistor according to a scanning signal of the grid electrode of the second transistor, and controlling the voltage amplitude of a PWM pulse to charge the second capacitor;
after the first capacitors and the second capacitors of all the pixels receive data, the second data signal line is openedA linear rising voltage signal is output and is loaded to the second plate of the first capacitor, the voltage of the second plate of the first capacitor is linearly raised through the coupling effect of the first capacitor, and the voltage reaches the threshold voltage V of the third transistorTHAt this time, the voltage of the first plate of the second capacitor is discharged through the third transistor, thereby generating the PWM pulse signal.
The shaping circuit comprises an inverter and a positive feedback circuit, and particularly comprises a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a ninth transistor T9 and a third capacitor C3, wherein the drain electrode of the fourth transistor is connected with a high-potential power supply VDD, the source electrode of the fourth transistor is connected with the grid electrode of the fifth transistor T5 and the first polar plate of the third capacitor C3 to form a point C, and the grid electrode of the fourth transistor is connected with a second scanning control line SCAN (N + 1).
The drain of the fifth transistor is connected with a high-potential power supply VDD, the source of the fifth transistor is connected with the second plate of the third capacitor C3 to form a point D, and the point D is connected with the PWM control circuit.
The drain of the sixth transistor is connected to the point D, the source thereof is connected to the low potential power source VSS, the gate thereof is connected to the drain of the ninth transistor at the point B, the point B is connected to the source of the second transistor and the drain of the third transistor, and the source of the sixth transistor is connected to the second plate of the second power source.
A source of the ninth transistor is connected to a low potential power source VSS.
The positive feedback circuit is a ninth transistor, and the inverter is a fourth transistor, a fifth transistor, a sixth transistor and a third capacitor. The main effect is to shape the PWM signal to reduce the rise-fall time of the PWM signal.
The shaping circuit may be further configured to charge the first terminal of the third capacitor with a power supply voltage during a period in which the second SCAN control line SCAN (N +1) of the gate terminal of the fourth switching transistor is turned on.
The PWM control circuit includes only a seventh transistor T7 for controlling the on/off of the current in the light emitting element, and has a gate connected to point D, a source connected to the drain of the eighth transistor, and a drain connected to the cathode of the light emitting element. The current source includes an eighth driving transistor T8, which operates in a saturation region, and the current control circuit is implemented by the second data signal Vba.
The current source is an eighth transistor, the current source is a driving transistor, and the other transistors are switching transistors.
The current source and the current control circuit are connected to control the current flowing in the light-emitting element together; the PWM generating circuit and the shaping circuit can be connected through the first plate of the second capacitor and the drain electrode of the ninth transistor, and the PWM generating circuit and the shaping circuit are commonly applied to the gate terminal of the seventh transistor, so that the duration time of the current of the light-emitting element is controlled through the voltage of the first plate of the first capacitor.
Fig. 5 is a timing diagram illustrating a detailed operation of a pixel circuit according to example embodiment 1. Specifically, fig. 5 shows the Scan control lines Scan (n) and Scan (n +1) applied to the pixel circuit, and the data signal VDATAAnd the ramp signal data Vsweep, the voltage at the gate (point a) of the third transistor T3, the voltage at the first plate (point B) of the second capacitor C2, the voltage at the gate (point C) of the fifth transistor T5, and the voltage at the gate (point D) of the seventh transistor T7, and the driving current Id vary according to time. The pixel circuit performs four stages of initialization, inverter initialization, data loading and light emission of the light emitting element under the control of these control signals and data signals, and the detailed operation of the pixel circuit of each stage is as follows:
(1) initialization: the Scan control line Scan (N) of the pixels of the nth row is given a high level, the Scan control line Scan (N +1) is given a low level, the first transistor T1 and the second transistor T2 are correspondingly turned on, and the fourth transistor T4 is turned off; at this time, the first plate of the first capacitor C1 of the pixel circuit is set to the data voltage VDATAThe first plate of the second capacitor C2 is configured as a high-level power supply voltage VDD; at this time, the sixth transistor T6 is turned on, and the potential at the point D is set to VSS, and the level setting for these points is completed.
(2) Initialization of an inverter: the Scan control line Scan (N +1) of the pixels of the nth row is given a high level, the Scan control line Scan (N) is given a low level, the first transistor T1 and the second transistor T2 are turned off, and the fourth transistor is correspondingly turned on; at this time, the point C of the pixel circuit is set to the high-level power supply voltage VDD, and since the sixth transistor is always in the on state, the point D is set to VSS at this stage, so that a voltage difference VDD-VSS is formed across the third capacitor C3, and initialization of the inverter is completed.
(3) Loading data: the Scan control lines Scan (N) and Scan (N +1) of the pixels of the nth row are all at the low level, and the first transistor T1, the second transistor T2, and the fourth transistor T4 are turned off; the Vsweep voltage starts to increase linearly from a low level to a high level, and the voltage at the first plate A of the first capacitor C1 is V due to the capacitive coupling effect of the first capacitor C1A＝VDATA+VsweepVSS, when the voltage at the point a has not reached the threshold voltage VTH of the third transistor T3, the third transistor T3 is partially turned on so that the potential at the point B is slowly lowered; at this time, when the potential at the point B is lowered to the threshold voltage VTH of the sixth transistor T6, the sixth transistor T6 is gradually turned off, the voltage at the point D is gradually raised, the third capacitor C3 causes the potential at the point C to follow the potential at the point D to rise due to the capacitive coupling effect, and the fifth transistor T5 is better in the on state, so as to accelerate the rise of the potential at the point D; the ninth transistor T9 is gradually turned on as the potential at point D rises, thereby accelerating the discharging process of the potential at point B, forming a positive feedback loop, and accelerating the rising process of the potential at point D.
(4) The light emitting element emits light: in the data loading phase, the second data signal line is changed from the low potential to the input constant voltage, and the D-point potential is changed from the low potential to the high potential to be loaded to the gate of the seventh transistor T7, thereby turning on the seventh transistor, thereby forming a path through the light emitting element, the seventh transistor T7 and the driving eighth transistor T8, and the second data signal line controls the driving eighth transistor T8 to form a constant current in the driving loop.
Example 2
As shown in fig. 3, the structure of the active electroluminescent display of this embodiment 2 is basically composed of a Pixel array section Pixel, a Scan driver Scan, and a DATA input driver DATA, a DATA input driver ba. The pixel array section is connected to SCAN lines SCAN arranged in rows, first data signal lines and second signal data lines arranged in columns, and includes a plurality of power supply lines for supplying a low potential power supply VSS and a high potential power supply VDD required for the operation of the pixels. A first data signal line required for the operation of the pixel is used to control the PWM signal pulse width, a second data signal line is used to control the output current of the current source, the low potential power supply VSS is also used to ground, and the high potential power supply VDD is used to supply power to the pixel.
The display device of the active electroluminescent display is different from the display device of the embodiment 1 in that the CMOS structure is used as the design of the inverter, so that the power consumption of the pixel circuit during operation is reduced, and the effect of saving energy is realized.
Fig. 6 is a circuit diagram of the pixel circuit of this example, and includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 (P-type transistor), a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1, a second capacitor C2, a high potential power supply line VDD, a second DATA signal line ba, a low potential power supply line VSS, a first DATA signal line DATA, a ramp DATA signal Vsweep, and a light emitting element. And the first transistor T1 and the second transistor T2 output a constant current in response to the nth row scan control line scan (n), the seventh transistor T7 controlled by the second data signal Vba.
The seventh transistor is a driving transistor.
The PWM generation circuit may include: a first capacitor having a first terminal connected to the gate terminal of the third transistor and the source terminal of the first transistor; and a second capacitor having a first terminal connected to the drain terminal of the third transistor and the source terminal of the second transistor.
The PWM generation circuit may be further configured to charge the first capacitor with a pulse width control voltage during a period in which an nth row scan control line (scan (n)) of gate terminals of the first and second transistors is turned on, and apply a voltage charged into the first capacitor to a gate terminal of the third transistor; the second capacitor is charged with a supply voltage to the same level as the supply voltage.
The shaping circuit can be composed of an inverter and a positive feedback circuit, and comprises: an eighth transistor having a gate segment connected to a drain terminal of the fourth transistor and a drain terminal of the fifth transistor; and a drain terminal having gate terminals connected to the fourth transistor and the fifth transistor; the fourth transistor is a P-type transistor, wherein the inverter is a fourth transistor T4 and a fifth transistor T5, and the positive feedback circuit is an eighth transistor T8.
The PWM control module may include a sixth transistor, the current source module may include a seventh driving transistor, the seventh driving transistor operates in a saturation region, and the current control circuit is implemented by the second data signal Vba.
The current source and the current control circuit are connected to control the current flowing in the light-emitting element together; the PWM generating circuit and the shaping circuit may be connected through the first terminal of the second capacitor and the drain of the eighth feedback transistor, and the PWM generating circuit and the shaping circuit commonly act on the gate terminal of the sixth switching transistor, so that the duration of the current of the light emitting element is controlled by the voltage of the first terminal of the first capacitor.
The current source in this embodiment is a seventh transistor T7.
Fig. 7 is a timing diagram illustrating a detailed operation of a pixel circuit according to example embodiment 1. In particular, fig. 7 shows the main control signals scan (n), the DATA signal lines DATA and Vsweep applied to the pixel circuit, the voltage at the gate electrode (point a) of the third transistor T3, the voltage at the first plate electrode (point B) of the second capacitor C2, the voltage at the gate electrode (point C) of the sixth transistor T6, and the driving current IdAccording to the change of time. The pixel circuit performs three stages of initialization, data loading and light emission of the light emitting element under the control of these control signals and data signals, and the detailed operation of the pixel circuit of each stage is as follows:
(1) initialization: the scan control line scan (n) of the pixels in the nth row is given a high level, and the first transistor T1 and the second transistor T2 are correspondingly turned on; at this time, the first plate of the first capacitor C1 of the pixel circuit is set to the data voltage VDATAThe first plate of the second capacitor C2 is configured as a high-level power supply voltage VDD; at this time, the process of the present invention,the sixth transistor T6 is turned on, and the potential at the point C is set to VSS, completing the level setting for these points.
(2) Loading data: the scan control line scan (n) of the pixels of the nth row is at a low level, the first transistor T1, the second transistor T2; the Vsweep voltage starts to increase linearly from a low level to a high level, and the voltage at the first plate A of the first capacitor C1 is V due to the capacitive coupling effect of the first capacitor C1A＝VDATA+VsweepVSS at which the voltage has not yet reached the threshold voltage V of the third switching transistor T3THAt this time, the third transistor T3 is partially turned on, so that the potential at the point B is slowly lowered; at this time, when the potential at the point B is lowered to the threshold voltage V of the transistor T5THWhen the potential at the point B is lowered to the threshold voltage V of the transistor T4, the fifth transistor T5 is gradually turned offTHWhen the voltage of the point C is gradually increased, the fourth transistor is gradually switched on; the voltage at point C reaches the threshold voltage V of the eighth transistorTHAt this time, the voltage at point B is discharged through the eighth transistor T8, thereby accelerating the discharging process of the potential at point B, forming a positive feedback loop, and accelerating the rising process of the potential at point C.
(3) The light emitting element emits light: in the data loading phase, the second data signal line is changed from the low potential to the input constant voltage, the potential of the point C is changed from the low potential to the high potential to be loaded to the gate of the sixth transistor T6, thereby turning on the seventh transistor, thereby forming a path through the light emitting element, the sixth transistor T6 and the seventh transistor T7, and the second data signal line controls the seventh transistor T7 to form a constant current in the driving circuit.
Example 3
As shown in fig. 8, the structure of an active electroluminescent display of this embodiment 3 is basically composed of a Pixel array section Pixel, a Scan driver Scan, and a DATA input driver DATA, a DATA input driver ba. The pixel array section is connected to SCAN lines SCAN arranged in rows, first data signal lines and second data signal lines arranged in columns, and includes a plurality of power supply lines for supplying a low potential power supply VSS and a high potential power supply VDD required for the operation of the pixels. The first DATA signal line required by the operation of the pixel is used for controlling the pulse width of a PWM signal, the second DATA signal line is used for controlling the output current of a current source, the low-potential power supply VSS is also used for grounding, the high-potential power supply VDD is used for supplying power to the pixel, the first DATA signal line is used for outputting DATA input drivers DATA, the second DATA signal line is used for outputting DATA input drivers ba, the scanning control line is output by a scanning driver Scan, and the slope signal DATA line sweet generates a slope DATA signal.
The display device of the active electroluminescent display is different from the display device of the embodiment 1 in that the display device of the electroluminescent display utilizes a P-type transistor as a design of an inverter, and adopts a mode of first discharging and recharging to avoid a direct current path generated in the working process of the inverter, thereby reducing the power consumption.
Fig. 9 is a circuit diagram showing a pixel array section formed on the display device shown in fig. 8. Referring to fig. 9, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4(PMOSFET), a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a seventh transistor T8, a first capacitor C1, a second capacitor C2, a third capacitor C3, a high potential power line VDD, a second DATA signal Vba, a low potential power line VSS, a DATA line DATA, a DATA line Vsweep, and a light emitting element; and the first transistor T1 and the second transistor T2 output a constant current in response to the nth row first Scan control line Scan1(n), and the fifth transistor T5 outputs a constant current in response to the nth row second Scan control line Scan2(n), the seventh transistor T7 controlled by the second data signal Vba.
The seventh transistor is a driving transistor.
The PWM generation circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, and a second capacitor C2, the first capacitor having a first terminal connected to a gate terminal of the third transistor and a source terminal of the first transistor; and a second capacitor having a first terminal connected to the drain terminal of the third transistor and the source terminal of the second transistor.
The PWM generation circuit may be further configured to charge the first capacitor with a pulse width control voltage during a period in which an nth row first SCAN control line SCAN1(n) of the gate terminals of the first and second transistors is turned on, and apply a voltage charged into the first capacitor to the gate terminal of the third transistor; the second capacitor is charged with a supply voltage to the same level as the supply voltage.
The shaping circuit can be composed of an inverter and a positive feedback circuit, and comprises: an eighth transistor having a gate segment connected to a drain terminal of the fourth transistor; and a drain terminal having a gate terminal connected to the fourth transistor; a third capacitor having a first terminal connected to the source terminal of the fifth transistor and the gate terminal of the eighth feedback transistor; the fourth transistor and the fifth transistor are P-type transistors.
The inverter is a fourth transistor, a fifth transistor and a third capacitor. The positive feedback circuit is an eighth transistor T8.
The shaping circuit may be further configured to discharge the first plate of the third capacitor with a power supply voltage during a period in which the nth row second SCAN control line SCAN2(n) of the gate terminal of the fifth transistor is turned on.
The PWM control module may include a sixth transistor, the current source module may include a seventh driving transistor, the seventh driving transistor operates in a saturation region, and the current control circuit is implemented by the second data signal Vba.
The current source and the current control circuit are connected to control the current flowing in the light-emitting element together; the PWM generating circuit and the shaping circuit may be connected through the first terminal of the second capacitor and the drain of the eighth feedback transistor, and the PWM generating circuit and the shaping circuit may commonly act on the gate terminal of the sixth transistor, so that the duration of the current of the light emitting element is controlled by the voltage of the first terminal of the first capacitor.
Fig. 10 is a timing diagram illustrating a detailed operation of a pixel circuit according to example embodiment 3. Specific FIG. 10 shows the main control signals Scan1(n) and Scan2(n), data signal V applied to the pixel circuitDATAAnd Vsweep, voltage at the gate (point A) of the third transistor T3, of the second capacitor C2Voltage at the first plate (point B) and gate (point C) of the seventh transistor T7 and driving current IdAccording to the change of time. The pixel circuit performs three stages of initialization, data loading and light emission of the light emitting element under the control of these control signals and data signals, and the detailed operation of the pixel circuit of each stage is as follows:
(1) initialization: the Scan control line Scan1(n) of the pixels of the nth row is given a high level, the Scan control line Scan2(n) is given a low level, and the first transistor T1, the second transistor T2 and the fifth transistor T5 are turned on accordingly; at this time, the first plate of the first capacitor C1 of the pixel circuit is set to the data voltage VDATAA first plate of the second capacitor C2 is configured as a high-level power supply voltage VDD, and a first plate of the third capacitor is configured as a low-level power supply voltage VSS; at this time, the fourth transistor T4 is turned off, and the potential at the point C is set to VSS, completing the level setting.
(2) Loading data: the Scan control line Scan1(n) of the pixels of the nth row is at a low level, Scan2(n) is at a high level, and the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned off; the Vsweep voltage starts to increase linearly from a low level to a high level, and the voltage at the first plate A of the first capacitor C1 is V due to the capacitive coupling effect of the first capacitor C1A＝VDATA+VsweepVSS, at point A the voltage has not yet reached the threshold voltage V of the third transistor T3THAt this time, the third transistor T3 is partially turned on, so that the potential at the point B is slowly lowered; at this time, when the potential at the point B is lowered to the threshold voltage V of the switching transistor T4THThe fourth transistor T4 is gradually turned on, and the voltage at the point C gradually increases; the ninth transistor T9 is gradually turned on as the potential at point C rises, thereby accelerating the discharging process of the potential at point B, forming a positive feedback loop, and accelerating the rising process of the potential at point D.
(3) The light emitting element emits light: in the data loading phase, Vba is changed from the low potential to the input constant voltage, the potential at point C is changed from the low potential to the high potential and is loaded to the gate of the sixth transistor T6, thereby turning on the sixth switching transistor, and the light emitting element, the sixth transistor T6 and the seventh transistor T7 form a path, and the second data signal VbaThe seventh transistor T7 is controlled to form a constant current in the drive loop.
Example 4
As shown in fig. 11, the general structure of the display device of the active electroluminescent display of this embodiment 4. The device is basically composed of a Pixel array section Pixel, a Scan driver Scan, and a DATA input driver DATA. The pixel array section is connected to Scan lines Scan arranged in rows, first DATA signal lines DATA arranged in columns, and second DATA signal lines, and includes a plurality of power lines and control signals for supplying a low potential power source VSS, a high potential power source VDD, a reference voltage Vref, and a control signal CV, which are required for the operation of the pixels. A first data line required for the operation of the pixel is used to control the pulse width of the PWM signal, a second data line is applied to the driving transistor for supplying a stable current to the light emitting element, a low potential power supply VSS is also used for grounding, a high potential power supply VDD is used to supply power to the pixel, a reference voltage Vref is used for a predetermined potential setting, and a control signal CV is used to separate the compensation phase and the light emitting phase. The display device of the active electroluminescent display realizes the compensation of the pulse width of the PWM signal and the compensation of the current flowing through the luminous element by multiplexing the scanning driver, improves the display uniformity of the display device and reduces the peripheral driving design of the display device.
Fig. 12 is a circuit diagram showing a pixel array section formed on the display device shown in fig. 11. Referring to fig. 12, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a first capacitor C1, a second capacitor C2, a third capacitor C3, a high potential power source VDD, a second data signal line, a low potential power source VSS, a first data signal line, a reference voltage Vref, a control signal CV, and a light emitting element. And the first transistor and the eleventh transistor are responsive to the scan control line of the (n-1) th row,the tenth, twelfth and thirteenth transistors are responsive to the scan control line of the nth row, the second transistor is responsive to the scan control line of the (n +1) th row, the fourth transistor is responsive to the scan control line of the (n +2) th row, the fourteenth, fifteenth and sixteenth transistors are responsive to the control signal CV, and the sixth transistor is responsive to the second data signal Vba。
The PWM generating circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a first capacitor C1, and a second capacitor C2: a first capacitor having a first plate connected to the gate terminal of the third transistor and the source of the first transistor and the source of the thirteenth transistor; and a second capacitor having a first plate connected to the source of the second transistor and the source terminal of the fifteenth transistor; a twelfth transistor having a gate connected to the gate of the thirteenth transistor, and a source connected to the drain of the fourteenth transistor and the source of the third transistor.
The PWM generation circuit may be further configured to charge the first capacitor with an initialization voltage during a period in which an n-1 th row SCAN control line SCAN (n-1) of the gate terminal of the first transistor is turned on, and apply a voltage charged into the first capacitor to the gate terminal of the third transistor; during a period in which the nth row scan control line sacn (n) of the gate terminals of the twelfth and thirteenth transistors is turned on, the data voltage is coupled to the first terminal of the first capacitor through the third and thirteenth transistors; when the gate terminal of the second transistor obtains the conduction period of the (n +1) th row scanning control line SCAN (n +1), the first terminal of the second capacitor is charged by power supply voltage, and the second capacitor is charged to be the same as the power supply voltage; the gate terminals of the fourteenth and fifteenth transistors are turned on by the control signal CV. And a threshold voltage compensation design can be implemented for the third transistor T3.
The shaping circuit can be composed of an inverter and a positive feedback circuit, and comprises: a third capacitor having a first plate connected to a source of the fourth transistor and a gate of the fifth transistor; a second plate having a drain connected to the sixth transistor and a gate of the ninth transistor; a gate of the sixth transistor is connected to a drain of the ninth feedback transistor.
The inverter includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a third capacitor C3. The positive feedback circuit includes a ninth transistor T9.
The shaping circuit may be further configured to charge the first terminal of the third capacitor with a power supply voltage during a period in which the (n +1) th row SCAN signal SCAN (n +1) of the gate terminal of the fourth transistor is turned on.
The PWM control module may include a seventh transistor and a sixteenth transistor, the current source module may include an eighth driving transistor operating in a saturation region, and the current control circuit may include a fourth capacitor having a first terminal connected to a source terminal of the eleventh transistor, a drain terminal of the tenth transistor, and a gate terminal of the eighth driving transistor.
The current source and the current control circuit are connected to control the current flowing in the light-emitting element together; the PWM generating circuit and the shaping circuit may be connected through the first terminal of the second capacitor and the drain of the ninth feedback transistor, and the PWM generating circuit and the shaping circuit commonly act on the gate terminal of the seventh transistor, so that the duration of the current of the light emitting element is controlled by the voltage of the first terminal of the first capacitor.
In this embodiment, the current source is an eighth transistor T8, specifically a driving transistor.
The current control circuit comprises T10, T11 and C4 functions, and threshold voltage compensation design can be carried out on the T8.
Fig. 13 is a timing diagram illustrating a detailed operation of a pixel circuit according to example embodiment 4. Specifically, fig. 13 shows main control signals (Scan control lines) Scan (n-1), Scan (n +1), and Scan (n +2) applied to the pixel circuit, CV, first, second, and Vsweep data signal lines, a reference voltage Vref, a voltage at the gate of the third transistor T3 (point a), and a voltage at the first plate of the second capacitor C2 (point B)) Voltage, voltage at the first plate of the third capacitor C3 (point C), voltage at the gate of the seventh switching transistor T7 (point D), and voltage at the gate of the eighth transistor T8 (point E), and driving current IdAccording to the change of time. The pixel circuit completes five stages of initialization, threshold voltage compensation, light emitting initialization, data loading and light emitting of the light emitting element under the control of the control signals and the data signals, and the detailed operation of the pixel circuit of each stage is as follows:
(1) initialization: the Scan control line Scan (n-1) of the (n-1) th row is given a high level, and the first transistor T1 and the eleventh transistor are turned on accordingly; the Scan control line Scan (n) of the nth row, the Scan control line Scan (n +1) of the n +1 th row, and the Scan control line Scan (n +2) of the n +2 th row are set to a low level, the control signal CV is set to a low level, and the second transistor T2, the fourth transistor T4, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor, the fifteenth transistor T15, and the sixteenth transistor are turned off; the points a and E in the pixel circuit are set to the reference voltage Vref, and the level resetting for the points a and E is completed.
(2) Threshold voltage latching stage: the Scan control line Scan (n) of the nth row is set to a high level, the Scan control line Scan (n-1) of the nth-1 row, the Scan control line Scan (n +1) of the n +1 th row and the Scan control line Scan (n +2) of the n +2 th row are set to a low level, the control signal CV is continuously set to a low level, and the tenth transistor T10, the twelfth transistor T12 and the thirteenth transistor T13 are turned on correspondingly; the first transistor T1, the second transistor T2, the fourth transistor T4, the eleventh transistor T11, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are turned off, respectively; at this time, the point A is shifted to V by the twelfth transistor T12 and the thirteenth transistor T13DATADischarging until the voltage at point A is VA＝VDATA+VTH_T3(ii) a The point E is discharged to VSS through the tenth transistor T10 and the eighth transistor T8, knowing that the voltage at the point E is VE＝VTH_T8Thereby latching the threshold voltages of the thirteenth transistor T3 and the driving transistor T8 at points a and E, respectively.
(3) Light emission initialization: the Scan control line Scan (n +1) of the (n +1) th row changes from low level to high level, the Scan control line Scan (n-1) of the (n-1) th row, the Scan control line Scan (n) of the (n) th row, and the Scan control line Scan (n +2) of the (n +2) th row give low level, the control signal CV continuously outputs low level, the second transistor is correspondingly turned on, and the first transistor T1, the fourth transistor T4, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are correspondingly turned off; the potential at the point B is configured to be the high level VDD so that the sixth transistor T6 is turned on, and the point D is configured to be the low level; subsequently, the Scan control line Scan (n +2) of the n +2 th row is changed from low level to high level, the Scan control line Scan (n-1) of the n-1 th row, the Scan control line Scan (n) of the n-1 th row, and the Scan control line Scan (n +1) of the n +1 th row output low level, so that the fourth transistor T4 is turned on, the third transistor is turned off, and the point C is configured to be high level, thereby completing the voltage configuration for the above points.
(4) The Scan control line Scan (n-1) of the n-1 th row, the Scan control line Scan (n) of the n-th row, (n +1) of the n +1 th row, and the Scan control line Scan (n +2) of the n +2 th row output a low level, the control signal CV outputs a high level, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the transistors T10 to T13 are turned off, and the fourteenth transistor T14, the fifteenth transistor T15, and the sixteenth transistor T16 are turned on; the Vsweep voltage starts to increase linearly from a low level to a high level, and the voltage at the first plate A of the first capacitor C1 is V due to the capacitive coupling effect of the first capacitor C1A＝VDATA+VTH_T3+VsweepVSS, at point A the voltage has not yet reached the threshold voltage V of the third transistor T3TH_T3At this time, the third transistor T3 is partially turned on, so that the potential at the point B is slowly lowered; at this time, when the potential at the point B is lowered to the threshold voltage V of the sixth transistor T6THThe sixth transistor T6 is gradually turned on, and the voltage at the point D gradually increases; as the potential at the point D rises, the ninth transistor T9 is gradually turned on, thereby accelerating the discharging process of the potential at the point B, forming a positive feedback loop, and accelerating the rising process of the potential at the point D; the light emitting time of the light emitting element is as follows:
Figure BDA0002935589680000151
it can be ensured that the threshold voltage shift of the third transistor T3 has no influence on the light emitting time of the light emitting element.
(5) The light emitting element emits light: in the data loading phase, the Vba is changed from the low potential to the input constant voltage, the potential at the point C is changed from the low potential to the high potential to be loaded to the gate of the seventh transistor T7, thereby turning on the seventh transistor, and the light emitting element, the sixteenth transistor T16, the seventh transistor T7 and the eighth transistor T8 form a path, and the second data signal V is turned onbaControlling and driving the eighth transistor T8 to form a constant current in the driving loop; at this time, the voltage at point E is maintained constant at Vba + VTH_T8Therefore, the light emitting element emits corresponding brightness, and the current flowing through the light emitting element is:
Figure BDA0002935589680000161
wherein, VgsIs a potential difference between the gate and the source of the eighth transistor T8, munIs the carrier mobility of the eighth transistor T8, COXW/L is the gate insulator capacitance of the eighth transistor T8, W/L is the width-to-length ratio of the driving transistor T8, VbaIs a data voltage, VthThe threshold voltage of the eighth transistor T8, VDD is the applied power supply voltage. As can be seen from the above equation, the current flowing through the light emitting element and the threshold voltage V of the eighth transistor T8th_T8The pixel circuit can keep the current flowing through the light emitting element constant in the case of the shift of the threshold voltage of the driving transistor and the light emitting element, and can ensure that the shift of the threshold voltage of the third transistor T3 has no influence on the light emitting time of the light emitting element, regardless of the on-voltage of the light emitting element.
The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.

Claims (10)

1. A pixel driving circuit for an active electroluminescent display, comprising:
a light emitting element;
a current source including a driving transistor connected to the light emitting element, the current source supplying a driving current having different amplitudes to the light emitting element according to a voltage applied to a gate terminal of the driving transistor;
the current control circuit is connected with the current source and is used for supplying voltages with different levels to the grid terminal of the driving transistor;
a PWM generating circuit for generating a PWM pulse signal for controlling the on-time of the light emitting element;
the shaping circuit is used for shaping the PWM pulse signal;
and a PWM control circuit for obtaining the duration time for controlling the driving current of the light-emitting element according to the shaped PWM pulse signal and the output voltage of the current control circuit.
2. The pixel driving circuit according to claim 1, wherein the light emitting element is a light emitting diode or an organic light emitting diode.
3. The pixel driving circuit according to claim 1, wherein the PWM generating circuit comprises a first capacitor, a second capacitor, a first transistor, a second transistor, and a third transistor; the drain electrode of the first transistor is connected with a first data signal line, the source electrode of the first transistor is connected with a first polar plate of the first capacitor, and the grid electrode of the first transistor is connected with a first scanning control line; the drain electrode of the second transistor is connected with a high-potential power supply, the source electrode of the second transistor is connected with the first pole plate of the second capacitor and the drain electrode of the third transistor, and the grid electrode of the second transistor is connected with the first scanning control line; the source electrode of the third transistor is connected with a low-potential power supply, and the grid electrode of the third transistor is connected with the first polar plate of the first capacitor; the second plate of the first capacitor is connected with a ramp signal data line; and the second plate of the second capacitor is connected with a low-potential power supply.
4. The pixel driving circuit according to claim 3,
setting the conduction time of a first transistor according to a scanning signal of the grid electrode of the first transistor, and controlling the voltage amplitude of a PWM pulse to charge the first capacitor;
setting the conduction time of a second transistor according to a scanning signal of the grid electrode of the second transistor, and controlling the voltage amplitude of a PWM pulse to charge the second capacitor;
after the first capacitors and the second capacitors of all the pixels receive data, the second data signal line starts to output a linear rising voltage signal, the linear rising voltage signal is loaded to the second plate of the first capacitor, the voltage of the second plate of the first capacitor is linearly raised through the coupling effect of the first capacitor, and the voltage reaches the threshold voltage V of the third transistorTHAt this time, the voltage of the first plate of the second capacitor is discharged through the third transistor, thereby generating the PWM pulse signal.
5. The pixel driving circuit according to claim 4, wherein the PWM shaping circuit comprises an inverter and a positive feedback circuit, one end of the positive feedback circuit is connected to the first plate of the second capacitor, the other end of the positive feedback circuit is connected to an input end of the inverter, and an output end of the inverter is connected to the PWM control circuit.
6. The pixel driving circuit according to claim 5, wherein the inverter is an N-type transistor, a P-type transistor, or a hybrid N-type and P-type integrated transistor.
7. The pixel driving circuit according to claim 3, wherein the first transistor, the second transistor, and the third transistor are all switching transistors.
8. The pixel driving circuit according to any one of claims 1 to 6, wherein the PWM control circuit includes a switching transistor having a gate connected to an output portion of the inverter of the PWM shaping circuit, a drain connected to a cathode portion of the light emitting element, and a source connected to a drain portion of the driving transistor.
9. A method of driving a pixel driving circuit of an active electroluminescent display, comprising the steps of:
(1) initialization: the scanning control line of the nth row of pixels is given a high level, the first transistor and the second transistor are correspondingly conducted, the data voltage is transmitted to the first polar plate of the first capacitor through the first transistor, and the first polar plate of the second capacitor is set to be the high level through the second transistor;
(2) a data loading stage: the scanning control line of the pixels of the nth row is at low level, and the first transistor and the second transistor are closed; the ramp signal data line starts to increase from low level to high level linearly, and the voltage of the first plate of the first capacitor is V due to the capacitive coupling effect of the first capacitorDATA+VsweepVSS, when the voltage has not yet reached the threshold voltage V of the third transistorTHWhen the first capacitor is in a first state, the third transistor is partially switched on, so that the potential of the first plate of the second capacitor is slowly reduced; at this time, when this potential is lowered to the threshold voltage of the inverter, the output voltage of the inverter gradually rises; the output voltage of the inverter reaches the threshold voltage V of the feedback transistorTHWhen the voltage of the first polar plate of the second capacitor is discharged through the feedback transistor, the discharging process of the first polar plate of the second capacitor is accelerated, a positive feedback loop is formed, and the rising process of the output potential of the phase inverter is accelerated;
(3) the light emitting element emits light: the second data signal line continuously inputs a constant voltage in all the stages; in the data loading phase, the inverter output potential is changed from a low potential to a high potential and loaded to the gate of the switching transistor of the driving circuit, so that the switching transistor is turned on, and the light emitting element, the switching transistor and the driving transistor form a path, and the second data signal line controls the driving transistor to form a constant current in the driving circuit.
10. An active light emitting display comprising the pixel driving circuit according to any one of claims 1 to 8 arranged in an array.
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