CN112921294A - Arc detector of vacuum coating pulse bias voltage membrane power supply - Google Patents
Arc detector of vacuum coating pulse bias voltage membrane power supply Download PDFInfo
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- 238000001771 vacuum deposition Methods 0.000 title claims abstract description 19
- 239000012528 membrane Substances 0.000 title claims abstract description 18
- 238000005070 sampling Methods 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 17
- 230000001629 suppression Effects 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 13
- 230000001360 synchronised effect Effects 0.000 claims description 12
- 230000000737 periodic effect Effects 0.000 claims description 10
- 230000000903 blocking effect Effects 0.000 claims description 3
- 238000000576 coating method Methods 0.000 abstract description 17
- 230000001939 inductive effect Effects 0.000 abstract description 9
- 239000011248 coating agent Substances 0.000 abstract description 7
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 230000009194 climbing Effects 0.000 abstract description 2
- 238000010891 electric arc Methods 0.000 description 8
- 238000001514 detection method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/54—Controlling or regulating the coating process
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Abstract
The invention belongs to the technical field of automatic control technology and power electronics, and particularly relates to an arc detector of a vacuum coating pulse bias voltage membrane power supply. When the power supply outputs high-frequency pulses, the arc detector continuously samples the inductance current value in the duty ratio of the output pulses of the power supply and calculates the change slope of the inductance current, so that the arc current starts to climb at the initial stage of arc generation, the controller detects the arc, then the output energy of the power supply is quickly cut off, and the arc energy is reduced. The arc detector adopts a method of directly sampling the inductive current and quickly calculating the current change rate, so that the generation of the arc can be detected at the initial stage of the arc current climbing, the power supply output can be cut off more quickly, the arc energy can be inhibited more effectively and the arc can be extinguished, and the coating quality, the product yield and the production efficiency are improved.
Description
Technical Field
The invention belongs to the technical field of automatic control technology and power electronics, and particularly relates to an arc detector of a vacuum coating pulse bias voltage membrane power supply.
Background
The technical field of vacuum coating needs a pulse bias deposition film technology in large quantity, and the load of a pulse bias power supply for vacuum coating is plasma, so that the load is easy to generate an electric arc phenomenon, the electric arc has negative influence on a coating process, the coating quality is influenced, and even a workpiece is damaged. The traditional arc judging method is to detect the arc current or the arc voltage to judge that the load generates the arc phenomenon, the lower the setting of the arc current judging threshold value is, the earlier the arc can be judged, and in addition, the higher the setting of the arc voltage judging threshold value is, the earlier the arc can be judged. However, the plasma load is not stable, and the output current of the power supply fluctuates, so that the threshold value cannot be set too low, otherwise, the arc is judged by mistake, the protection is too sensitive, and the vacuum coating process cannot be normally carried out. For the use of the same pulse bias power supply for vacuum coating, different coating processes and different process sections of the same coating process, the output currents of the pulse bias power supply are different, so that the process of detecting the occurrence of the electric arc according to the electric arc current judgment threshold value has a great problem: the method requires a worker to change the set value of the arc current judgment threshold according to the magnitude of the load current in different process stages, but under the condition that the set value of the arc current judgment threshold is higher, when the power load draws an arc, the arc current climbs to the arc current judgment threshold to detect the arc, the peak value of the arc current is higher, the energy of the arc is higher, a coated workpiece is damaged, and the quality of the coating process is fatally influenced. In addition, the output voltage of the bias power supply is different in different coating processes and different process sections of the same coating process, and the setting of the arc voltage judgment threshold value is changed along with the change, so that the operation of the bias power supply is complicated during coating. Because the lead between the power supply and the load have inductive and capacitive distribution parameters, the front edge of the pulse output by the pulse bias power supply oscillates, the threshold value for judging the arc voltage is set to be high, the arc is judged to be an arc by mistake due to over-sensitivity detection, the power supply is turned off by mistake, and the coating process is influenced. The threshold value for judging the arc voltage is set to be too low and lower than the arc voltage, and the arc can not be detected. When the pulse bias power supply outputs a low-voltage deposited film of dozens of volts, the coating voltage is close to the arc voltage, the arc voltage judgment threshold value is close to the arc voltage, the boundary between the coating voltage and the arc voltage judgment threshold value and the boundary between the coating voltage and the arc voltage judgment threshold value are not obvious. A vacuum coating power supply which can quickly and accurately detect electric arcs and does not need manual intervention of power supply electric arc management measures has a crucial influence on a coating process. In order to reduce the adverse effect of arc discharge, it is desirable to automatically determine an arc in the initial stage of arc current ramp-up so as to turn off the power supply output energy as soon as possible and reduce the risk of an arc that has already occurred.
Disclosure of Invention
The invention aims to provide an arc detector of a vacuum coating pulse bias power supply, when the power supply outputs high-frequency pulses, the arc detector continuously samples the inductance current value in the duty ratio of the output pulses of the power supply and calculates the change slope of the inductance current, so that the arc current starts to climb at the initial stage of arc generation, the controller detects the arc, and then the output energy of the power supply is quickly cut off to reduce the arc energy.
The technical scheme of the invention is as follows:
an arc detector of a vacuum coating pulse bias voltage membrane power supply comprises an arc suppression circuit, a current transformer LEM, an ADC (analog-to-digital converter) adopting circuit and a programmable logic device, wherein an internal circuit of the programmable logic device comprises a multi-pulse enabling circuit, a first register, a second register, a subtracter, a divider, a slope comparison circuit, a PWM (pulse width modulation) pulse forming circuit and an SPI (serial peripheral interface) serial register;
the arc suppression circuit is connected to the positive output end of the output high-voltage pulse forming unit of the pulse power supply, and the inductor of the arc suppression circuit is used for suppressing the maximum rising rate of the arc current;
the current transformer LEM is sleeved on an output line at one end of an inductor of the arc suppression circuit and used for inducing the magnitude of the inductive current and converting the inductive current into an isolated voltage weak current signal;
the programmable logic device controls the ADC sampling circuit to sample a voltage signal output by the current transformer LEM within the duty ratio time of a power supply PWM pulse driving signal, calculates the timely slope of current, compares the timely slope with a preset threshold value of the current slope, judges whether a load generates an electric arc or not, and blocks the power supply PWM pulse driving signal if the electric arc is generated so as to cut off a strong current output pulse of an output high-voltage pulse forming unit of the power supply;
the arc suppression circuit is formed by connecting an inductor L and at least one diode D in parallel, the positive output end of an output high-voltage pulse forming unit of the pulse power supply is connected to the cathode of the diode component, and the anode of the diode is connected to one end of the plasma load;
the current transformer LEM is sleeved on an output line at one end of an inductor of the arc suppression circuit, and a sampling signal output end of the current transformer LEM is connected with a sampling resistor in parallel to convert the inductor current into an isolated voltage signal;
the output resistance sampling signal of the current transformer LEM is connected to the analog signal input end of the ADC sampling circuit, and the ADC sampling circuit can sample the output resistance sampling signal of the current transformer LEM in due time;
a parallel Data output signal port Data, a sampling enable input signal port EN1, a chip selection input signal port CS and a read Data input signal port RD of the ADC sampling circuit are respectively connected to an I/O port of the programmable logic device, so that the programmable logic device timely controls the ADC to sample an analog input signal and read sampling Data by adopting the circuit;
the output I/O port of the programmable logic device is connected to the input end of the drive isolation circuit, the output end of the drive isolation circuit is connected to the control input end of the output high-voltage pulse forming unit of the pulse power supply, and the drive and blocking control of the power supply output pulse is realized;
the internal circuit of the programmable logic device comprises a multi-pulse enabling circuit, two first-in first-out registers connected in series, a subtracter, a divider, a slope comparison circuit, a PWM pulse forming circuit and an SPI serial port register.
A PWM pulse forming circuit in a programmable logic device outputs a driving signal of a switching tube of an output high-voltage pulse forming unit of a pulse power supply, wherein the frequency range of the driving signal is 20 kHz-100 kHz, and a synchronous signal of the driving signal of the output high-voltage pulse forming unit of the pulse power supply is also output; the pulse leading edge of the synchronous signal lags behind the driving signal leading edge of the high-voltage pulse forming unit by 500 ns-2 us, but the trailing edges are synchronous; the synchronous signal is transmitted to an input end of a multi-pulse enabling circuit in the programmable logic device, so that the multi-pulse enabling circuit starts or stops outputting a plurality of paths of enabling signals;
the multi-pulse enabling circuit in the programmable logic device also comprises a first enabling output signal, a second enabling output signal, a third enabling output signal, a fourth enabling output signal, a fifth enabling output signal, a sixth enabling output signal, a chip selection signal CS and a read enabling signal RD which are respectively used for enabling and controlling the ADC adopting circuit, the first register, the second register, the subtracter, the divider and the slope comparison circuit;
the multi-pulse enabling circuit in the programmable logic device outputs a first enabling output signal EN1 to a sampling enabling input signal end of the ADC adopting circuit, the frequency of the first enabling output signal EN1 is 1mHz, the duty ratio is 50% so as to control the sampling start and sampling period of the ADC adopting circuit, and the falling edge of the first enabling output signal EN1 starts the sampling holding function of the ADC adopting circuit;
the chip selection signal CS and the read enable signal RD output by the multi-pulse enable circuit in the programmable logic device are respectively transmitted to the ADC chip selection input end CS and the read enable input end RD of the circuit, and the falling edges of the chip selection signal CS and the read enable signal RD lag behind the falling edge of the first enable output signal by 50 ns.
The arc detector of the vacuum coating pulse bias voltage membrane power supply is characterized in that a parallel data input end of a first register is connected to a sampling data parallel output end of an ADC (analog-to-digital converter) adopting circuit, and a parallel data output end of the first register is connected to a parallel data input end of a second register.
An arc detector of a vacuum coating pulse bias voltage film power supply is characterized in that a second enable output signal EN2 of a multi-pulse enable circuit is transmitted to a shift enable input end of a first register, and a third enable output signal EN3 of the multi-pulse enable circuit is transmitted to a shift enable input end of a second register;
the second enable output signal EN2 lags the falling edge of the read enable signal RD by 30ns and the third enable output signal EN3 lags the falling edge of the read enable signal RD by 20ns, so that the data of the first register are shifted to the second register in parallel.
A first data input end of a subtracter is connected with a parallel data output end of a first register, and a second data input end of the subtracter is connected with a parallel data output end of a second register; a fourth enable output signal EN4 of the multi-pulse enable circuit is transmitted to an enable input terminal of a subtracter, a falling edge of the fourth enable output signal EN4 lags behind a falling edge of the read enable signal RD by 40ns, and the subtracter performs subtraction of the first data from the second data, and the subtraction is used as output data of the subtracter;
an arc detector of a vacuum coating pulse bias voltage membrane power supply, a parallel data input end of a dividend of a divider is connected to a parallel data output end of a subtracter, and the divisor of the divider is fixed to be 1. The fifth enable output signal EN5 of the multi-pulse enable circuit is transmitted to the enable input terminal of the divider, the falling edge of the fifth enable output signal EN5 lags behind the falling edge of the read enable signal RD by 50ns, the falling edge enables division operation, the quotient of the divider is the current change rate, and the quotient is used as the output of the divider.
An arc detector of a vacuum coating pulse bias voltage membrane power supply, a positive parallel data input end of a slope comparison circuit is connected to a parallel data output end of a quotient of a divider, a negative parallel data input end of the slope comparison circuit is connected to a parallel data output end of an SPI serial port register, and the SPI serial port register can modify negative parallel data of the slope comparison circuit;
and a sixth enabling output signal EN6 of the multi-pulse enabling circuit is transmitted to an enabling input end of the slope comparing circuit, a falling edge of the sixth enabling output signal EN6 lags behind a falling edge of the read enabling signal RD by 60ns, the falling edge enables slope comparing operation, when positive parallel data of the slope comparing circuit is larger than negative parallel data of the slope comparing circuit, the slope comparing circuit outputs a high level signal, otherwise, the slope comparing circuit outputs a low level signal.
An arc detector of a vacuum coating pulse bias voltage film power supply, wherein the turn-off enabling input end of a PWM pulse forming circuit is connected to the output end of a slope comparison circuit, a driving signal output by the PWM pulse forming circuit is connected to the input end of a driving isolation circuit, and the output end of the driving isolation circuit is connected to the input end of an output high-voltage pulse forming unit of a pulse power supply; when the slope comparison circuit outputs a high level, the driving signal output by the PWM pulse forming circuit is turned off, and the driving signal is recovered after the protection time is turned off.
An arc detector of a vacuum coating pulse bias voltage membrane power supply, the multi-pulse enable circuit comprises a periodic pulse signal generator, a delay circuit A, a delay circuit B, a delay circuit C, a delay circuit D, a delay circuit E and a delay circuit F;
the periodic pulse signal generator counts and divides the CLOCK signal CLOCK, and outputs a first enable output signal EN1, and SEN is a synchronous signal input end of the periodic pulse signal generator;
the first enable output signal EN1 is connected to the input end of the delay circuit A, and the delay circuit A outputs a chip selection signal CS and a read enable signal RD;
the read enable signal RD is connected to the input end of the delay circuit B, and the delay circuit B outputs a third enable output signal EN 3;
the third enable output signal EN3 is connected to the input terminal of the delay circuit C, and the delay circuit C outputs a second enable output signal EN 2;
the second enable output signal EN2 is connected to the input terminal of the delay circuit D, and the delay circuit D outputs a fourth enable output signal EN 4;
the fourth enable output signal EN4 is connected to the input terminal of the delay circuit E, and the delay circuit E outputs a fifth enable output signal EN 5;
the fifth enable output signal EN5 is connected to an input of the delay circuit F, which outputs a sixth enable output signal EN 6.
The invention has the beneficial effects that:
the arc detector adopts a method of directly sampling the inductive current and quickly calculating the current change rate, so that the generation of the arc can be detected at the initial stage of the arc current climbing, the power supply output can be cut off more quickly, the arc energy can be inhibited more effectively and the arc can be extinguished, and the coating quality, the product yield and the production efficiency are improved.
When the traditional arc current judgment method and the traditional arc voltage judgment method are adopted to detect the arc, a user needs to evaluate the appropriate values of the load current and the arc voltage under different coating processes, then sets the threshold value of the arc current judgment method and the threshold value of the arc voltage judgment method appropriately, and the power supply output is frequently turned off due to the fact that the arc energy is too large or the power supply misjudges that the arc is generated if the threshold values are set improperly, so that the quality of the coating process cannot be guaranteed. However, the method of directly detecting the change rate of the inductor current is adopted, so that the threshold value of arc current judgment and the threshold value of an arc voltage judgment method do not need to be set manually and frequently, and the production efficiency is improved; the method can overcome the problems of low arc detection accuracy and uncertain arc detection time caused by inaccurate setting of the manually set arc judgment threshold.
Drawings
FIG. 1 is a block diagram of the hardware system architecture of the present invention;
fig. 2 is a schematic diagram of a multi-pulse enable circuit of the present invention.
In the figure: 101. a plasma load; 102. an output high-voltage pulse forming unit of the pulse power supply; 103. the ADC adopts a circuit; 104. a drive isolation circuit; 105. a first register; 106. a second register; 107. a subtractor; 108. a divider; 109. an SPI serial port register; 110. a slope comparison circuit; 111. a PWM pulse forming circuit; 112. a multi-pulse enable circuit; 113. a programmable logic device;
201. a periodic pulse signal generator; 202. a delay circuit A; 203. a delay circuit B; 204. a delay circuit C; 205. a delay circuit D; 206. a delay circuit E; 207. a delay circuit F.
Detailed Description
The invention is described in further detail below with reference to the figures and the embodiments.
Referring to fig. 1, an embodiment of the present invention provides an arc detector of a vacuum deposition pulse bias power supply, including an arc suppression circuit, a current transformer LEM, an ADC adoption circuit 103, and a programmable logic device 113, where an internal circuit of the programmable logic device 113 includes a multi-pulse enable circuit 112, a first register 105, a second register 106, a subtractor 107, a divider 108, a slope comparison circuit 110, a PWM pulse forming circuit 111, and an SPI serial register 109.
Wherein, the arc suppression circuit is connected to the positive output end of the output high-voltage pulse forming unit 102 of the pulse power supply, and the inductance of the arc suppression circuit is used for suppressing the maximum rising rate of the arc current. The current transformer LEM is sleeved on an output line at one end of an inductor of the arc suppression circuit and used for sensing the magnitude of the inductive current and converting the inductive current into an isolated voltage weak current signal. The programmable logic device 113 controls the ADC sampling circuit 103 to sample the voltage signal output by the current transformer LEM within the duty cycle time of the power supply PWM pulse driving signal, and calculates the timely slope of the current, compares the timely slope with a preset threshold of the current slope, determines whether the load generates an arc, and blocks the power supply PWM pulse driving signal if the arc is generated, so as to turn off the strong current output pulse of the output high voltage pulse forming unit of the power supply.
The arc suppression circuit is formed by connecting an inductor L and at least one diode D in parallel. The positive output terminal of the output high voltage pulse forming unit 102 of the pulse power source is connected to the cathode of the diode assembly, and the anode of the diode is connected to one end of the plasma load 101.
The current transformer LEM is sleeved on an output line at one end of an inductor of the arc suppression circuit, and a sampling signal output end of the current transformer LEM is connected with a sampling resistor in parallel to convert inductive current into an isolated voltage signal.
The output resistance sampling signal of the current transformer LEM is connected to the analog signal input terminal of the ADC sampling circuit 103, and the ADC sampling circuit 103 can sample the output resistance sampling signal of the current transformer LEM at the right moment.
The parallel Data output signal port Data, the sampling enable input signal port EN1, the chip select input signal port CS, and the read Data input signal port RD of the ADC sampling circuit 103 are respectively connected to the I/O port of the programmable logic device 113, so that the programmable logic device 113 timely controls the ADC sampling circuit 103 to sample the analog input signal and read the sampled Data.
The output I/O port of the programmable logic device 113 is connected to the input end of the drive isolation circuit 104, the output end of the drive isolation circuit 104 is connected to the control input end of the output high-voltage pulse forming unit 102 of the pulse power supply, and the drive and blocking control of the power supply output pulse is realized.
The internal circuit of the programmable logic device 113 includes a multi-pulse enable circuit 112, two first-in first-out registers 105, 106 connected in series, a subtractor 107, a divider 108, a slope comparison circuit 110, a PWM pulse forming circuit 111, and an SPI serial register 109.
The PWM pulse forming circuit 111 in the programmable logic device 113 outputs a driving signal of the switching tube of the output high-voltage pulse forming unit 102 of the pulse power supply, the frequency range of the driving signal is 20kHz to 100kHz, and also outputs a synchronization signal of the driving signal of the output high-voltage pulse forming unit 102 of the pulse power supply. The leading edge of the synchronous signal lags behind the leading edge of the driving signal of the high-voltage pulse forming unit by 500 ns-2 us, but the trailing edges are synchronous. The synchronization signal is transmitted to an input terminal of the multi-pulse enable circuit 112 in the programmable logic device 113, so that the multi-pulse enable circuit 112 starts or stops outputting the multi-path enable signal.
The multi-pulse enable circuit 112 inside the programmable logic device 113 further includes a first, second, third, fourth, fifth, and sixth enable output signal EN1, EN2, EN3, EN4, EN5, EN6, a chip select signal CS, and a read enable signal RD for enabling the ADC using circuit 103, the first register 105, the second register 106, the subtractor 107, the divider 108, and the slope comparison circuit 110, respectively.
The multi-pulse enable circuit 112 inside the programmable logic device 113 outputs a first enable output signal EN1 to the sampling enable input signal terminal of the ADC using circuit 103, the frequency of the first enable output signal EN1 is 1mHz, the duty ratio is 50% to control the sampling start and sampling period of the ADC using circuit 103, and the falling edge of the first enable output signal EN1 starts the sampling hold function of the ADC using circuit 103.
The chip select signal CS and the read enable signal RD output by the multi-pulse enable circuit 112 in the programmable logic device 113 are respectively transmitted to the chip select input CS and the read enable input RD of the ADC using circuit 103, and the falling edges of the chip select signal CS and the read enable signal RD lag behind the falling edge of the first enable output signal by 50 ns.
The parallel data input of the first register 105 is connected to the sampled data parallel output of the ADC-employing circuit 103 and the parallel data output of the first register 105 is connected to the parallel data input of the second register 106.
The second enable output signal EN2 of the multi-pulse enable circuit 112 is transmitted to the shift enable input terminal of the first register 105, and the third enable output signal EN3 of the multi-pulse enable circuit 112 is transmitted to the shift enable input terminal of the second register 106. The second enable output signal EN2 lags the falling edge of the read enable signal RD by 30ns, and the third enable output signal EN3 lags the falling edge of the read enable signal RD by 20ns, so that the data of the first register 105 are shifted to the second register 106 in parallel.
A first data input of the subtractor 107 is connected to a parallel data output of the first register 105 and a second data input of the subtractor 107 is connected to a parallel data output of the second register 106. The fourth enable output signal EN4 of the multi-pulse enable circuit 112 is transmitted to the enable input of the subtractor 107, and the falling edge of the fourth enable output signal EN4 lags the falling edge of the read enable signal RD by 40ns, at which time the subtractor 107 performs subtraction of the first data from the second data, the difference being the output data of the subtractor 107.
The parallel data input of the dividend of divider 108 is connected to the parallel data output of subtractor 107, and the divisor of divider 108 is fixed to 1. The fifth enable output signal EN5 of the multi-pulse enable circuit 112 is transmitted to the enable input of the divider 108, the falling edge of the fifth enable output signal EN5 lags the falling edge of the read enable signal RD by 50ns, the falling edge enables the division operation, and the quotient of the divider 108 is the current change rate and is used as the output of the divider 108.
The positive parallel data input terminal of the slope comparison circuit 110 is connected to the parallel data output terminal of the quotient of the divider 108, the negative parallel data input terminal of the slope comparison circuit 110 is connected to the parallel data output terminal of the SPI serial register 109, and the SPI serial register 109 can modify the negative parallel data of the slope comparison circuit 110.
The sixth enable output signal EN6 of the multi-pulse enable circuit 112 is transmitted to the enable input terminal of the slope comparison circuit 110, the falling edge of the sixth enable output signal EN6 lags behind the falling edge of the read enable signal RD by 60ns, the falling edge enables the slope comparison operation, when the positive parallel data of the slope comparison circuit 110 is greater than the negative parallel data of the slope comparison circuit 110, the slope comparison circuit 110 outputs a high level signal, otherwise, a low level signal is output.
The off enable input terminal of the PWM pulse forming circuit 111 is connected to the output terminal of the slope comparing circuit 110, the driving signal output by the PWM pulse forming circuit 111 is connected to the input terminal of the driving isolation circuit 104, and the output terminal of the driving isolation circuit 104 is connected to the input terminal of the output high voltage pulse forming unit 102 of the pulse power supply. When the slope comparing circuit 110 outputs a high level, the driving signal output from the PWM pulse forming circuit 111 is turned off, and the driving signal is restored after the off-protection time.
The multi-pulse enable circuit 112 includes a periodic pulse signal generator 201, a delay circuit a202, a delay circuit B203, a delay circuit C204, a delay circuit D205, a delay circuit E206, and a delay circuit F207.
The periodic pulse signal generator 201 counts and divides the CLOCK signal CLOCK, and outputs a first enable output signal EN1, SEN being a synchronization signal input terminal of the periodic pulse signal generator 201.
The first enable output signal EN1 is coupled to an input of the delay circuit A202, and the delay circuit A202 outputs the chip select signal CS and the read enable signal RD.
The read enable signal RD is coupled to an input of the delay circuit B203, and the delay circuit B203 outputs a third enable output signal EN 3.
The third enable output signal EN3 is coupled to an input of the delay circuit C204, and the delay circuit C204 outputs the second enable output signal EN 2.
The second enable output signal EN2 is connected to an input of the delay circuit D205, and the delay circuit D205 outputs a fourth enable output signal EN 4.
The fourth enable output signal EN4 is coupled to an input of the delay circuit E206, and the delay circuit E206 outputs a fifth enable output signal EN 5.
The fifth enable output signal EN5 is coupled to an input of the delay circuit F207, and the delay circuit F207 outputs a sixth enable output signal EN 6.
Claims (9)
1. An arc detector of a vacuum coating pulse bias voltage membrane power supply comprises an arc suppression circuit, a current transformer LEM, an ADC (analog-to-digital converter) adopting circuit (103) and a programmable logic device (113), wherein an internal circuit of the programmable logic device (113) comprises a multi-pulse enabling circuit (112), a first register (105), a second register (106), a subtracter (107), a divider (108), a slope comparison circuit (110), a PWM (pulse width modulation) pulse forming circuit (111) and an SPI (serial port) register (109);
the method is characterized in that:
the arc suppression circuit is formed by connecting an inductor L and at least one diode D in parallel, the positive output end of an output high-voltage pulse forming unit (102) of the pulse power supply is connected to the cathode of the diode component, and the anode of the diode is connected to one end of the plasma load (101);
the current transformer LEM is sleeved on an output line at one end of an inductor of the arc suppression circuit, and a sampling signal output end of the current transformer LEM is connected with a sampling resistor in parallel to convert the inductor current into an isolated voltage signal;
the output resistance sampling signal of the current transformer LEM is connected to the analog signal input end of an ADC sampling circuit (103), and the ADC sampling circuit (103) can sample the output resistance sampling signal of the current transformer LEM in due time;
a parallel Data output signal port Data, a sampling enable input signal port EN1, a chip selection input signal port CS and a read Data input signal port RD of the ADC sampling circuit (103) are respectively connected to an I/O port of the programmable logic device (113), so that the programmable logic device (113) timely controls the ADC adopting circuit (103) to sample and sample Data to be read from an analog input signal;
the output I/O port of the programmable logic device (113) is connected to the input end of the drive isolation circuit (104), the output end of the drive isolation circuit (104) is connected to the control input end of the output high-voltage pulse forming unit (102) of the pulse power supply, and the drive and blocking control of the power supply output pulse is realized;
the internal circuit of the programmable logic device (113) comprises a multi-pulse enabling circuit (112), two first-in first-out registers (105, 106) connected in series, a subtracter (107), a divider (108), a slope comparison circuit (110), a PWM pulse forming circuit (111) and an SPI serial register (109).
2. The arc detector of a vacuum coated pulse bias voltage membrane power supply as claimed in claim 1, wherein: a PWM pulse forming circuit (111) in the programmable logic device (113) outputs a driving signal of a switching tube of an output high-voltage pulse forming unit (102) of a pulse power supply, wherein the frequency range of the driving signal is 20 kHz-100 kHz, and also outputs a synchronous signal of the driving signal of the output high-voltage pulse forming unit (102) of the pulse power supply; the pulse leading edge of the synchronous signal lags behind the driving signal leading edge of the high-voltage pulse forming unit by 500 ns-2 us, but the trailing edges are synchronous; the synchronous signal is transmitted to one input end of a multi-pulse enabling circuit (112) in the programmable logic device (113) to enable the multi-pulse enabling circuit (112) to start or stop outputting multi-path enabling signals;
the multi-pulse enabling circuit (112) in the programmable logic device (113) further comprises a first enabling output signal, a second enabling output signal, a third enabling output signal, a fourth enabling output signal, a fifth enabling output signal and a sixth enabling output signal, a chip selection signal CS and a read enabling signal RD which are respectively used for enabling and controlling the ADC adopting circuit (103), the first register (105), the second register (106), the subtracter (107), the divider (108) and the slope comparison circuit (110);
the multi-pulse enabling circuit (112) in the programmable logic device (113) outputs a first enabling output signal EN1 to a sampling enabling input signal end of the ADC adopting circuit (103), the frequency of the first enabling output signal EN1 is 1mHz, the duty ratio is 50% so as to control the sampling starting and sampling period of the ADC adopting circuit (103), and the falling edge of the first enabling output signal EN1 starts the sampling holding function of the ADC adopting circuit (103);
the chip selection signal CS and the read enable signal RD output by the multi-pulse enable circuit (112) in the programmable logic device (113) are respectively transmitted to the chip selection input end CS and the read enable input end RD of the ADC application circuit (103), and the falling edges of the chip selection signal CS and the read enable signal RD lag behind the falling edge of the first enable output signal by 50 ns.
3. The arc detector of a vacuum coated pulse bias voltage membrane power supply as claimed in claim 1, wherein: the parallel data input of the first register (105) is connected to the sampled data parallel output of the ADC employing circuit (103), and the parallel data output of the first register (105) is connected to the parallel data input of the second register (106).
4. The arc detector of a vacuum coated pulse bias voltage membrane power supply as claimed in claim 1, wherein: the second enable output signal EN2 of the multi-pulse enable circuit (112) is transmitted to the shift enable input terminal of the first register (105), and the third enable output signal EN3 of the multi-pulse enable circuit (112) is transmitted to the shift enable input terminal of the second register (106);
the second enable output signal EN2 lags the falling edge of the read enable signal RD by 30ns, and the third enable output signal EN3 lags the falling edge of the read enable signal RD by 20ns, so that the data of the first register (105) are shifted to the second register (106) in parallel.
5. The arc detector of a vacuum coated pulse bias voltage membrane power supply as claimed in claim 1, wherein: a first data input end of the subtracter (107) is connected with a parallel data output end of the first register (105), and a second data input end of the subtracter (107) is connected with a parallel data output end of the second register (106); the fourth enable output signal EN4 of the multi-pulse enable circuit (112) is transmitted to the enable input of the subtractor (107), the falling edge of the fourth enable output signal EN4 lags the falling edge of the read enable signal RD by 40ns, and at the time of the falling edge, the subtractor (107) performs the subtraction of the first data from the second data, and the difference is used as the output data of the subtractor (107).
6. The arc detector of a vacuum coated pulse bias voltage membrane power supply as claimed in claim 1, wherein: the parallel data input end of the dividend of the divider (108) is connected to the parallel data output end of the subtracter (107), and the divisor of the divider (108) is fixed to 1. The fifth enable output signal EN5 of the multi-pulse enable circuit (112) is transmitted to the enable input terminal of the divider (108), the falling edge of the fifth enable output signal EN5 lags behind the falling edge of the read enable signal RD by 50ns, the falling edge enables the division operation, and the quotient of the divider (108) is the current change rate and is used as the output of the divider (108).
7. The arc detector of a vacuum coated pulse bias voltage membrane power supply as claimed in claim 1, wherein: a positive parallel data input end of the slope comparison circuit (110) is connected to a parallel data output end of a quotient of the divider (108), a negative parallel data input end of the slope comparison circuit (110) is connected to a parallel data output end of the SPI serial port register (109), and the SPI serial port register (109) can modify negative parallel data of the slope comparison circuit (110);
the sixth enabling output signal EN6 of the multi-pulse enabling circuit (112) is transmitted to the enabling input end of the slope comparing circuit (110), the falling edge of the sixth enabling output signal EN6 lags behind the falling edge of the read enabling signal RD by 60ns, the falling edge enables the slope comparing operation, when the positive direction parallel data of the slope comparing circuit (110) is larger than the negative direction parallel data of the slope comparing circuit (110), the slope comparing circuit (110) outputs a high level signal, otherwise, the slope comparing circuit outputs a low level signal.
8. The arc detector of a vacuum coated pulse bias voltage membrane power supply as claimed in claim 1, wherein: the turn-off enabling input end of the PWM pulse forming circuit (111) is connected to the output end of the slope comparison circuit (110), the driving signal output by the PWM pulse forming circuit (111) is connected to the input end of the driving isolation circuit (104), and the output end of the driving isolation circuit (104) is connected to the input end of the output high-voltage pulse forming unit (102) of the pulse power supply; when the slope comparison circuit (110) outputs a high level, the driving signal output by the PWM pulse forming circuit (111) is turned off, and the driving signal is recovered after the protection time is turned off.
9. The arc detector of a vacuum coated pulse bias voltage membrane power supply as claimed in claim 1, wherein: the multi-pulse enabling circuit (112) comprises a periodic pulse signal generator (201), a delay circuit A (202), a delay circuit B (203), a delay circuit C (204), a delay circuit D (205), a delay circuit E (206) and a delay circuit F (207);
the periodic pulse signal generator (201) counts and divides the CLOCK signal CLOCK, and outputs a first enable output signal EN1, SEN is a synchronous signal input end of the periodic pulse signal generator (201);
the first enable output signal EN1 is connected to the input end of the delay circuit A (202), and the delay circuit A (202) outputs a chip selection signal CS and a read enable signal RD;
the read enable signal RD is connected to the input terminal of the delay circuit B (203), and the delay circuit B (203) outputs a third enable output signal EN 3;
the third enable output signal EN3 is connected to the input of the delay circuit C (204), and the delay circuit C (204) outputs the second enable output signal EN 2;
the second enable output signal EN2 is connected to the input terminal of the delay circuit D (205), and the delay circuit D (205) outputs a fourth enable output signal EN 4;
the fourth enable output signal EN4 is connected to an input terminal of the delay circuit E (206), and the delay circuit E (206) outputs a fifth enable output signal EN 5;
the fifth enable output signal EN5 is connected to the input of the delay circuit F (207), and the delay circuit F (207) outputs a sixth enable output signal EN 6.
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| CN201911236265.0A CN112921294A (en) | 2019-12-05 | 2019-12-05 | Arc detector of vacuum coating pulse bias voltage membrane power supply |
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| CN201911236265.0A CN112921294A (en) | 2019-12-05 | 2019-12-05 | Arc detector of vacuum coating pulse bias voltage membrane power supply |
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|---|---|---|---|---|
| GB1399101A (en) * | 1971-08-24 | 1975-06-25 | Welding Inst | Arc welding apparatus |
| JP2007143338A (en) * | 2005-11-21 | 2007-06-07 | Nippon Reliance Kk | Ac power supply device and arc suppression method therein |
| JP2008206372A (en) * | 2007-02-22 | 2008-09-04 | Nippon Reliance Kk | Ac power supply |
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| WO2013015556A2 (en) * | 2011-07-22 | 2013-01-31 | Lee Youn Hack | Method for detecting an abnormality of a switchgear having a self-diagnosis function |
| CN211734466U (en) * | 2019-12-05 | 2020-10-23 | 核工业西南物理研究院 | Arc detector of vacuum coating pulse bias voltage membrane power supply |
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2019
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1399101A (en) * | 1971-08-24 | 1975-06-25 | Welding Inst | Arc welding apparatus |
| JP2007143338A (en) * | 2005-11-21 | 2007-06-07 | Nippon Reliance Kk | Ac power supply device and arc suppression method therein |
| JP2008206372A (en) * | 2007-02-22 | 2008-09-04 | Nippon Reliance Kk | Ac power supply |
| WO2012177177A2 (en) * | 2011-06-20 | 2012-12-27 | Anpilov Sergej Mikhajlovich | Method for initiating an electric arc and device for the implementation thereof |
| WO2013015556A2 (en) * | 2011-07-22 | 2013-01-31 | Lee Youn Hack | Method for detecting an abnormality of a switchgear having a self-diagnosis function |
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