CN112908870A - Wafer-level fan-out type packaging method capable of eliminating chip displacement difference - Google Patents
Wafer-level fan-out type packaging method capable of eliminating chip displacement difference Download PDFInfo
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- CN112908870A CN112908870A CN202110133957.3A CN202110133957A CN112908870A CN 112908870 A CN112908870 A CN 112908870A CN 202110133957 A CN202110133957 A CN 202110133957A CN 112908870 A CN112908870 A CN 112908870A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000006073 displacement reaction Methods 0.000 title claims abstract description 15
- 239000000463 material Substances 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims description 33
- 239000011521 glass Substances 0.000 claims description 7
- 239000012790 adhesive layer Substances 0.000 claims description 5
- 239000005022 packaging material Substances 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000012858 packaging process Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000003292 glue Substances 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a wafer level fan-out type packaging method capable of eliminating chip displacement difference, which comprises the steps of firstly calculating the offset of a chip after plastic packaging corresponding to the adopted temporary slide material, plastic packaging layer material, plastic packaging temperature and room temperature, then displacing the chip to the opposite direction of the offset direction in advance for a sufficient distance and mounting on the temporary slide, then carrying out plastic packaging on the temporary slide with the chip mounted thereon, then removing the temporary slide, preparing a rewiring layer on the side surface of the plastic packaging layer exposed with chip pins through integral exposure, and finally planting balls on the rewiring layer and cutting the rewiring layer into small packages. Through the design scheme of the invention, the displacement difference generated in the plastic packaging process of the chip can be well eliminated, so that the overall exposure is carried out when the rewiring layer is manufactured, and the complicated step of local exposure caused by the displacement difference is omitted.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a wafer level fan-out type packaging method capable of eliminating chip displacement difference.
Background
Wafer level fan-out packaging is a promising advanced packaging technology, and has gained wide acceptance and great development in the industry due to its flexible SiP integration packaging capability, advantages in package miniaturization, and excellent packaging performance.
In the process flow of fan-out type packaging, in the chip mounting and plastic packaging process, many materials of different materials such as temporary carrier sheets (usually SST, glass), organic plastic packaging materials and the like are used, and along with the rise and fall of temperature, the position of the chip is often shifted after the mounting and plastic packaging are completed, that is, a large deviation is generated between the actual position of the chip and the designed position, which is called a chip shift problem (die shift), and the chip shift generates limitation on manufacturing rewiring layers in subsequent processes, thereby affecting the wiring precision and the overall packaging yield.
For the problem of chip displacement generated in the mounting and plastic packaging process of the chip, the common practice in the industry is to adopt a wafer 'regional exposure' method to solve the problem when a rewiring layer is subsequently manufactured: that is, each tiny local area on the wafer (instead of simultaneously exposing the whole wafer or sequentially exposing a larger area on the wafer) is exposed in sequence, and the adjustment is made according to the actual position of the chip in each area, so that the position of the manufactured rewiring layer can be well matched with the position of the chip. The method can correct the alignment between the chip and the rewiring layer to a certain degree, but the effect is limited (because each chip on the wafer cannot be exposed independently), but the method greatly increases the times of photoetching exposure when the rewiring layer is manufactured, greatly increases the manufacturing difficulty of the rewiring layer and reduces the efficiency, and the photoetching machine needs to be improved to well complete the tiny local distributed exposure, so that the realization difficulty and the cost are higher.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to solve the problems that in the existing packaging mode, the production cost is greatly increased and the production efficiency is reduced by adopting a regional exposure mode to avoid chip displacement.
The technical scheme is as follows: in order to solve the above problems, the present invention provides the following technical solutions:
a wafer level fan-out type packaging method capable of eliminating chip displacement difference comprises the following steps:
1) establishing a coordinate axis with the center of the wafer as the origin of coordinates, and calculating the offset of the chip after plastic package corresponding to the adopted temporary slide material, the plastic package layer material, the plastic package temperature and the room temperature;
2) coating a temporary bonding adhesive layer on the temporary slide, and on the temporary bonding adhesive layer, displacing the chip by the distance of the offset calculated in the step 1) according to the direction opposite to the offset direction, and mounting;
3) plastically packaging the temporary slide glass on which the chip is pasted;
4) then removing the temporary slide glass, and preparing a rewiring layer on the side surface of the exposed chip pin of the plastic packaging layer through integral exposure;
5) the re-wiring layer is ball-bumped and diced into small packages.
Further, in the step 1), the more distant the chip on the wafer from the origin of coordinates, the larger the offset amount after plastic packaging.
Further, in the step 1), the offset is set to be (x ', y'), and the offset start position is set to be (x ″)0，y0) The position after the offset is (x)1，y1) The following formula can be obtained:
x′＝x1-x0＝(Tm-Tr)*(CTEc-CTEm)*x0
y′＝y1-y0＝(Tm-Tr)*(CTEc-CTEm)*y0
in the above formula, Tm is the temperature at the time of plastic packaging, Tr is the room temperature, i.e., the ambient temperature, CTEc is the thermal expansion coefficient of the temporary slide, and CTEm is the thermal expansion coefficient of the plastic packaging material.
Further, in the step 3), the chip, the plastic package layer and the temporary slide are heated to the plastic package temperature together, and then cooled to the room temperature to complete the plastic package.
Further, when x' is greater than 0, x0The chip is shifted to the positive direction of the coordinate axis, and the preset position of the x axis of the chip needs to be set as x0-x ', when x' is less than 0, x0Sit toThe axis of the mark deviates in the opposite direction, and the preset position of the x axis of the chip needs to be set as x0-x′。
Has the advantages that: compared with the prior art, the invention has the advantages that:
1) the problem of chip shift (die shift) generated in the mounting and plastic packaging process of the chip is effectively solved, and the precision and the yield of fan-out type packaging are improved.
2) Because the actual position of the chip after mounting and plastic packaging is basically consistent with the original design position, the process flow of the rewiring layer to be performed after plastic packaging does not need to be changed or corrected, the complication of the process flow is avoided, and the stability and the repeatability of the whole process are ensured.
Drawings
FIG. 1 is a flow chart of a packaging method of the present invention;
FIG. 2 is a schematic diagram of a coordinate system established by the packaging method of the present invention;
FIG. 3 is a schematic diagram of a chip position before plastic encapsulation in embodiment 1;
FIG. 4 is a schematic diagram showing the positions of the chips after being molded in example 1;
FIG. 5 is a schematic diagram showing the position of a chip after the package is completed in embodiment 1;
FIG. 6 is a schematic diagram of a chip position before plastic encapsulation in embodiment 2;
FIG. 7 is a schematic diagram showing the positions of the chips after molding in example 2;
fig. 8 is a schematic diagram of a chip position after the package is completed in embodiment 2.
Detailed Description
The invention is further described below with reference to the figures and examples.
A wafer level fan-out type packaging method capable of eliminating chip displacement difference comprises the following steps:
1) establishing a coordinate axis with the center of the wafer as the origin of coordinates, and calculating the offset of the chip after plastic package corresponding to the adopted temporary slide material, the plastic package layer material, the plastic package temperature and the room temperature;
2) coating a temporary bonding glue layer 110 on the temporary slide 100, and on the temporary bonding glue layer 110, displacing the chip 120 by the distance of the offset calculated in the step 1) according to the direction opposite to the offset direction, and mounting;
3) plastically packaging the temporary slide 100 on which the chip 120 is mounted;
4) then removing the temporary slide 100, and preparing a rewiring layer 140 on the side surface of the plastic packaging layer 130, which is exposed out of the chip pins, through integral exposure;
5) the redistribution layer 140 is bumped and diced into small packages.
In the step 1), the more away from the origin of coordinates, the larger the deviation of the chips after plastic packaging on the wafer.
In step 1), the offset is set as (x ', y'), and the offset start position is set as (x)0，y0) The position after the offset is (x)1，y1) The following formula can be obtained:
x′＝x1-x0＝(Tm-Tr)*(CTEc-CTEm)*x0
y′＝y1-y0＝(Tm-Tr)*(CTEc-CTEm)*y0
in the above formula, Tm is the temperature at the time of plastic packaging, Tr is the room temperature, i.e., the ambient temperature, CTEc is the thermal expansion coefficient of the temporary slide, and CTEm is the thermal expansion coefficient of the plastic packaging material.
In step 3), the chip 120, the plastic package layer 130 and the temporary slide 100 are heated together to the plastic package temperature, and then cooled to room temperature to complete the plastic package.
When x' is greater than 0, x0The chip is shifted to the positive direction of the coordinate axis, and the preset position of the x axis of the chip needs to be set as x0-x ', when x' is less than 0, x0The direction of the X axis is deviated in the opposite direction, and the preset position of the X axis of the chip needs to be set as x0′＝x0-x′。
When y' is greater than 0, y0The chip is shifted to the positive direction of the coordinate axis, and the preset position of the y axis of the chip needs to be set as y0-y ', when y' is less than 0, y0The direction of the coordinate axis is deviated in the opposite direction, and the y-axis preset position of the chip needs to be set as y0′＝y0-y′。
Example 1
Fig. 3 to 5 show an embodiment of a fan-out package process structure and an application of the invention, in which a face-down (face down) manner is adopted to mount a chip:
as shown in fig. 3, a first chip and a second chip (both chips are indicated by 120) are first mounted on a temporary carrier 100 coated with a temporary bonding glue layer 110. Only two chips are shown for illustrating the invention, the chip on the left being referred to as the first chip and the chip on the right being referred to as the second chip. According to the fitting formula of the invention in fig. 1, the first chip and the second chip are respectively mounted at the respective corrected positions 1(x0 ', y 0') and 2(x0 ', y 0'), instead of the originally designed positions 1(x0, y0) and 2(x0, y 0);
heating the temporary slide glass with the mounted chip to the plastic packaging temperature, adding a plastic packaging material for plastic packaging, and then cooling to room temperature, wherein 130 is a plastic packaging layer as shown in fig. 4; since chip shift (die shift) occurs in the manufacturing process, the positions of the first chip and the second chip are changed from 1(x0 ', y 0') and 2(x0 ', y 0') to 1(x0, y0) and 2(x0, y0), respectively, that is, the chips can just be located at their original design positions;
then, the temporary carrier and the temporary bonding glue layer are removed, a rewiring layer 140 connected with the signal pins of the first chip and the second chip in an alignment manner is manufactured on the plastic packaging layer 130, and solder balls 150 are implanted to complete the packaging, as shown in fig. 5.
Example 2
Fig. 6 to 8 show a fan-out package process structure and application of a chip mounted in a face-up (face up) manner according to another embodiment of the present invention:
as shown in fig. 6, first, a first chip and a second chip (chips are both indicated by 120) are mounted on a temporary carrier 100 coated with a temporary bonding adhesive layer 110, and the two chips are mounted at respective corrected positions 1(x0 ', y 0') and 2(x0 ', y 0');
then, the temporary slide mounted with the chip is heated to the plastic package temperature, plastic package material is added for plastic package, then the temperature is reduced to the room temperature, and the plastic package layer is thinned to expose the pin contact on the chip, as shown in fig. 7. Since chip shift (die shift) occurs in the manufacturing process, the positions of the two illustrated chips are changed from the original positions 1(x0 ', y 0') and 2(x0 ', y 0'), respectively, to the originally designed positions 1(x0, y0) and 2(x0, y 0);
the redistribution layer 140 connected to the signal pins of the first chip and the second chip in alignment is continuously formed on the molding compound layer 130, and solder balls 150 are implanted, as shown in fig. 8. The temporary carrier 100 and the temporary bonding glue layer 110 are then removed to complete the package.
Claims (5)
1. A wafer level fan-out type packaging method capable of eliminating chip displacement difference is characterized in that: the method comprises the following steps:
1) establishing a coordinate axis with the center of the wafer as the origin of coordinates, and calculating the offset of the chip after plastic package corresponding to the adopted temporary slide material, the plastic package layer material, the plastic package temperature and the room temperature;
2) coating a temporary bonding adhesive layer on the temporary slide, and on the temporary bonding adhesive layer, displacing the chip by the distance of the offset calculated in the step 1) according to the direction opposite to the offset direction, and mounting;
3) plastically packaging the temporary slide glass on which the chip is pasted;
4) then removing the temporary slide glass, and preparing a rewiring layer on the side surface of the exposed chip pin of the plastic packaging layer through integral exposure;
5) the re-wiring layer is ball-bumped and diced into small packages.
2. The wafer level fan-out packaging method capable of eliminating chip displacement difference as claimed in claim 1, wherein: in the step 1), the more away from the origin of coordinates, the larger the deviation of the chips after plastic package is on the wafer.
3. The wafer level fan-out packaging method capable of eliminating chip displacement difference as claimed in claim 1, wherein: in the step 1), the offset is set as (x ', y'), and the offset starting position is set as (x)0，y0) The position after the offset is (x)1，y1) The following formula can be obtained:
x′＝x1-x0＝(Tm-Tr)*(CTEc-CTEm)*x0
y′＝y1-y0＝(Tm-Tr)*(CTEc-CTEm)*y0
in the above formula, Tm is the temperature at the time of plastic packaging, Tr is the room temperature, i.e., the ambient temperature, CTEc is the thermal expansion coefficient of the temporary slide, and CTEm is the thermal expansion coefficient of the plastic packaging material.
4. The wafer level fan-out packaging method capable of eliminating chip displacement difference as claimed in claim 1, wherein: in the step 3), the chip, the plastic packaging layer and the temporary slide glass are heated to the plastic packaging temperature together, and then cooled to the room temperature to complete the plastic packaging.
5. The wafer level fan-out packaging method capable of eliminating chip displacement difference as claimed in claim 3, wherein: when x' is greater than 0, x0The chip is shifted to the positive direction of the coordinate axis, and the preset position of the x axis of the chip needs to be set as x0-x ', when x' is less than 0, x0The direction of the X axis is deviated in the opposite direction, and the preset position of the X axis of the chip needs to be set as x0-x′。
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| CN202110133957.3A CN112908870B (en) | 2021-02-01 | 2021-02-01 | Wafer-level fan-out type packaging method capable of eliminating chip displacement difference |
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| CN202110133957.3A CN112908870B (en) | 2021-02-01 | 2021-02-01 | Wafer-level fan-out type packaging method capable of eliminating chip displacement difference |
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| CN112908870B CN112908870B (en) | 2023-08-18 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105428260A (en) * | 2015-12-22 | 2016-03-23 | 成都锐华光电技术有限责任公司 | Manufacturing method of carrier-based fan-out 2.5D/3D package structure |
| CN110571156A (en) * | 2019-08-01 | 2019-12-13 | 广东芯华微电子技术有限公司 | Manufacturing method of board-level fan-out type packaging fine circuit |
| CN110571159A (en) * | 2019-08-01 | 2019-12-13 | 广东芯华微电子技术有限公司 | instant self-compensation method for improving large-scale chipset positioning accuracy |
| CN110690125A (en) * | 2019-09-10 | 2020-01-14 | 广东芯华微电子技术有限公司 | FOPLP wafer integral packaging method |
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- 2021-02-01 CN CN202110133957.3A patent/CN112908870B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105428260A (en) * | 2015-12-22 | 2016-03-23 | 成都锐华光电技术有限责任公司 | Manufacturing method of carrier-based fan-out 2.5D/3D package structure |
| CN110571156A (en) * | 2019-08-01 | 2019-12-13 | 广东芯华微电子技术有限公司 | Manufacturing method of board-level fan-out type packaging fine circuit |
| CN110571159A (en) * | 2019-08-01 | 2019-12-13 | 广东芯华微电子技术有限公司 | instant self-compensation method for improving large-scale chipset positioning accuracy |
| CN110690125A (en) * | 2019-09-10 | 2020-01-14 | 广东芯华微电子技术有限公司 | FOPLP wafer integral packaging method |
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