CN112908401A - Memory repair circuit, memory module and memory repair method - Google Patents
Memory repair circuit, memory module and memory repair method Download PDFInfo
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- 230000015654 memory Effects 0.000 title claims abstract description 358
- 230000008439 repair process Effects 0.000 title claims abstract description 247
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000012360 testing method Methods 0.000 claims abstract description 64
- 238000013507 mapping Methods 0.000 claims description 15
- 230000005540 biological transmission Effects 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 abstract description 27
- 230000008901 benefit Effects 0.000 abstract description 13
- 230000006870 function Effects 0.000 abstract description 8
- 238000009825 accumulation Methods 0.000 abstract description 2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/838—Masking faults in memories by using spares or by reconfiguring using programmable devices with substitution of defective spares
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Abstract
The invention provides a memory repair circuit, a memory module and a memory repair method, wherein the memory repair circuit comprises a non-volatile storage unit, a controller, a self-test circuit and a repair information generation circuit, wherein the controller also sets a main memory and a standby memory or an embedded redundant memory according to second repair information. The invention has at least part of the advantages of both hard repair technology and soft repair technology, and can provide accumulation type repair function. In the application of electronic products with longer service life, the memory repair circuit and method and the memory module using the same can repair the memory unit with newly-appeared errors so as to ensure that the electronic products can normally operate.
Description
Technical Field
The present invention relates to a memory repair technology, and more particularly, to a memory repair circuit with an accumulation repair function, and further relates to a memory module and a memory repair method.
Background
The memory module is a necessary component of various conventional computer devices, and allows the processing unit to access data, wherein the memory module referred to herein may be a volatile memory module or a non-volatile memory module, and is not limited by the type thereof. A memory module generally includes a main memory and a redundant memory, wherein when a memory cell (memory cell) in a row or a column of the main memory has a fault (fault), the redundant memory provides a plurality of redundant memory cells in the row or the column to replace the plurality of memory cells in the faulty row or column. Briefly, redundant memory is a plurality of memory cells in a row or column that are used to repair errors.
The prior art body repair technology can be roughly divided into soft repair (soft repair) technology and hard repair (hard repair) technology. The soft repair technique combines Built-In Self-Test (BIST) with boot-up (boot up) to detect whether there are faulty memory cells by Built-In Self-Test each time the device is powered up. During testing, the addresses of all the faulty memory cells are stored separately, and an address mapping process maps the addresses of all the faulty memory cells to the addresses of the memory cells of the non-faulty redundant memory. Although the soft repair technology can perform multi-time repair (multi-time repair) and lower design overhead (low design overhead) on the erroneous memory cells of the memory module, the soft repair technology has technical problems that the repair setting time is too long and part of the potential errors cannot be repaired.
The hard repair technique uses fuses in conjunction with the write programming to open the fuses of the column or row corresponding to the faulty memory cell (e.g., using a laser or high voltage to open the fuses), and replaces the faulty column or row of memory cells with the redundant column or row of memory cells. The existing memory module mostly adopts a hard repair technology because the repair setting time is short. However, the hard repair technique has the technical problems that only one-time repair (one-time repair) can be performed on the error memory cell and extra fuses and hardware are needed.
Disclosure of Invention
The invention aims to provide a memory repair circuit, a memory module and a memory repair method, which overcome the defects of the existing hard repair technology and soft repair technology and simultaneously obtain at least part of the advantages of the existing hard repair technology and soft repair technology.
In view of the foregoing, the present invention provides a memory repair circuit, which includes: the non-volatile storage unit is used for storing first repair information;
the volatile storage unit is electrically connected with the non-volatile storage unit and is used as a data transmission bridge between the non-volatile storage unit and the repair information generation circuit;
the controller is electrically connected with the volatile storage unit, the non-volatile storage unit and the repair information generating circuit and is used for controlling the transmission, reading and writing of the first repair information and the second repair information;
the self-testing circuit is electrically connected with the main memory and the repair information generating circuit and is used for carrying out built-in self-testing on the main memory after the main memory and the standby memory or the embedded redundant memory are set according to the first repair information; and the number of the first and second groups,
the repair information generating circuit is electrically connected with the main memory, or is electrically connected with the main memory and the standby memory simultaneously and is used for generating second repair information according to the test result of the built-in self test;
the controller further sets the main memory and the standby memory or the embedded redundant memory according to the second repair information.
Optionally, the first repair information records a previous mapping relationship between an address of the erroneous at least one memory unit of the main memory and an address of the spare memory or the at least one memory unit of the embedded redundant memory, and the second repair information records a current mapping relationship between an address of the erroneous at least one memory unit of the main memory and an address of the spare memory or the at least one memory unit of the embedded redundant memory.
Optionally, the controller further controls the non-volatile storage unit to update the first repair information to the second repair information according to a user selection or a use situation.
Optionally, the self-control circuit performs the built-in self-test on the main memory according to a user selection or a use situation.
Optionally, the repair information generating circuit generates the second repair information when the test result indicates that the test is not passed.
In view of the foregoing, the present invention provides a memory module, which includes: the memory repair circuit; the main memory; and the spare memory or the embedded redundant memory.
Based on the foregoing objective, the present invention provides a memory repair method, which includes:
reading first repair information stored in the non-volatile storage unit by using the volatile storage unit when the computer is started;
setting a main memory and a standby memory or an embedded redundant memory according to the first repair information;
after the main memory and the standby memory or the embedded redundant memory are set according to the first repair information, performing built-in self-test on the main memory;
generating second repair information according to the test result of the built-in self test; and the number of the first and second groups,
and setting the main memory and the standby memory or the embedded redundant memory according to the second repair information.
Optionally, the first repair information records a previous mapping relationship between an address of the erroneous at least one memory unit of the main memory and an address of the spare memory or the at least one memory unit of the embedded redundant memory, and the second repair information records a current mapping relationship between an address of the erroneous at least one memory unit of the main memory and an address of the spare memory or the at least one memory unit of the embedded redundant memory.
Optionally, the memory repair method further includes: controlling the non-volatile storage unit to update the first repair information to the second repair information according to user selection or use situation; and determining whether to perform the built-in self test on the main memory according to the user selection or the use situation.
Optionally, the second repair information is generated when the test result indicates that the test is not passed.
In summary, the memory module, the memory repair circuit and the memory repair method of the present invention have the advantage of short set repair time of the hard repair technology, and have the advantages of repeated repair of the soft repair technology and low design overhead.
Drawings
FIG. 1 is a functional block diagram of a memory module according to an embodiment of the present invention;
FIG. 2 is a functional block diagram of a memory module according to another embodiment of the present invention;
fig. 3 is a schematic workflow diagram of a memory repair method according to an embodiment of the present invention.
Wherein, the reference numbers:
1. 1' -a memory module; 10-a memory repair circuit; 101-self test circuit; 102-a controller; 103-repair information generation circuit; 104-a non-volatile storage unit; 105-a volatile storage unit; 11. 11' -main memory; 12-standby memory; 13-embedded redundant memory.
Detailed Description
For a fuller understanding of the objects, features and advantages of the present invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings.
Embodiments of the present invention provide a memory repair circuit, method and memory module (e.g., a static memory module (SRAM module), but not limited to a static memory module) using the same, wherein the memory repair circuit, method and memory module using the same have at least a part of the advantages of both the hard repair technology and the soft repair technology, and can provide an accumulative repair function. In the application of electronic products with longer service life, the memory repair circuit and method and the memory module using the same can repair the memory unit with newly-appeared errors so as to ensure that the electronic products can normally operate.
In the embodiment of the invention, the memory repair circuit and the method can correct errors of the main memory according to the built-in self-test result of the main memory. Further, the memory repair circuit and method uses the non-volatile storage unit to store the first repair information, and uses the volatile storage unit to temporarily store the second repair information, wherein the first repair information records a previous mapping relationship between the address of the erroneous memory cell of the main memory and the address of the memory cell of the spare memory (spare memory) (i.e., the mapping relationship before the built-in self-test is performed at the time of booting), and the second repair information records a current mapping relationship between the address of the erroneous memory cell of the main memory and the address of the memory cell of the spare memory (i.e., the mapping relationship after the built-in self-test is performed at the time of booting).
When the computer is started, the first repair information stored in the non-volatile storage unit is read to the volatile storage unit, and the main memory and the standby memory are set according to the first repair information. When the main memory is subjected to built-in self test and the test result shows that a new error memory unit is detected in the main memory, the memory repair circuit and the memory repair method are set for the main memory and the standby memory to generate second repair information, and the second repair information is temporarily stored in the volatile storage unit to update the temporarily stored first repair information. Then, the first repair information stored in the non-volatile storage unit can be selected to be updated into the second repair information according to the using condition and situation. Briefly, the memory repair circuit and method provide an accumulative repair function. Incidentally, the spare memory and the main memory are independent memories, or the spare memory may be an embedded redundant memory embedded in the main memory.
Referring to fig. 1 of the present application, fig. 1 is a block diagram of a memory module according to an embodiment of the present invention. The memory module 1 of fig. 1 includes a memory repair circuit 10, a main memory 11 and a spare memory 12, wherein the memory repair circuit 10 is electrically connected to the main memory 11 and the spare memory 12. When the computer is turned on, the memory repair circuit 10 reads the first repair information stored therein, and sets the main memory 11 and the spare memory 12 according to the first repair information, so as to map the erroneous memory cells in the main memory 11 to the memory cells of the spare memory 12 recorded in the first information.
Then, if there is a built-in self test performed, and the test result indicates that a new error memory cell (i.e., an error memory cell still existing after the main memory 11 is repaired according to the first repair information) is found in the main memory 11, the memory repair circuit 10 generates second repair information according to the test result. The second repair information is temporarily stored by the memory repair circuit 10, and the memory repair circuit 10 sets the main memory 11 and the spare memory 12 according to the second repair information, so that new error memory cells in the main memory 11 can be mapped to memory cells in the spare memory 12. Then, the memory repair circuit 10 may update the first repair information to the second repair information according to the selection or usage situation of the user. In other words, the memory repair circuit 10 provides an accumulative repair function, so that it has the advantages of short repair setup time of the hard repair technique and the advantages of multiple repairs and low design overhead of the soft repair technique.
Next, the details of the memory repair circuit 10 will be further described. The memory repair circuit 10 includes a self-test circuit 101, a controller 102, a repair information generating circuit 103, a non-volatile storage unit 104 and a volatile storage unit 105, wherein the self-test circuit 101 is electrically connected to the main memory 11 and the repair information generating circuit 103, the repair information generating circuit 103 is electrically connected to the main memory 11, the controller 102 and the spare memory 12, the non-volatile storage unit 104 is electrically connected to the volatile storage unit 105 and the controller 102, and the volatile storage unit 105 is electrically connected to the controller 102.
When the computer is turned on, the controller 102 controls the non-volatile storage unit 104 to read the first repair information stored in the non-volatile storage unit 105, wherein the first repair information records a previous mapping relationship between the address of the faulty memory cell of the main memory 11 and the address of the memory cell of the standby memory 12 (i.e., the mapping relationship before the built-in self test is performed during the power-on). Then, the controller 102 sets the main memory 11 and the spare memory 12 according to the first repair information temporarily stored in the volatile storage unit 105, so that the address of the erroneous memory cell of the main memory 11 is mapped to the address of the memory cell of the spare memory 12, so that the erroneous memory cell of the main memory 11 can be repaired.
Then, the self-test circuit 101 selectively performs a built-in self-test on the main memory 11 according to the user's selection or usage scenario to check whether the main memory 11 has new faulty memory cells. If the built-in self test of the main memory 11 is not selected, the controller 102 controls the memory module 1 to operate in a normal mode. If the built-in self test of the main memory 11 is selected and no new faulty memory cell is found in the main memory 11 as a result of the test, the controller 102 controls the memory module 1 to operate in the normal mode.
If the built-in self test is selected to be performed on the main memory 11, and the test result indicates that a new faulty memory cell is found in the main memory 11, the controller 102 controls the repair information generating circuit 103 to generate the second repair information according to the test result. The controller 102 temporarily stores the second repair information in the volatile storage unit 105, and then the controller 102 sets the main memory 11 and the spare memory 12 according to the second repair information temporarily stored in the volatile storage unit 105, so that the address of the erroneous memory cell in the main memory 11 is mapped to the address of the memory cell in the spare memory 12, so that the new erroneous memory cell in the main memory 11 can be repaired. Then, the controller 102 controls the memory module 1 to operate in a normal mode. In addition, the controller 102 may also selectively control the non-volatile storage unit 104 to update the stored first repair information to the second repair information (i.e., store the second repair information instead of the first repair information) according to the selection or usage situation of the user. In brief, the controller 102 is configured to control the transfer reading and writing of the first repair information and the second repair information, and the volatile storage unit 105 is configured to serve as a data transfer bridge between the non-volatile storage unit 104 and the repair information generation circuit 103.
Referring to fig. 2, fig. 2 is a block diagram of a memory module according to another embodiment of the invention. Unlike the memory module 1 of fig. 1, the memory module 1 'of fig. 2 does not have the spare memory 12, but the main memory 11' has the embedded redundant memory 13 (which may be a redundant memory having a plurality of redundant rows and/or a plurality of redundant columns, depending on the case), and since the memory module 1 'does not have the spare memory 12, the repair information generating circuit 103 is electrically connected only to the main memory 11', the controller 102, and the self-test circuit 101. The embedded redundant memory 13 functions as the spare memory 12, and is used to replace the faulty memory cell in the main memory 11 ' to repair the faulty memory cell in the main memory 11 ', and therefore, the detailed description of the memory module 1 ' in fig. 2 is not additionally provided.
According to the above description, it can be known that the memory modules 1 and 1' and the memory repair circuit 10 in the present application integrate the non-volatile storage unit 104 and the volatile storage unit 105 to realize the accumulative repair function, so as to solve the technical problem that the set repair time of the built-in self test type is too long for each boot of the conventional soft repair technology, and the technical problem that the conventional hard repair technology requires additional hardware to perform the burning programming on the fuse. The memory modules 1 and 1' and the memory repair circuit 10 of the present disclosure have the advantages of short set repair time of the hard repair technology and the advantages of repeated repair and low design overhead of the soft repair technology. Furthermore, the memory repair circuit 10 of the present invention can support the architecture of the memory module 1 of the stand-alone spare memory 12, and also can support the architecture of the memory module 1' of the embedded redundant memory 13 having a plurality of redundant columns and/or redundant rows, and even can provide a flexible control interface and a programmable operation flow to determine whether to perform the built-in self-test and/or update the first repair information stored in the non-volatile storage unit 104 according to the selection and usage situation of the user.
Next, referring to fig. 3, fig. 3 is a flowchart of a memory repair method according to an embodiment of the invention. The memory repair method of fig. 3 may provide an accumulative repair function, and may be implemented in a memory repair circuit, such as the memory repair circuit 10 of fig. 1 and 2, but not limited thereto. First, in step S01, the electronic device with the memory module is booted. Then, in step S02, the volatile storage unit of the memory repair circuit reads the first repair information stored in the non-volatile storage unit of the memory repair circuit, and the controller of the memory repair circuit sets the main memory and the spare memory (or the embedded redundant memory) according to the first repair information, so as to map the address of the erroneous memory cell of the main memory to the address of the memory cell of the spare memory (or the embedded redundant memory).
Then, in step S03, the controller of the memory repair circuit determines whether to perform the built-in self test according to the use situation or the selection of the user. If it is determined not to perform the BIST, the step S06 is performed, and if it is determined to perform the BIST, the step S04 is performed. In step S04, the self-test circuit of the memory repair circuit performs a built-in self-test on the main memory. In step S05, the self-test circuit of the memory repair circuit determines whether the test result passes or not according to the test result. If the test is passed (i.e., the main memory does not have a new faulty cell), step S06 is performed, and if the test is not passed (i.e., the main memory does have a new faulty cell), step S07 is performed. In step S06, the controller of the memory repair circuit controls the memory module to operate in the normal mode.
In step S07, the repair information generating circuit of the memory repair circuit generates second repair information according to the test result, and the volatile storage unit of the memory repair circuit temporarily stores the second repair information, and then the controller of the memory repair circuit sets the main memory and the spare memory (or the embedded redundant memory) according to the second repair information to map the addresses of the new and old error memory units of the main memory to the addresses of the memory units of the spare memory (or the embedded redundant memory). Then, in step S08, the controller of the memory repair circuit determines whether to write the second repair information into the non-volatile storage unit according to the selection or usage situation of the user, so as to update the stored first repair information into the second repair information. If it is determined that the second repair information is not written to the non-volatile storage unit, step S09 is performed, and if it is determined that the second repair information is not written to the non-volatile storage unit, step S06 is performed. In step S09, the nonvolatile storage unit of the memory repair circuit stores the second repair information to update the stored first repair information into the second repair information.
It should be noted that the memory repair method shown in fig. 3 is only one embodiment of the invention, and is not intended to limit the invention. For example, between steps S07 and S08, a built-in self test may be additionally performed to determine whether the main memory is successfully repaired by the second repair information. Furthermore, steps S03 and/or S08 may be selectively removed, such that steps S04 and/or S09 are forcibly performed. Furthermore, the usage scenario may be a periodic inspection scenario or a maintenance scenario, and the invention is not limited thereto.
In summary, the memory repair circuit, the memory repair method and the memory module using the same according to the embodiments of the present invention are described as follows, compared to the prior art.
In the prior art, the soft repair technology has the technical problem that the repair setting time is too long, and the hard repair technology has the technical problem that additional fuses and hardware are needed.
However, the memory module, the memory repair circuit and the memory repair method integrate the non-volatile storage unit and the volatile storage unit to solve the technical problem that the set repair time of the built-in self-test type is too long when the conventional soft repair technology is started every time, and the technical problem that the conventional hard repair technology needs additional hardware equipment to perform burning programming on the fuse. Meanwhile, the memory module, the memory repair circuit and the memory repair method have the advantages of short set repair time of a hard repair technology and the advantages of repeated repair and low design overhead of a soft repair technology. Moreover, the memory module, the memory repair circuit and the memory repair method can be used for various electronic products with memories, so that the memory module, the memory repair circuit and the memory repair method have industrial utilization and huge market and economic benefits.
While the invention has been described in terms of preferred embodiments, it will be understood by those skilled in the art that the foregoing embodiments are illustrative of the invention and are not to be construed as limiting the scope of the invention. It should be noted that equivalent variations and substitutions to those of the previous embodiments are intended to be included within the scope of the present invention.
Claims (10)
1. A memory repair circuit, the memory repair circuit comprising:
the non-volatile storage unit is used for storing first repair information;
the volatile storage unit is electrically connected with the non-volatile storage unit and is used as a data transmission bridge between the non-volatile storage unit and the repair information generation circuit;
the controller is electrically connected with the volatile storage unit, the non-volatile storage unit and the repair information generating circuit and is used for controlling the transmission, reading and writing of the first repair information and the second repair information;
the self-testing circuit is electrically connected with the main memory and is used for carrying out built-in self-testing on the main memory after the main memory and the standby memory or the embedded redundant memory are set according to the first repair information; and the number of the first and second groups,
the repair information generating circuit is electrically connected with the main memory, or is electrically connected with the main memory and the standby memory simultaneously and is used for generating the second repair information according to the test result of the built-in self test;
the controller further sets the main memory and the standby memory or the embedded redundant memory according to the second repair information.
2. The memory repair circuit of claim 1, wherein the first repair information records a previous mapping relationship between the address of the erroneous at least one memory cell of the main memory and the address of the at least one memory cell of the spare memory or the embedded redundant memory, and the second repair information records a current mapping relationship between the address of the erroneous at least one memory cell of the main memory and the address of the at least one memory cell of the spare memory or the embedded redundant memory.
3. The memory repair circuit of claim 1, wherein the controller further controls the non-volatile storage unit to update the first repair information to the second repair information according to a user selection or a usage situation.
4. The memory repair circuit of claim 1, wherein the self-control circuit performs the built-in self-test on the main memory according to a user selection or a use situation.
5. The memory repair circuit of claim 1, wherein the repair information generation circuit generates the second repair information when the test result indicates a non-test pass.
6. A memory module, the memory module comprising:
the memory repair circuit of any of claims 1-5;
the main memory; and the number of the first and second groups,
the spare memory or the embedded redundant memory.
7. A memory repair method, comprising:
reading first repair information stored in the non-volatile storage unit by using the volatile storage unit when the computer is started;
setting a main memory and a standby memory or an embedded redundant memory according to the first repair information;
after the main memory and the standby memory or the embedded redundant memory are set according to the first repair information, performing built-in self-test on the main memory;
generating second repair information according to the test result of the built-in self test; and the number of the first and second groups,
and setting the main memory and the standby memory or the embedded redundant memory according to the second repair information.
8. The memory repair method according to claim 7, wherein the first repair information records a previous mapping relationship between the address of the erroneous at least one memory cell of the main memory and the address of the at least one memory cell of the spare memory or the embedded redundant memory, and the second repair information records a current mapping relationship between the address of the erroneous at least one memory cell of the main memory and the address of the at least one memory cell of the spare memory or the embedded redundant memory.
9. The memory repair method according to claim 7, further comprising:
controlling the non-volatile storage unit to update the first repair information to the second repair information according to user selection or use situation; and the number of the first and second groups,
and determining whether to perform the built-in self test on the main memory according to the user selection or the use situation.
10. The memory repair method according to claim 7, wherein the second repair information is generated when the test result indicates that the test has not passed.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113900843A (en) * | 2021-09-08 | 2022-01-07 | 联想(北京)有限公司 | Detection and repair method, device, equipment and readable storage medium |
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