CN1129071C - Tunnel transmission structure between components and transmission method - Google Patents
Tunnel transmission structure between components and transmission method Download PDFInfo
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- CN1129071C CN1129071C CN 99122055 CN99122055A CN1129071C CN 1129071 C CN1129071 C CN 1129071C CN 99122055 CN99122055 CN 99122055 CN 99122055 A CN99122055 A CN 99122055A CN 1129071 C CN1129071 C CN 1129071C
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- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
- G06F13/4269—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using a handshaking protocol, e.g. Centronics connection
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Abstract
The present invention relates to a channel transmission structure between components and a transmission method, which mainly establishes a plurality of connection channels between two elements, wherein each channel is composed of a plurality of signal lines. The differences of the operation period of a clock signal are used for determining the meaning (data, addresses or control signals) represented by the signal lines, or an address/ control line is used for defining the start, the end, the addresses and the control signals. Through the mode, each channel has the characteristics of independent running and one-way transmission of address information and data information, the configuration of the channels can be adjusted according to the actual demands so that information can be transmitted between elements in a mobile mode and the awaiting time of the elements for transmission is reduce, and thus, optimal transmission efficiency is obtained.
Description
Channel transfer structure and transmission method thereof between the relevant a kind of element of the present invention, but refer to a kind of channel transfer pattern and method that is suitable for independent operating and visual actual demand adjustment channel arrangement especially.
In traditional computer architecture, the form that is connected between element and the element is to adopt bus structure, as shown in Figure 1, traditional bus structure are as (comprising CPU, storer and peripheral unit etc. between first element 10 and second element 20, all be generally called it with element) the binding path, wherein include: 1. control bus (control bus): can send the operation of several different signals with control system, major function is to transmit control signal between CPU and peripheral unit or the storer.2. address bus (address bus): in order to the bus of selection memory address and input and output device.3. data bus (data bus): in order to the transmission data to be provided, can read or write data from CPU, storer or peripheral unit, can be two-way.
Computer is exactly by above-mentioned bus, by the setting to control bus, the data address of desiring to read is determined the address through bus, and transmits the data that read or write by data bus.But, these conventional bus have following shortcoming: have monistic feature 1., promptly after a certain transmission demand has taken a certain group of bus, other transmission demand then must it discharge after the bus entitlement by the time, can carry out, give peripheral unit and send data to give CPU simultaneously on one side can't transmit data.2. the bit width of the data/address wire of bus that present most of computer system is used (bit width) is the data line of 64 bit widths, and the bus that will be anticipated that 128 bit widths future will be a main flow.The increase of bit width promptly means the increase of integrated circuit (IC) pin count (pin count), and the pin count that is increased is considerably big.The difficulty that pin count then can cause too greatly encapsulating increases, and volume becomes the big shortcoming that waits.The pin count with system controller have the greatest impact (this is because it must be to each coupled element, individually increases corresponding pin) wherein.3. data/the address wire of parallelization can be bigger in the consumption of power when occurring switching the situation of (by 0 change 1, becoming 0 by 1) simultaneously, produces bigger undesired signal simultaneously.
Fundamental purpose of the present invention provides channel transfer structure and the transmission method thereof between a kind of element, mainly with passage (channel) as being connected between element and the element, and as the configurable unit of resource, can look to maneuverability actual demand and adjust the configuration of passage, each passage is to utilize set transmission mode to reach one group of signal wire (comprising control, address and data-signal) of effective transmission, and the present invention just provides channel transfer pattern and the method that is suitable for above-mentioned channel architecture.
Channel transmission method is achieved in that it mainly is to set up a plurality of interface channels between element between the element of the present invention, each passage is made of many signal line, and with the single signal line in the passage as clock signal and beginning, end signal, remaining signal wire is the representative data transmission line then, this clock signal and nonconforming square wave, utilize the work period relation that different cycles presented on the clock cable, the real meaning and the sequential of transmitted breath on the data line defined and extracted, address signal, data-signal, control signal also promptly distinguished.
Wherein in the one-period of this clock signal, the time of " 1 " be expressed as the transmission beginning, and be address (address) or controls (control) signal this moment when having a proper proportion greater than time of " 0 " on data line.
Wherein this proper proportion was the best with 3: 1.
Wherein in the one-period of this clock signal, the time of " 1 ", being illustrated on the data line was data-signal when being similar to the time of " 0 ".
Wherein in the one-period of this clock signal, the time of " 1 " is expressed as end of transmission (EOT) during less than time of " 0 ".
Comprising having: data latches is to be used for the information of being transmitted on the data line (comprising data, address and control signal) is latched, and the negative pulse of subject clock signal triggers the signal that latchs on the current data line; Duty detector is the work period of detecting each cycle of clock signal; The work period after the detection and the data message of data latches will be judged type by above-mentioned definition, determine address, control or the data-signal meaning of actual representative, and the element that is sent to reception is for further processing, until detect the condition of end of transmission (EOT).
The another kind of method of channel transfer is achieved in that it mainly is to set up between element that a plurality of connections are logical escapes between the element of the present invention, each passage is made of many signal line, and defining beginning, end and the transfer address signal and the control signal of transmission with an address/control (Address/Control) line in the passage, remaining data line then is used to transmit data itself; And define the sequential that latchs of data line according to the variation of signal on the A/C line, and according to the variation of data on the data line determine on the A/C line by reference the bit of information switch.
Wherein this data line latch that to trigger be the edge-triggered that is subjected to the A/C line, promptly be latching that rising edge or drop edge all can the trigger data lines.
Wherein this A/C line is to utilize beginning label to start transmission procedure, after the intact beginning label of A/C line transmission, follows each bit of transfer address information.
Wherein deserve the same situation of institute's communication of data content in two cycles, data must repeat output to represent this kind state on the A/C line.
The channel transfer structure is achieved in that and includes between the element of the present invention: a data line switch detector is that signal has no change to produce on the detection judgment data line, produces switch-over control signal when changing to data latches; One edge and beginning label detecting device have following action: detect the beginning label on the A/C line, produce address control signal to the data line switch detector, with the beginning of real valid data on the specified data line; Detect the appearance of A/C line coboundary, to produce needed edge-triggered control signal, delayed impact damper is sent to data latches, lives signal on the data line with the control data latches; Produce control signal at the beginning and decide real valid data in the data buffer; One sequence buffer is that the effective address information of composition that data latches is sent here is sent; One data buffer is begun control signal to determine real valid data in the data buffer.
A kind of preferred embodiment provided by the present invention mainly is to set up a plurality of interface channels between element, each passage is made of many signal line, in the signal wire that this passage comprised, define a signal line and represent clock signal (clock) and commencing signal, clock signal is not to be conforming square wave, can define the data type of transmitting in the data line according to the work period in each cycle (cycle) (duty cycle), and utilize a duty detector (duty cycledetector) to detect, decide the meaning of the actual representative of signal on the data line according to the detected work period, and distinguish the address, data and control signal.
The invention provides another kind of preferred embodiment, is beginning, end and transfer address and the control signal of utilizing an A/C (address/control) the line definition in the passage to transmit, and remaining signal wire is then as transmitting data itself.Can define the sequential that latchs of data line according to the variation of signal on the A/C line, according to the data variation on the data line then can determine on the A/C line the bit change of information by reference, and, detect the feature of signal on data line and the A/C line by data line switch detector (dada line switch detector) and edge and beginning label detecting device (edge and staring signature detector).
According to above-mentioned transmission mode and method, each passage promptly constitutes complete bus structure, characteristic with independent operating, one-way transmission address information and data message, can adjust the configuration of passage according to the actual requirements, make between the element can maneuverability transmission information, reduce the times to be transmitted such as element, and obtain best transfer efficiency, and help to simplify the hardware one-piece construction.
Below in conjunction with accompanying drawing structural design of the present invention and know-why are done detailed explanation:
Fig. 1 is traditional bus structure synoptic diagram;
Fig. 2 is a channel transfer system architecture synoptic diagram of the present invention;
Fig. 3 is the sequential chart of first kind of preferred embodiment of the present invention;
Fig. 4 is the receiving end block schematic diagram of Fig. 3 transmission mode;
Fig. 5 is the method flow diagram of first kind of preferred embodiment;
Fig. 6 is the sequential chart of second kind of preferred embodiment of the present invention;
Fig. 7 is the receiving end block schematic diagram of Fig. 5 transmission mode;
Fig. 8 is the method flow diagram of second kind of preferred embodiment.
As shown in Figure 2, figure can obviously find out difference between the present invention and the conventional bus thus.Be to be connected by a plurality of passages 30 between first element 10 and second element 20, each passage 30 is made of many signal line, can independent operating, in fact can be considered the data stream (localized data stream) of localization.Because the characteristic of independent operating is so can adjust the configuration of passage 30 according to the actual requirements.Shown in scheming is the example explanation: passage A, channel B and channel C are that first line (sessionl) is given in configuration, passage D and passage E then are that second line is given in configuration, wherein passage A is that the direction that is sent to second element 20 by first element 10 is given in configuration, and channel B and channel C then are that the direction that is sent to first element 10 by second element 20 is given in configuration.In other words, passage 30 is the configurable unit of resource, and for each transmission demand, each passage 30 is to utilize set transmission mode to reach one group of signal wire of effective transmission.Emphasis of the present invention just is to provide the channel transfer pattern and the method that are suitable for above-mentioned channel architecture.
Below two of explanations are actual can be applicable to channel transfer of the present invention agreement.Each passage 30 is made of many signal line, it is characterized in that one-way transmission, with transfer address information (address) and data message (data) this as the master.Below with first and second preferred embodiment this two kinds of channel transfer patterns are described respectively
First preferred embodiment:
First kind of channel transfer pattern is to represent clock letter clock with the single signal line in the passage 30, commencing signal start and end signal end, remaining signal wire (has 9 signal line explanations at present embodiment with passage, when practical application, the bar number of data line is not limited) representative data transmission line data (8 data lines are promptly arranged) then, please consult simultaneously shown in the sequential chart of Fig. 3, clock signal clock and nonconforming square wave can define the data type of transmitting among the relative data line data according to the work period in each cycle (cycle); (with positive logic) as shown in Figure 5:
(a) when in this one-period, " 1 " time＞time of " 0 " (for example works when having some cycles than ("+": "-" is 3: 1), be expressed as the transmission beginning, and be address (address) or control (control) signal this moment on data line.In the example of Fig. 3, first in transmitting on the data line data is address signal A, and second is control signal C.And data line is the judgement on address or the control signal, can be defined as follows:
1. follow closely and behind address signal, be defined as control signal (as precedent).
2. have certain proportion between address signal and the control signal, for example both period ratios are 4: 1, and cycle the greater is an address signal, and the smaller is a control signal.
(b) in this cycle, the time of the time ≈ " 0 " of " 1 " (for example work period ratio is 1: 1, error is in 25%), be illustrated in data line data this moment and go up and be data-signal, in the example of Fig. 3, the 3rd to the 7th in transmitting on the data line data is data-signal.
(c) in this cycle, " 1 " time＜during time (for example the work period ratio is 1: 3) of " 0 ", be expressed as end of transmission (EOT) end.
According to above-mentioned definition, the information that clock cable clock will transmit comprises two parts:
The beginning start of Chuan Songing, finish end.
2. data line data goes up form (data D, address A, the control C, and extract the sequential that data line data goes up signal of signal in each cycle.
In the example of Fig. 3, be negative edge (negativeedge) trigger data line data signal extraction according to clock cable clock.And in first asymmetric cycle of transmitting beginning, that data line data goes up transmission is address signal A; In second adjacent asymmetric cycle, then be to transmit control signal C on the data line, other are data-signal D for the symmetric periodic transmission, until till the end of transmission (EOT) end.
Fig. 4 represents is how receiving end in this channel transfer pattern receives the block schematic diagram with above-mentioned clock signal clock and data line data signal.Include: data latches 40 (datalatch), the information of being transmitted on the data line data (comprising data D, address A and control signal C) is latched, the negative edge of its subject clock signal clock (falling edge) triggers, when negative edge occurring on the clock signal wire clock, data latches 40 promptly can latch the signal on the present data line data.Duty detector 41 (duty cycle detector) is the work period of detecting clock signal each cycle of clock.The data message of work period after the detection and data latches 40 will be judged type by above-mentioned definition (dotted line as shown in the figure partly), determine address A, control C or the data D significance signal of actual representative, and the element that is sent to reception further processes, until detect the condition of end of transmission (EOT) end, stop above-mentioned action again.
Under above-mentioned channel transfer pattern, mainly be to utilize clock cable clock to go up the work period relation that different cycles is presented, define the upward real meaning of transmitted information of data line data, also promptly distinguish address signal A, data-signal D, control signal C.As for the data line data quantity in above-mentioned example, or in the data line data meaning that different operating was defined in the cycle, all be can change with practical situations, be not in order to limit the form that this channel transfer pattern can be implemented.
Second preferred embodiment:
In the present embodiment, be to utilize an A/C (Address/Control) line to define beginning, end and transfer address (address) signal and control (control) signal of transmission, and utilize remaining data line to transmit data itself.Please consult the sequential chart of Fig. 6 simultaneously.This channel transfer pattern mainly is: can define the sequential that latchs of data line data according to the variation of signal on the A/C line, the bit that the variation of going up data according to data line data then can determine institute's transport addresses information on the A/C line switches.Similarly, under this channel transfer pattern, the bar number (present embodiment is 8) of bar number of A/C line (present embodiment is 1) and data line data also can change.In the embodiment of Fig. 6, the trigger condition that latchs of data line data is edge-triggered (edgetriggering), also promptly is latching that rising edge or negative edge all can trigger data line 6ata, and this triggers different with negative edge in the last pattern.The A/C line be utilize the beginning label staring signature of " 1010 " start transmission procedure (as shown in Figure 8 a), and on the A/C line after having transmitted beginning label staring signature, then then be each bit (b as shown in Figure 8) of transfer address information, such as among the figure a0, a1, a2, a3, the a4... of sign.At this moment, the variation that then utilizes data line data the to go up data conversely switching that comes presentation address bit (address bits).At the same time, utilize the rising edge and the negative edge of signal on the A/C line, can allow D0, D1, D2, D3 on the data line data latch (c as shown in Figure 8).Utilize identical sequential, can continue to latch remaining data line data and go up signal.In Fig. 6, also comprised a special case, also promptly when the interior the same situation of institute's communication of data content of two cycles, as D7 among the figure and D8.Data must repeat output to represent this kind state on this moment A/C line, also second the bit a2 that promptly occurs among the figure.
Shown in Figure 7 is to be illustrated in the how block schematic diagram of the above-mentioned sequential of decipher of receiving end under this channel transfer pattern.As above-mentioned, in this channel transfer pattern, having three kinds of states needs to detect, also promptly: 1. Chuan Shu beginning (or end); 2. latching of signal can be gone up as data line data in the edge of signal (comprising rising edge or negative edge) on the A/C line; 3. the data itself that transmitted on the data line data change, and can be used for expressing the bit change of signal on the A/C line.Structure shown in Figure 7, include: a data line switch detector 50 (data lines switch detector), be to detect the last signal of judgment data line data to have no change to produce, produce switch-over control signal 501 (switching control) when changing, be sent to data latches 52 (data latch) through the buffering of a delay buffer 51 (delay buffer).One edge and beginning label detecting device 53 (edgeand starting signature detector) have following action:
1. detect the beginning label starting signature on the A/C line, produce address control signal 531 (address control), go up the beginning of real valid data with specified data line data to data line switch detector 50.
2. detect appearance at A/C line coboundary, to produce needed edge-triggered control signal 532 (edge-triggering control), delayed impact damper 54 is sent to data latches 55, latchs signal on the data line data with control data latch 55.
3. produce control signal 533 (starting control) at the beginning and decide real valid data in data buffer 56.One sequence buffer 57 (serial buffer) is that the effective address information of composition that data latches 52 is sent here is sent.One data buffer 56 (databuffer), it is begun control signal 533 and is determined real valid data in data buffer 56.
This edge and beginning label detecting device 53 detect the beginning label (" 1010 " as the aforementioned) on the A/C line, and specified data line data goes up the beginning of real valid data.Simultaneously, edge and beginning label detecting device 53 also can detect the appearance at A/C line coboundary, produce needed edge-triggered control signal after 54 certain delays of 532 process delay buffers, control data latch 55 latchs the signal on the data line data, 55 latched data of data latches can all be delivered in the data buffer 56, are sent by the real valid data that beginning control signal 533 decides in data buffer 56.On the other hand, the A/C line is sent address information subsequently, because the A/C line is single signal wire, therefore address information is to send in regular turn in the mode of single bit, this edge and beginning label detecting device 53 will be sent address control signal 531 to data line switch detector 50, can begin each bit in the receiver address information in regular turn in order to designation data line switch detector 50, when data line data goes up the signal variation, promptly send switch-over control signal 501 to data latches 52, receive the bit on the present A/C line, the bit that is received will be delivered on the sequence buffer 57 in regular turn, send up to forming effective address information.
In this channel transfer pattern, be to utilize the mutual reference of A/C line and data line data to carry out data latching, on the A/C line, be responsible for indication beginning and the end sequential, utilize the edge of A/C line to come trigger data line data to go up latching of signal, and latching of address information bit on the A/C line carried out in the variation that utilizes data line data to go up data.Similarly, the structure of the specified conditions in this preferred embodiment and non-limiting this channel transfer pattern.
In sum, channel transfer structure and transmission method thereof between the element provided by the present invention, can come transfer address/data by a plurality of passages and defined channel transfer pattern, and can reach the optimization of data transmission according to the data traffic demand of reality.
Claims (11)
1, channel transmission method between a kind of element, it is characterized in that: between element, set up a plurality of interface channels, each passage is made of many signal line, and with single signal line transmit clock signal and the beginning in the passage, end signal, remaining signal wire is the representative data transmission line then, this clock signal and nonconforming square wave, utilize the time of " 1 " in one-period of clock signal and the scale of " 0 " to define and distinguish address signal, control signal and data-signal, and from the above-mentioned address signal of described data line extraction, control signal and data-signal.
2, the channel transmission method between the element as claimed in claim 1, it is characterized in that: wherein in the one-period of this clock signal, the time of " 1 " be expressed as the transmission beginning, and is address or control signal this moment when having a proper proportion greater than time of " 0 " on data line.
3, the channel transmission method between the element as claimed in claim 2 is characterized in that: wherein this proper proportion was the best with 3: 1.
4, the channel transmission method between the element as claimed in claim 1 is characterized in that: wherein in the one-period of this clock signal, the time of " 1 ", being illustrated on the data line was data-signal when being similar to the time of " 0 ".
5, the channel transmission method between the element as claimed in claim 1 is characterized in that: wherein in the one-period of this clock signal, the time of " 1 " is expressed as end of transmission (EOT) during less than time of " 0 ".
6, the channel transfer structure between a kind of element, it is characterized in that including: a plurality of interface channels of setting up between the element, each passage is made of many signal line, and with the single signal line transmit clock signal in the passage and beginning, end signal, remaining signal wire is the representative data transmission line then; Data latches is used for the information of being transmitted on the data line (comprising data, address and control signal) is latched, and the negative edge of subject clock signal triggers the signal that latchs on the current data line; Duty detector is the work period of detecting each cycle of clock signal; The work period after the detection and the data message of data latches will be judged type by predefined judgment rule, the address, control or the data-signal meaning that determine actual representative are sent to the element do processing further of reception, until detect the condition of end of transmission (EOT).
7, the channel transmission method between a kind of element, it is characterized in that: mainly be between element, to set up a plurality of interface channels, each passage is made of many signal line, and defining beginning, end and the transfer address signal and the control signal of transmission with an address in the passage/control A/C (Address/Control) line, remaining data line then is used for transmission itself; And define the sequential that latchs of data line according to the variation of signal on the A/C line, and according to the variation of data on the data line determine on the A/C line by reference the bit of information switch.
8, the channel transmission method between the element as claimed in claim 7 is characterized in that: wherein this data line latch that to trigger be the edge-triggered that is subjected to the A/C line, promptly be latching that rising edge or drop edge all can the trigger data lines.
9, the channel transmission method between the element as claimed in claim 7 is characterized in that: wherein this A/C line is to utilize beginning label to start transmission procedure, after the intact beginning label of A/C line transmission, follows each bit of transfer address information.
10, the channel transmission method between the element as claimed in claim 7 is characterized in that: wherein deserve the same situation of institute's communication of data content in two cycles, data must repeat output to represent this kind state on the A/C line.
11, the channel transfer structure between a kind of element, it is characterized in that including: a plurality of interface channels of setting up between the element, each passage is made of many signal line, and with the single signal line transmit clock signal in the passage and beginning, end signal, remaining signal wire is the representative data transmission line then; One data line switch detector, signal has no change to produce on the judgment data line in order to detect, and produces switch-over control signal when changing to data latches; One edge and beginning label detecting device in order to detect the beginning label on the A/C line, produce address control signal to the data line switch detector, with the beginning of real valid data on the specified data line; Detect the appearance of A/C line coboundary, to produce needed edge-triggered control signal, delayed impact damper is sent to data latches, lives signal on the data line with the control data latches, produces control signal at the beginning and decides real valid data in data buffer; One sequence buffer is sent in order to the effective address information of the composition that data latches is sent here; One data buffer is begun control signal to determine real valid data in data buffer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 99122055 CN1129071C (en) | 1999-10-27 | 1999-10-27 | Tunnel transmission structure between components and transmission method |
| GB0025563A GB2362735B (en) | 1999-10-27 | 2000-10-18 | Framework and method for inter-element channel transmission |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 99122055 CN1129071C (en) | 1999-10-27 | 1999-10-27 | Tunnel transmission structure between components and transmission method |
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| Publication Number | Publication Date |
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| CN1247342A CN1247342A (en) | 2000-03-15 |
| CN1129071C true CN1129071C (en) | 2003-11-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 99122055 Expired - Fee Related CN1129071C (en) | 1999-10-27 | 1999-10-27 | Tunnel transmission structure between components and transmission method |
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| Country | Link |
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| CN (1) | CN1129071C (en) |
| GB (1) | GB2362735B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101390066B (en) * | 2006-02-24 | 2014-08-13 | 高通股份有限公司 | Auxiliary writes over address channel |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7209998B2 (en) * | 2004-02-04 | 2007-04-24 | Qualcomm Incorporated | Scalable bus structure |
| US7617343B2 (en) | 2005-03-02 | 2009-11-10 | Qualcomm Incorporated | Scalable bus structure |
| US8107492B2 (en) * | 2006-02-24 | 2012-01-31 | Qualcomm Incorporated | Cooperative writes over the address channel of a bus |
| US8108563B2 (en) * | 2006-02-24 | 2012-01-31 | Qualcomm Incorporated | Auxiliary writes over address channel |
| DE102006059962A1 (en) | 2006-12-19 | 2008-06-26 | GM Global Technology Operations, Inc., Detroit | Bending device and method for folding workpieces |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6209053B1 (en) * | 1998-08-28 | 2001-03-27 | Intel Corporation | Method and apparatus for operating an adaptive multiplexed address and data bus within a computer system |
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1999
- 1999-10-27 CN CN 99122055 patent/CN1129071C/en not_active Expired - Fee Related
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2000
- 2000-10-18 GB GB0025563A patent/GB2362735B/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101390066B (en) * | 2006-02-24 | 2014-08-13 | 高通股份有限公司 | Auxiliary writes over address channel |
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| Publication number | Publication date |
|---|---|
| GB2362735A (en) | 2001-11-28 |
| GB2362735B (en) | 2003-04-02 |
| CN1247342A (en) | 2000-03-15 |
| GB0025563D0 (en) | 2000-12-06 |
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