CN112906332A - Comprehensive implementation method and device for FPGA (field programmable Gate array) design - Google Patents
Comprehensive implementation method and device for FPGA (field programmable Gate array) design Download PDFInfo
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Abstract
The application provides a comprehensive implementation method and a device for FPGA design, and the method comprises the following steps: acquiring a register chain group in FPGA design, wherein the register chain group comprises at least one register chain, the register chain is formed by connecting a plurality of registers in series, control signals of the plurality of registers are the same, and the plurality of registers are all synchronous registers or asynchronous registers; determining a target memory corresponding to the target register chain group; and replacing the corresponding target register chain group by using the target memory to obtain the updated FPGA design. The method ensures that fewer nodes are arranged in the updated FPGA design, thereby ensuring that fewer chip resources are occupied and solving the problem that the FPGA design occupies more chip resources in the comprehensive stage in the prior art.
Description
Technical Field
The application relates to the field of semiconductors, in particular to a comprehensive implementation method and device for FPGA design, a computer readable storage medium, a processor and electronic equipment.
Background
As a general Programmable logic device, an FPGA (Field Programmable Gate Array) is designed to be closer to a hardware bottom architecture, has a large number of storage resources, DSP (Digital Signal Processing) resources, and the like, and has the characteristics of excellence in data parallel computation, flexibility, and low delay, and meanwhile, the FPGA also has the characteristics of low power consumption, programmability, flexible design, and the like, so the FPGA is widely used in many fields.
In the FPGA development process, a user needs to synthesize a Hardware design Circuit written in Verilog HDL (Hardware Description Language) or VHDL (Very-High-Speed-Integrated Circuit Hardware Description Language) Language to complete the conversion from the Hardware design Circuit to the netlist. Along with the development of the FPGA industry, the scale of user design becomes larger and larger, and due to the improvement of the scale of the user design, the integrated circuit occupies more and more chip resources, so that the overall performance of the chip is influenced, the situation of layout failure is caused, and the layout and wiring are not facilitated.
Therefore, how to optimize the circuit to reduce the occupation of chip resources is a problem that needs to be solved in the prior art.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The present application mainly aims to provide a comprehensive implementation method and apparatus for FPGA design, a computer-readable storage medium, a processor, and an electronic device, so as to solve the problem that the FPGA design occupies more chip resources in the comprehensive stage in the prior art.
According to an aspect of the embodiments of the present invention, a method for comprehensively implementing an FPGA design is provided, which includes: acquiring a register chain group in FPGA design, wherein the register chain group comprises at least one register chain, the register chain is formed by connecting a plurality of registers in series, control signals of the plurality of registers are the same, and the plurality of registers are all synchronous registers or asynchronous registers; determining a target memory corresponding to the target register chain group; and replacing the corresponding target register chain group by using the target memory to obtain the updated FPGA design.
Optionally, obtaining a register chain set in the FPGA design includes: acquiring a target register in the FPGA design; and traversing the FPGA design according to the target register to determine the register chain group.
Optionally, traversing the FPGA design according to the target register to determine the register chain group includes: and traversing the FPGA design along a first direction and a second direction respectively by taking the target register as an initial position to determine the register chain, wherein the register chain is the register chain group, the first direction is the extension direction of the input end of the target register, the second direction is the extension direction of the output end of the target register, and the first direction is opposite to the second direction.
Optionally, traversing the FPGA design according to the target register to determine the register chain group includes: traversing the FPGA design along a first direction and a second direction respectively by taking the target register as an initial position to determine a plurality of register chains, wherein the capacities and the types of the plurality of register chains are the same, the first direction is the extension direction of the input end of the target register, the second direction is the extension direction of the output end of the target register, and the first direction is opposite to the second direction; and combining the plurality of register chains to obtain the register chain group.
Optionally, determining a target memory corresponding to the target register chain group includes: determining an input end, an output end, a write enable end and an initial value of the corresponding target memory according to the target register chain group; and constructing an address bus of the corresponding target memory according to the target register chain group.
Optionally, constructing an address bus of the corresponding target memory according to the target register chain group includes: acquiring the depth of a target register chain in the target register chain group; determining the width of the address bus according to the depth of the target register chain; constructing a counter according to the width of the address bus; and determining the output end of the counter as the address bus.
Optionally, determining an input end, an output end, a write enable end, and an initial value of the corresponding target memory according to the target register chain group includes: determining an input end of a target register chain in the target register chain group as an input end of the target memory; determining an output end of the target register chain as an output end of the target memory; determining enabling ends of a plurality of registers in the target register chain group as writing enabling ends of the target memory; acquiring initial values of a plurality of registers in the target register chain group; and determining the initial value of the target memory according to the initial values of the plurality of registers.
Optionally, determining an initial value of the target memory according to initial values of a plurality of the registers includes: determining the arrangement sequence of the initial values of the registers according to the structure information of the target register chain group to obtain an initial value array, wherein the structure information at least comprises the serial connection sequence of the target register chain; and determining the initial value array as the initial value of the target memory.
Optionally, in a case that the target register chain group includes a plurality of target register chains, the structure information further includes a correspondence between an input end of each of the target register chains and an input end of the target memory.
Optionally, after determining the arrangement order of the initial values of the plurality of registers according to the structure information of the target register chain group, before determining that the initial value array is the initial value of the target memory, the method further includes: determining whether a capacity of the target memory is greater than a capacity of the target chain set of registers; determining a missing bit of the initial value array if the capacity of the target memory is greater than the capacity of the target register chain group, the missing bit being a position where the target register chain group lacks the initial value compared to the target memory; and taking a preset numerical value as an initial value of the missing bit to obtain the updated initial value array.
According to another aspect of the embodiments of the present invention, there is also provided a comprehensive implementation apparatus for FPGA design, including an obtaining unit, a first determining unit, and a replacing unit, where the obtaining unit is configured to obtain a target register chain group in the FPGA design, the target register chain group includes at least one register chain, the register chain is formed by connecting a plurality of registers in series, control signals of the plurality of registers are the same, and the plurality of registers are all synchronous registers or asynchronous registers; the first determining unit is used for determining a target memory corresponding to the target register chain group; and the replacing unit is used for replacing the corresponding target register chain group by using the target memory to obtain the updated FPGA design.
According to another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium including a stored program, wherein the program executes any one of the methods.
According to another aspect of the embodiments of the present invention, there is also provided a processor, configured to execute a program, where the program executes any one of the methods.
According to another aspect of the embodiments of the present invention, there is also provided an electronic device, including: one or more processors, memory, and one or more programs stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for performing any of the methods described herein.
The comprehensive implementation method of the FPGA design includes the steps that firstly, a register chain group in the FPGA design is obtained, the register chain group at least comprises one register chain, namely the register chain group can comprise one register chain and also comprises a plurality of register chains, and one register chain comprises a plurality of registers which are connected in series; then determining a target memory corresponding to a target register chain group, wherein the register chain group comprises the target register chain group; and finally, replacing the corresponding target register chain group by using the target memory to obtain the updated FPGA design. According to the method, the target storage is used for replacing the corresponding target register chain group in the FPGA design, namely one target storage is used for replacing a plurality of corresponding registers in the FPGA design, and the number of nodes corresponding to the target storage is less than that of the nodes corresponding to the registers, so that the number of the nodes in the updated FPGA design is less, the occupied area of a chip is less, the chip resource is less, and the problem that the FPGA design occupies more chip resources in the comprehensive stage in the prior art is solved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 shows a schematic flow diagram generated by a comprehensive implementation method of an FPGA design according to an embodiment of the present application;
FIG. 2 illustrates a flow diagram of a method for comprehensive implementation of an FPGA design in accordance with a particular embodiment of the present application;
FIG. 3 shows a schematic diagram of an integrated implementation of an FPGA design, according to an embodiment of the present application;
FIG. 4 illustrates a schematic diagram of traversing a set of determined register chains, according to an embodiment of the present application;
FIG. 5 is a flow diagram illustrating the determination of ports of a corresponding memory from a chain of registers according to a specific embodiment of the present application.
Wherein the figures include the following reference numerals:
100. a target register; 200. a chain of registers.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As mentioned in the background art, in order to solve the above problem, a typical embodiment of the present application provides a comprehensive implementation method and apparatus for FPGA design, a computer-readable storage medium, a processor, and an electronic device.
According to the embodiment of the application, a comprehensive implementation method for FPGA design is provided.
FIG. 1 is a flowchart of a comprehensive implementation method of an FPGA design according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:
step S101, a register chain group in FPGA design is obtained, the register chain group comprises at least one register chain, the register chain is formed by connecting a plurality of registers in series, control signals of the plurality of registers are the same, and the plurality of registers are all synchronous registers or asynchronous registers;
step S102, determining a target memory corresponding to the target register chain group;
and step S103, replacing the corresponding target register chain group by using the target memory to obtain the updated FPGA design.
Firstly, acquiring a register chain group in the FPGA design, wherein the register chain group at least comprises one register chain, namely the register chain group can comprise one register chain and also comprises a plurality of register chains, and one register chain comprises a plurality of registers connected in series; then determining a target memory corresponding to a target register chain group, wherein the register chain group comprises the target register chain group; and finally, replacing the corresponding target register chain group by using the target memory to obtain the updated FPGA design. In the method, the target memory is used for replacing the corresponding target register chain group in the FPGA design, namely one target memory is used for replacing a plurality of corresponding registers in the FPGA design, and the number of nodes corresponding to one target memory is less than that of the nodes corresponding to the registers, so that the number of the nodes in the updated FPGA design is less, the occupied area of a chip is less, the chip resource is less, and the problem that the FPGA design occupies more chip resources in the comprehensive stage in the prior art is solved.
In practical application, data input or output of the memory is in a bus form, so that register chains with the same length and the same type can be combined into register chain groups, and the register chain groups are mapped into the memory.
According to a specific embodiment of the present application, acquiring a register chain group in an FPGA design includes: acquiring a target register in the FPGA design; and traversing the FPGA design according to the target register to determine the register chain group. Through the target register, the FPGA design is traversed to obtain the register chain group, so that all the register chain groups in the FPGA design can be found quickly and accurately, and at least part of the register chain groups in the register chain groups can be replaced by corresponding memories conveniently in the follow-up process.
In order to further ensure that all register chain groups in the FPGA design can be found more quickly and accurately, according to another specific embodiment of the present application, as shown in fig. 4, when the register chain group includes one register chain, traversing the FPGA design according to the target register 100 to determine the register chain group includes: the FPGA design is traversed along a first direction and a second direction respectively with the target register 100 as a start position to determine the register chain 200, the register chain 200 is the register chain group, the first direction is an extension direction of an input end of the target register 100, the second direction is an extension direction of an output end of the target register 100, and the first direction and the second direction are opposite.
According to another specific embodiment of the present application, in a case that the register chain group includes a plurality of register chains, traversing the FPGA design according to the target register to determine the register chain group includes: traversing the FPGA design along a first direction and a second direction respectively by taking the target register as a starting position to determine a plurality of register chains, wherein the capacity and the type of the plurality of register chains are the same, the first direction is the extending direction of the input end of the target register, the second direction is the extending direction of the output end of the target register, and the first direction and the second direction are opposite; and combining a plurality of the register chains to obtain the register chain group. Therefore, all register chain groups in the FPGA design can be found more quickly and accurately.
In a specific embodiment of the present application, a target register in the FPGA design is determined, an output pin of the target register traverses the search register backward until reaching a chain end of the register, and then the input pin of the target register traverses the search register forward until reaching a chain head of the register, and the chain head and the chain end of the register are recorded. It is sufficient that all register control signals in this chain are identical and are synchronous or asynchronous during traversal. And circulating the steps until all the register chains in the FPGA design are found, and recording the input and output of the register chains and the length of the register chains.
In another specific embodiment of the present application, determining a target memory corresponding to a target register chain group includes: determining an input end, an output end, a write enable end and an initial value of the corresponding target memory according to the target register chain group; and constructing an address bus of the corresponding target memory according to the target register chain group. According to the method, the input end, the output end, the write enable end and the initial value of the corresponding target memory are determined according to the target register chain group, and the address bus of the corresponding target memory is constructed, so that the target memory is conveniently used for replacing the corresponding target register chain group subsequently, the number of nodes in the updated FPGA design is further ensured to be less, and the occupied chip resources are further ensured to be less.
In order to establish an address bus of the target memory more easily, and further facilitate subsequent replacement of the corresponding target register chain set with the target memory, in another specific embodiment of the present application, the establishing an address bus of the corresponding target memory according to the target register chain set includes: acquiring the depth of a target register chain in the target register chain group; determining the width of the address bus according to the depth of the target register chain; constructing a counter according to the width of the address bus; and determining the output end of the counter as the address bus.
In an actual application process, the counter can be constructed by using a primitive with an addition function on the design of the FPGA, and can also be constructed by using other logic primitives. The address bit width of the target memory is log2 depthRounded up, depth is the depth of the corresponding target register chain set, e.g. 16 for a target register chain set, then 4 for the address width of the corresponding target memory, and 5 for a target register chain set of 17 for the address width of the corresponding target memory.
In order to further facilitate the subsequent replacement of the corresponding target register chain group by the target memory, thereby further ensuring that there are fewer nodes in the updated FPGA design, according to yet another specific embodiment of the present application, as shown in fig. 5, determining an input terminal, an output terminal, a write enable terminal, and an initial value of the corresponding target memory according to the target register chain group includes the following steps:
step S201, determining the input end of the target register chain in the target register chain group as the input end of the target memory;
step S202, determining the output end of the target register chain as the output end of the target memory;
step S203, determining the enable terminals of a plurality of registers in the target register chain group as the write enable terminals of the target memory;
step S204, obtaining the initial values of a plurality of registers in the target register chain group;
in step S205, the initial value of the target memory is determined according to the initial values of the plurality of registers.
In an actual application process, determining an initial value of the target memory according to initial values of a plurality of registers includes: determining the arrangement sequence of the initial values of a plurality of registers according to the structure information of the target register chain group to obtain an initial value array, wherein the structure information at least comprises the serial sequence of the target register chain; and determining the initial value array as the initial value of the target memory. According to the method, the initial value of the corresponding target memory can be determined simply and quickly through the serial connection sequence of the target register chain.
According to another specific embodiment of the present application, in a case that the target register chain group includes a plurality of target register chains, the configuration information further includes a correspondence relationship between an input terminal of each of the target register chains and an input terminal of the target memory. When the target register chain group includes a plurality of target register chains, the initial value of the target memory is determined based on the serial order of the target register chains and the correspondence between the input terminals of the target register chains and the input terminals of the target memory.
In an actual application process, in order to further ensure that the target memory can be used to replace the corresponding target register chain group, in a case that the capacity of the target register chain group is smaller than the capacity of the corresponding target memory, in yet another specific embodiment of the present application, after determining an arrangement order of initial values of a plurality of registers according to the structure information of the target register chain group, before determining the initial value array as the initial value of the target memory, the method further includes: determining whether the size of the target memory is larger than the size of the target register chain group; determining a missing bit of the initial value array when the capacity of the target memory is larger than the capacity of the target register chain group, the missing bit being a position where the target register chain group is less than the target memory by the initial value; and taking a preset value as an initial value of the missing bit to obtain an updated initial value array.
In a specific embodiment, when the capacity of the target register chain group does not satisfy the capacity of the corresponding target memory, the initial value of the missing bit is all complemented by 0.
FIG. 2 is a flowchart generated by a comprehensive implementation method of FPGA design according to the present application. As can be seen from fig. 2, first all register chains in the FPGA design are found, then the same register chains are merged into a register chain group, then input/output signals and initial values of corresponding memories are constructed on the basis of the register chain group, and finally all corresponding register chain groups in the FPGA design are replaced with the memories, and the corresponding register chain groups are deleted, so as to obtain an updated FPGA design.
It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer-executable instructions and that, although a logical order is illustrated in the flowcharts, in some cases, the steps illustrated or described may be performed in an order different than presented herein.
The embodiment of the present application further provides a comprehensive implementation device for FPGA design, and it should be noted that the comprehensive implementation device for FPGA design of the embodiment of the present application may be used to execute the comprehensive implementation method for FPGA design provided in the embodiment of the present application. The comprehensive implementation device for the FPGA design provided by the embodiment of the present application is introduced below.
FIG. 3 is a schematic diagram of an integrated implementation apparatus of an FPGA design according to an embodiment of the present application. As shown in fig. 3, the apparatus includes an obtaining unit 10, a first determining unit 20, and a replacing unit 30, where the obtaining unit 10 is configured to obtain a target register chain group in an FPGA design, where the target register chain group includes at least one register chain, the register chain is formed by serially connecting a plurality of registers, control signals of the plurality of registers are the same, and the plurality of registers are all synchronous registers or asynchronous registers; the first determining unit 20 is configured to determine a target memory corresponding to the target register chain group; the replacing unit 30 is configured to replace the corresponding target register chain group with the target memory, so as to obtain an updated FPGA design.
The comprehensive implementation device for the FPGA design obtains a register chain group in the FPGA design through the obtaining unit, where the register chain group includes at least one register chain, that is, the register chain group may include one register chain and may also include a plurality of register chains, and one register chain includes a plurality of registers connected in series; determining a target memory corresponding to a target register chain group by the first determining unit, wherein the register chain group comprises the target register chain group; and replacing the corresponding target register chain group by using the target memory through the replacing unit to obtain the updated FPGA design. In the above-mentioned device of this application, through using the target memory to replace the corresponding target register chain group in the FPGA design, even if used a target memory to replace a plurality of registers that correspond in the FPGA design, because the node quantity that a target memory corresponds is less than the node quantity that a plurality of registers correspond, guaranteed like this that the node in the FPGA design after the update is less, thereby guaranteed that the area occupied of chip is less, guaranteed that chip resource occupies fewly, solved among the prior art FPGA design and taken up the problem of more chip resource at the stage of synthesizing.
In practical application, data input or output of the memory is in a bus form, so that register chains with the same length and the same type can be combined into register chain groups, and the register chain groups are mapped into the memory.
According to a specific embodiment of the present application, the obtaining unit includes an obtaining module and a traversing module, wherein the obtaining module is configured to obtain a target register in the FPGA design; and the traversal module is used for traversing the FPGA design according to the target register and determining the register chain group. Through the target register, the FPGA design is traversed to obtain the register chain group, so that all the register chain groups in the FPGA design can be found quickly and accurately, and at least part of the register chain groups in the register chain groups can be replaced by corresponding memories conveniently in the follow-up process.
In order to further ensure that all register chain groups in the FPGA design can be found more quickly and accurately, according to another specific embodiment of the present application, as shown in fig. 4, in a case that the register chain group includes one register chain, the traversal module includes a first traversal submodule, the first traversal submodule is configured to traverse the FPGA design along a first direction and a second direction respectively with the target register 100 as a start position, and determine the register chain 200, the register chain 200 is the register chain group, the first direction is an extension direction of an input end of the target register 100, the second direction is an extension direction of an output end of the target register 100, and the first direction and the second direction are opposite.
According to another specific embodiment of the present application, in a case that the register chain group includes a plurality of register chains, the traversal module includes a second traversal submodule and a merge module, where the second traversal submodule is configured to traverse the FPGA design along a first direction and a second direction respectively with the target register as a start position, to determine a plurality of register chains, capacities and types of the plurality of register chains are all the same, the first direction is an extending direction of an input end of the target register, the second direction is an extending direction of an output end of the target register, and the first direction and the second direction are opposite; the merging module is used for merging the plurality of register chains to obtain the register chain group. Therefore, all register chain groups in the FPGA design can be found more quickly and accurately.
In a specific embodiment of the present application, a target register in the FPGA design is determined, an output pin of the target register traverses the search register backward until reaching a chain end of the register, and then the input pin of the target register traverses the search register forward until reaching a chain head of the register, and the chain head and the chain end of the register are recorded. It is sufficient that all register control signals in this chain are identical and are synchronous or asynchronous during traversal. And circulating the steps until all the register chains in the FPGA design are found, and recording the input and output of the register chains and the length of the register chains.
In another specific embodiment of the present application, the first determining unit includes a determining module and a constructing module, where the determining module is configured to determine, according to the target register chain group, an input end, an output end, a write enable end, and an initial value of the corresponding target memory; the building module is used for building the corresponding address bus of the target memory according to the target register chain group. According to the device, the input end, the output end, the write enable end and the initial value of the corresponding target memory are determined according to the target register chain group, and the address bus of the corresponding target memory is constructed, so that the target memory is conveniently used for replacing the corresponding target register chain group subsequently, the number of nodes in the updated FPGA design is further ensured to be less, and the occupied chip resources are further ensured to be less.
In order to establish an address bus of the target memory more easily, so as to further facilitate subsequent replacement of the corresponding target register chain group with the target memory, in another specific embodiment of the present application, the building module includes a first obtaining submodule, a first determining submodule, a building submodule, and a second determining submodule, where the first obtaining submodule is configured to obtain a depth of a target register chain in the target register chain group; the first determining submodule is used for determining the width of the address bus according to the depth of the target register chain; the construction submodule is used for constructing a counter according to the width of the address bus; the second determining submodule is configured to determine that the output terminal of the counter is the address bus.
In an actual application process, the counter can be constructed by using a primitive with an addition function on the design of the FPGA, and can also be constructed by using other logic primitives. The address bit width of the target memory is log2 depthRounded up, depth being the depth of the corresponding set of destination register chains, e.g. set of destination register chainsIs 16, then the corresponding target memory has an address width of 4, and when the depth of the target register chain set is 17, then the corresponding target memory has an address width of 5.
In order to further facilitate subsequent replacement of the corresponding target register chain group by using the target memory, thereby further ensuring that fewer nodes are present in the updated FPGA design, according to yet another specific embodiment of the present application, the determining module includes a third determining submodule, a fourth determining submodule, a fifth determining submodule, a second obtaining submodule, and a sixth determining submodule, where the third determining submodule is configured to determine that an input end of a target register chain in the target register chain group is an input end of the target memory; the fourth determining submodule is configured to determine that an output end of the target register chain is an output end of the target memory; the fifth determining submodule is configured to determine that enable terminals of the plurality of registers in the target register chain group are write enable terminals of the target memory; the second obtaining submodule is used for obtaining the initial values of a plurality of registers in the target register chain group; the sixth determining submodule is configured to determine an initial value of the target memory based on initial values of the plurality of registers.
In an actual application process, the sixth determining sub-module is further configured to determine an arrangement order of initial values of the plurality of registers according to the structure information of the target register chain group, so as to obtain an initial value array, where the structure information at least includes a serial order of the target register chain; the sixth determining submodule is further configured to determine that the initial value array is an initial value of the target memory. The device can determine the initial value of the corresponding target memory more simply and quickly through the serial sequence of the target register chain.
According to another specific embodiment of the present application, in a case that the target register chain group includes a plurality of target register chains, the configuration information further includes a correspondence relationship between an input terminal of each of the target register chains and an input terminal of the target memory. When the target register chain group includes a plurality of target register chains, the initial value of the target memory is determined based on the serial order of the target register chains and the correspondence between the input terminals of the target register chains and the input terminals of the target memory.
In an actual application process, in order to further ensure that the target memory can be used to replace the corresponding target register chain group, in another specific embodiment of the present application, the apparatus further includes a second determining unit, a third determining unit, and an obtaining unit, where the second determining unit is configured to determine whether the capacity of the target memory is greater than the capacity of the target register chain group after determining an arrangement order of the initial values of the plurality of registers according to the structure information of the target register chain group and before determining that the initial value array is the initial value of the target memory; the third determining unit is configured to determine a missing bit of the initial value array when the capacity of the target memory is larger than the capacity of the target register chain group, the missing bit being a position where the target register chain group is less than the target memory by the initial value; the obtaining unit is configured to obtain the updated initial value array by using a predetermined value as the initial value of the missing bit.
In a specific embodiment, when the capacity of the target register chain group does not satisfy the capacity of the corresponding target memory, the initial value of the missing bit is all complemented by 0.
The comprehensive implementation device of the FPGA design comprises a processor and a memory, wherein the acquisition unit, the first determination unit, the replacement unit and the like are stored in the memory as program units, and the processor executes the program units stored in the memory to implement corresponding functions.
The processor comprises a kernel, and the kernel calls the corresponding program unit from the memory. The kernel can be set to be one or more than one, and the problem that FPGA design occupies more chip resources in the comprehensive stage in the prior art is solved by adjusting kernel parameters.
The memory may include volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or Flash memory (Flash RAM), and the memory includes at least one memory chip.
The embodiment of the invention provides a computer readable storage medium, wherein a program is stored on the computer readable storage medium, and the program is used for realizing the comprehensive implementation method of the FPGA design when being executed by a processor.
The embodiment of the invention provides a processor, which is used for running a program, wherein the comprehensive implementation method of the FPGA design is executed when the program runs.
The embodiment of the invention provides equipment, which comprises a processor, a memory and a program which is stored on the memory and can run on the processor, wherein when the processor executes the program, at least the following steps are realized:
step S101, a register chain group in FPGA design is obtained, the register chain group comprises at least one register chain, the register chain is formed by connecting a plurality of registers in series, control signals of the plurality of registers are the same, and the plurality of registers are all synchronous registers or asynchronous registers;
step S102, determining a target memory corresponding to the target register chain group;
and step S103, replacing the corresponding target register chain group by using the target memory to obtain the updated FPGA design.
The device herein may be a server, a PC, a PAD, a mobile phone, etc.
The present application further provides a computer program product adapted to perform a program of initializing at least the following method steps when executed on a data processing device:
step S101, a register chain group in FPGA design is obtained, the register chain group comprises at least one register chain, the register chain is formed by connecting a plurality of registers in series, control signals of the plurality of registers are the same, and the plurality of registers are all synchronous registers or asynchronous registers;
step S102, determining a target memory corresponding to the target register chain group;
and step S103, replacing the corresponding target register chain group by using the target memory to obtain the updated FPGA design.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit may be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as a separate product. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the above methods according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) firstly, a register chain group in the FPGA design is obtained, wherein the register chain group at least comprises one register chain, namely the register chain group can comprise one register chain and also comprises a plurality of register chains, and one register chain comprises a plurality of registers connected in series; then determining a target memory corresponding to a target register chain group, wherein the register chain group comprises the target register chain group; and finally, replacing the corresponding target register chain group by using the target memory to obtain the updated FPGA design. In the method, the target memory is used for replacing the corresponding target register chain group in the FPGA design, namely one target memory is used for replacing a plurality of corresponding registers in the FPGA design, and the number of nodes corresponding to one target memory is less than that of the nodes corresponding to the registers, so that the number of the nodes in the updated FPGA design is less, the occupied area of a chip is less, the chip resource is less, and the problem that the FPGA design occupies more chip resources in the comprehensive stage in the prior art is solved.
2) The comprehensive implementation device for the FPGA design obtains a register chain group in the FPGA design through the obtaining unit, where the register chain group includes at least one register chain, that is, the register chain group may include one register chain and may also include a plurality of register chains, and one register chain includes a plurality of registers connected in series; determining a target memory corresponding to a target register chain group by the first determining unit, wherein the register chain group comprises the target register chain group; and replacing the corresponding target register chain group by using the target memory through the replacing unit to obtain the updated FPGA design. In the above-mentioned device of this application, through using the target memory to replace the corresponding target register chain group in the FPGA design, even if used a target memory to replace a plurality of registers that correspond in the FPGA design, because the node quantity that a target memory corresponds is less than the node quantity that a plurality of registers correspond, guaranteed like this that the node in the FPGA design after the update is less, thereby guaranteed that the area occupied of chip is less, guaranteed that chip resource occupies fewly, solved among the prior art FPGA design and taken up the problem of more chip resource at the stage of synthesizing.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (14)
1. A comprehensive implementation method for FPGA design is characterized by comprising the following steps:
acquiring a register chain group in FPGA design, wherein the register chain group comprises at least one register chain, the register chain is formed by connecting a plurality of registers in series, control signals of the plurality of registers are the same, and the plurality of registers are all synchronous registers or asynchronous registers;
determining a target memory corresponding to the target register chain group;
and replacing the corresponding target register chain group by using the target memory to obtain the updated FPGA design.
2. The method of claim 1, wherein obtaining a set of register chains in an FPGA design comprises:
acquiring a target register in the FPGA design;
and traversing the FPGA design according to the target register to determine the register chain group.
3. The method of claim 2, wherein traversing the FPGA design to determine the set of register chains according to the target register comprises:
and traversing the FPGA design along a first direction and a second direction respectively by taking the target register as an initial position to determine the register chain, wherein the register chain is the register chain group, the first direction is the extension direction of the input end of the target register, the second direction is the extension direction of the output end of the target register, and the first direction is opposite to the second direction.
4. The method of claim 2, wherein traversing the FPGA design to determine the set of register chains according to the target register comprises:
traversing the FPGA design along a first direction and a second direction respectively by taking the target register as an initial position to determine a plurality of register chains, wherein the capacities and the types of the plurality of register chains are the same, the first direction is the extension direction of the input end of the target register, the second direction is the extension direction of the output end of the target register, and the first direction is opposite to the second direction;
and combining the plurality of register chains to obtain the register chain group.
5. The method of claim 1, wherein determining the target memory to which the set of target register chains corresponds comprises:
determining an input end, an output end, a write enable end and an initial value of the corresponding target memory according to the target register chain group;
and constructing an address bus of the corresponding target memory according to the target register chain group.
6. The method of claim 5, wherein constructing an address bus for the corresponding target memory from the set of target register chains comprises:
acquiring the depth of a target register chain in the target register chain group;
determining the width of the address bus according to the depth of the target register chain;
constructing a counter according to the width of the address bus;
and determining the output end of the counter as the address bus.
7. The method of claim 5, wherein determining the input, output, write enable, and initial values of the corresponding target memory according to the target register chain set comprises:
determining an input end of a target register chain in the target register chain group as an input end of the target memory;
determining an output end of the target register chain as an output end of the target memory;
determining enabling ends of a plurality of registers in the target register chain group as writing enabling ends of the target memory;
acquiring initial values of a plurality of registers in the target register chain group;
and determining the initial value of the target memory according to the initial values of the plurality of registers.
8. The method of claim 7, wherein determining an initial value of the target memory from initial values of a plurality of the registers comprises:
determining the arrangement sequence of the initial values of the registers according to the structure information of the target register chain group to obtain an initial value array, wherein the structure information at least comprises the serial connection sequence of the target register chain;
and determining the initial value array as the initial value of the target memory.
9. The method according to claim 8, wherein, in a case where the destination register chain group includes a plurality of the destination register chains, the configuration information further includes a correspondence relationship between an input terminal of each of the destination register chains and an input terminal of the destination memory.
10. The method according to claim 8 or 9, wherein after determining an arrangement order of the initial values of the plurality of registers according to the configuration information of the target register chain group, before determining the initial value array as the initial values of the target memory, the method further comprises:
determining whether a capacity of the target memory is greater than a capacity of the target chain set of registers;
determining a missing bit of the initial value array if the capacity of the target memory is greater than the capacity of the target register chain group, the missing bit being a position where the target register chain group lacks the initial value compared to the target memory;
and taking a preset numerical value as an initial value of the missing bit to obtain the updated initial value array.
11. The utility model provides a synthesize realization device of FPGA design which characterized in that includes:
the FPGA control device comprises an acquisition unit, a processing unit and a control unit, wherein the acquisition unit is used for acquiring a target register chain group in FPGA design, the target register chain group comprises at least one register chain, the register chain is formed by connecting a plurality of registers in series, control signals of the registers are the same, and the registers are all synchronous registers or asynchronous registers;
the first determining unit is used for determining a target memory corresponding to the target register chain group;
and the replacing unit is used for replacing the corresponding target register chain group by using the target memory to obtain the updated FPGA design.
12. A computer-readable storage medium, characterized in that the computer-readable storage medium comprises a stored program, wherein the program performs the method of any one of claims 1 to 10.
13. A processor, characterized in that the processor is configured to run a program, wherein the program when running performs the method of any of claims 1 to 10.
14. An electronic device, comprising: one or more processors, memory, and one or more programs stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for performing the method of any of claims 1-10.
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