CN112903800A - Semiconductor structure analysis method - Google Patents
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Abstract
The invention provides a semiconductor structure analysis method, which comprises the following steps: providing a substrate on an insulator, wherein the substrate comprises an upper semiconductor layer, a lower semiconductor layer and an oxide layer positioned between the upper semiconductor layer and the lower semiconductor layer; forming a test block on the surface of the upper semiconductor layer; etching the test block to form an etching groove, wherein the etching groove penetrates through the upper semiconductor layer and the oxide layer; filling a conductive medium into the etching groove to form a conductive path; and analyzing the test block by using a secondary ion mass spectrometry method. In the configuration, the conductive medium is filled in the formed etching groove to form a conductive path to connect the upper semiconductor layer and the lower semiconductor layer, so that an electric field formed by a large amount of positive charges enriched in the test block is eliminated, and secondary ions can normally deflect to the receiver when secondary ion mass spectrometry is carried out. Further, by studying the secondary ion signal spectrograms of the test block and the substrate, the position of the oxide layer in the substrate and the thickness of the oxide layer can be roughly determined.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure analysis method.
Background
The secondary ion mass spectrometry is a high-sensitivity and high-resolution surface analysis instrument, and is an essential tool in the manufacturing and developing stages of semiconductor integrated circuits. In the semiconductor process of 28/22/14/12nm and other nodes, the doping of SiGe and SiP in trace amount in the material has great influence on the characteristics of the applied device, and the prior art generally adopts secondary ion mass spectrometry to research the distribution of ultra-shallow implantation and ultra-thin layer impurity Ge/B/P elements.
For the products of LP/HKMG/FinFET process, as shown in fig. 1a, fig. 1a is a schematic diagram of conventional secondary ion mass spectrometry, and the secondary ion mass spectrometry is completed by adjusting the voltage 01 applied to the substrate to a target value, so that the secondary ions sputtered from the substrate are deflected to the secondary ion receiver 02 under the action of the electric field.
As shown in fig. 1b to 1d, fig. 1b is a schematic diagram of a conventional FDSOI structure, fig. 1c is a front view of the FDSOI structure, and fig. 1d is a top view of the FDSOI structure, where an oxide layer 03 is formed on a silicon substrate in the FDSOI (fully depleted silicon on insulator) compared to LP/HKMG/FinFET process products. In addition, a test region 04 is formed on the surface of the silicon substrate, as shown in fig. 1e, fig. 1e is a schematic diagram of secondary ion mass spectrometry of an FDSOI structure, a primary ion beam is continuously injected into the test region to bring a large amount of positive charges to the silicon substrate, and the oxidation layer 03 is not conductive, so that a large amount of positive charges are enriched on the surface of the silicon substrate, and an electric field is formed, so that sputtered secondary ions are deflected from the secondary ion receiver 02 under the action of the electric field, and secondary ion mass spectrometry cannot be performed.
Disclosure of Invention
The invention aims to provide a semiconductor structure analysis method, which aims to solve the problem that the conventional FDSOI product cannot be subjected to secondary ion mass spectrometry.
To solve the above technical problem, the present invention provides a semiconductor structure analysis method, which includes:
providing a substrate on an insulator, wherein the substrate comprises an upper semiconductor layer, a lower semiconductor layer and an oxide layer positioned between the upper semiconductor layer and the lower semiconductor layer; forming a test block on the surface of the upper semiconductor layer;
etching the test block to form an etching groove, wherein the etching groove penetrates through the upper semiconductor layer and the oxide layer;
filling a conductive medium into the etching groove to form a conductive path; and
and analyzing the test block by using a secondary ion mass spectrometry method.
Optionally, the test block is etched to form at least four etching grooves.
Optionally, at least four etching grooves are arranged to be distributed along the circumferential direction of the test block.
Optionally, the step of etching the test block to form an etched groove includes: and etching the test block by utilizing a focused ion beam process.
Optionally, the step of filling the etching groove with a conductive medium to form a conductive path includes: and filling the conductive medium into the etching groove by utilizing a focused ion beam process.
Optionally, the step of analyzing the test block by using a secondary ion mass spectrometry method includes:
bombarding the test block by using a primary ion beam to sputter a secondary ion beam on the surface of the test block;
and receiving the secondary ion beam by using a detector, and performing secondary ion mass spectrometry.
Optionally, before bombarding the test block with the primary ion beam, analyzing the test block by using a secondary ion mass spectrometry method further includes; and loading a power supply to the substrate, and adjusting the voltage of the power supply to a preset value.
Optionally, one end of the power supply is grounded.
Optionally, the conductive medium comprises at least one of platinum and tungsten.
Optionally, the substrate comprises a fully depleted silicon-on-insulator substrate.
In summary, the semiconductor structure analysis method provided by the present invention includes: providing a substrate on an insulator, wherein the substrate comprises an upper semiconductor layer, a lower semiconductor layer and an oxide layer positioned between the upper semiconductor layer and the lower semiconductor layer; forming a test block on the surface of the upper semiconductor layer; etching the test block to form an etching groove, wherein the etching groove penetrates through the upper semiconductor layer and the oxide layer; filling a conductive medium into the etching groove to form a conductive path; and analyzing the test block by using a secondary ion mass spectrometry method. The etching groove is formed by etching the test block of the upper semiconductor layer, penetrates through the upper semiconductor layer and the oxide layer, and is filled with a conductive medium to form a conductive path so as to connect the upper semiconductor layer and the lower semiconductor layer, so that an electric field formed by a large number of positive charges enriched in the test block is eliminated, and secondary ions can normally deflect towards the receiver when secondary ion mass spectrometry is carried out, so that secondary ion mass spectrometry is carried out. Further, by studying the secondary ion signal spectrograms of the test block and the substrate, the position of the oxide layer in the substrate and the thickness of the oxide layer can be roughly determined.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention. Wherein:
FIG. 1a is a schematic representation of a prior art secondary ion mass spectrometry analysis;
FIG. 1b is a schematic diagram of a prior art FDSOI structure;
FIG. 1c is a front view of a prior art FDSOI structure;
FIG. 1d is a top view of a prior art FDSOI structure;
FIG. 1e is a schematic diagram of secondary ion mass spectrometry analysis of an FDSOI structure;
FIG. 2a is a schematic diagram of a test block and a substrate according to an embodiment of the invention;
FIG. 2b is a front view of a test block and a substrate according to an embodiment of the invention;
FIG. 2c is a top view of the test block and the substrate according to one embodiment of the present invention;
FIG. 2d is a schematic view of an etch trench according to an embodiment of the present invention;
FIG. 2e is a schematic diagram of a conductive path according to an embodiment of the present invention;
FIG. 2f is a distribution diagram of etched trenches in accordance with one embodiment of the present invention;
FIG. 2g is a schematic diagram of secondary ion mass spectrometry of the test block and the substrate according to one embodiment of the present invention;
FIG. 2h is a signal spectrum of secondary ion mass spectrometry of the test block and the substrate in accordance with one embodiment of the present invention.
In the drawings:
01-voltage; 02-secondary ion receiver; 03-an oxide layer; 04-test area;
10-a substrate; 11-an upper semiconductor layer; 111-test blocks; 112-etching a groove; 113-a conductive path; 12-a lower semiconductor layer; 13-an oxide layer; 20-a detector; 30-power supply.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, features defined as "first," "second," and "third" may explicitly or implicitly include one or at least two of the features unless the content clearly dictates otherwise.
The invention provides a semiconductor structure analysis method, which aims to solve the problem that the conventional FDSOI product cannot be subjected to secondary ion mass spectrometry.
The following description refers to the accompanying drawings.
As shown in fig. 2a to 2c, fig. 2a is a schematic diagram of a test block and a substrate according to an embodiment of the present invention, fig. 2b is a front view of the test block and the substrate according to the embodiment of the present invention, and fig. 2c is a top view of the test block and the substrate according to the embodiment of the present invention, the embodiment provides a substrate 10 on an insulator, wherein the substrate 10 includes an upper semiconductor layer 11, a lower semiconductor layer 12, and an oxide layer 13 located between the upper semiconductor layer 11 and the lower semiconductor layer 12; forming a test block 111 on the surface of the upper semiconductor layer 11; it should be noted that the substrate 10 on an insulator described in this embodiment specifically refers to a fully depleted silicon-on-insulator substrate 10, and the oxide layer 13 (specifically, a silicon dioxide layer) located in the middle layer is insulated and isolates the upper semiconductor layer 11 from the lower semiconductor layer 12.
As shown in fig. 2d, fig. 2d is a schematic diagram of an etching groove according to an embodiment of the invention, the test block 111 is etched to form an etching groove 112, and the etching groove 112 penetrates through the upper semiconductor layer 11 and the oxide layer 13.
As shown in fig. 2e, fig. 2e is a schematic diagram of a conductive path according to an embodiment of the present invention, and the etching groove 112 is filled with a conductive medium to form a conductive path 113; optionally, the conductive medium is at least one of platinum and tungsten, but may be other materials for conducting electricity, such as copper and gold.
As shown in fig. 2g, fig. 2g is a schematic diagram of secondary ion mass spectrometry of the test block and the substrate according to an embodiment of the invention, and the test block 111 is analyzed by using a secondary ion mass spectrometry method, but elements in the substrate 10 may also be analyzed.
In the above semiconductor structure analysis method, an etching trench 112 is formed by etching the test block 111, and the etching trench 112 penetrates through the upper semiconductor layer 11 and the oxide layer 13, and the etching trench 112 is filled with a conductive medium to form a conductive via 113, so that the upper semiconductor layer 11 and the lower semiconductor layer 12 can be connected through the conductive via 113, and when performing secondary ion mass spectrometry, a large amount of positive charges brought to the surface of the test block 111 by a primary ion beam can be introduced into the lower semiconductor layer 12 through the conductive via 113, thereby eliminating a surface electric field formed by the large amount of positive charges, and enabling secondary ions sputtered from the surface of the test block 111 to normally deflect to a secondary ion receiver (detector 20), thereby performing secondary ion mass spectrometry.
Referring to fig. 2f, fig. 2f is a layout diagram of etching grooves according to an embodiment of the invention, and optionally, the test block 111 is etched to form at least four etching grooves 112 (fig. 2f shows four etching grooves 112). Further, at least four etching grooves 112 are arranged to be distributed along the circumferential direction of the test block 111. In the embodiment, the top view of the test block 111 is rectangular, and the four etching grooves 112 are respectively located at four corners of the rectangle. The shape of the test block 111 is not limited in the present invention, and may be any shape, such as a circle, a polygon, an ellipse, … …. It should be noted that the shape of the etching trench 112 is not limited in the present invention, and the shape may be similar to the shape of the test block 111, such as rectangular, circular … …; further, the extending direction of the etching grooves 112 (the direction from the upper semiconductor layer 11 to the lower semiconductor layer 12) is not limited to being perpendicular to the upper semiconductor layer 11, and may be inclined (such as inclined at 60 ° or 45 °) to the upper semiconductor layer 11.
Further, the step of etching the test block 111 to form the etched groove 112 includes: the test block 111 is etched using a focused ion beam process.
Further, the step of filling the etching groove 112 with a conductive medium to form a conductive via 113 includes: the conductive medium is filled into the etched trench 112 using a focused ion beam process.
It should be noted that a Focused Ion Beam (FIB) system is a micro-machining instrument that focuses an Ion beam to a very small size using a lens. The material surface is bombarded by charged energy ions, so that the stripping, deposition, injection and modification of the material are realized. The basic functions of a focused ion beam microscope can be broadly divided into four categories: (1) site directed cleavage (precision cutting): the physical collision of ions is used to achieve the purpose of cutting. The method is widely applied to Cross Section (Cross Section) processing and analysis of Integrated Circuits (IC) and LCDs. (2) Selective material evaporation (Selective Deposition): the Deposition of Metal and TEOS Deposition of Metal and oxide layers (Metal and TEOS Deposition) may be provided by decomposing organometallic vapors or vapor phase insulating materials with ion beam energy to deposit either conductive or non-conductive layers in localized areas, with the common Metal Deposition being Platinum (Pt) and tungsten (tungsten, W). (3) Enhanced Etching or Selective Etching (Enhanced Etching-Iodine/Selective Etching-XeF 2): assisted by corrosive gases, the efficiency of the cutting or selective material removal is accelerated. (4) Etch endpoint Detection (End Point Detection): the signal of the secondary ions is detected to know the progress of the cutting or etching. In this embodiment, the conductive medium is filled into the etching grooves 112 by using the (2) th function of the focused ion beam, and the test block 111 is etched by using the (3) th function of the focused ion beam to form the etching grooves 112.
Further, the step of analyzing the test block 111 and the substrate 10 by using a secondary ion mass spectrometry method includes:
using a primary ion beam (O)2Bombard the test block 111 with + causing the surface of the test block 111 to sputter a secondary ion beam (Ge +/P +);
the secondary ion beam is received by detector 20 for secondary ion mass spectrometry.
It is to be understood that the principle of secondary ion mass spectrometry is: when the surface of the test block 111 is bombarded by the primary ion beam focused by high energy, the primary ion beam is injected into the test block 111, transfers kinetic energy to solid atoms, causes neutral particles and a secondary ion beam with positive and negative charges to be sputtered by cascade collision, and analyzes the element distribution characteristics of the test block 111 and the substrate 10 according to the mass signal of the sputtered secondary ion beam.
Further, the step of analyzing the test block 111 and the substrate 10 by using a secondary ion mass spectrometry method before bombarding the test block 111 with the primary ion beam further comprises; the substrate 10 is loaded with a power supply 30, and the voltage of the power supply 30 is adjusted to a predetermined value. Still further, one end of the power supply 30 is grounded. With this arrangement, the electric field of the substrate 10 is oriented such that the lower semiconductor layer 12 faces the upper semiconductor layer 11, so that the sputtered secondary ion beam is correctly deflected toward the secondary ion receiver (detector 20). In addition, the predetermined value of the voltage is set according to actual conditions.
Further, referring to fig. 2h, fig. 2h is a signal spectrum diagram of secondary ion mass spectrometry of the test block 111 and the substrate 10 according to an embodiment of the present invention, wherein the X-axis represents the depth (in nm) from the surface of the test block 11 to the lower semiconductor layer 12, and the Y-axis represents the concentration of each element, typically, the material of the test block 111 is SiGe (silicon-germanium) and is doped with B (boron), the material of the upper semiconductor layer 11 and the lower semiconductor layer 12 is silicon, it should be understood that the concentration of each element herein refers to the ratio (i.e. percentage) of the concentrations of Ge and Si, and the sum of the concentrations is 100%; for B, it refers to its concentration content (i.e., number of atoms per unit volume). As shown in fig. 2h, when the oxide layer 13 (i.e., the silicon dioxide layer) is tested, the auxiliary conduction function of the focused ion beam process fails, the surface of the tested region (specifically, the silicon dioxide layer) is again enriched with positive charges, the sputtered secondary ion beam cannot reach the detector, the content of the B element is suddenly reduced at X1, after the oxide layer 13 is finished, the content of the B element suddenly increases at X2 due to the sudden change of the material of the surface of the tested region (i.e., the lower semiconductor layer 12 is reached), and then the curve returns to normal, so that it can be determined that the thickness of the oxide layer 13 is approximately (X2-X1) nm, and the depth of the oxide layer 13 in the substrate is approximately at X1 nm. It should be noted that, in order to schematically show the position of the oxide layer 13 in the substrate, in fig. 2h, the depth of the substrate 10 is only shown as 40nm, and actually it should be understood that the depth of the substrate 10 is greater than 40 nm.
In summary, the semiconductor structure analysis method provided by the present invention includes: providing a substrate on an insulator, wherein the substrate comprises an upper semiconductor layer, a lower semiconductor layer and an oxide layer positioned between the upper semiconductor layer and the lower semiconductor layer; forming a test block on the surface of the upper semiconductor layer; etching the test block to form an etching groove, wherein the etching groove penetrates through the upper semiconductor layer and the oxide layer; filling a conductive medium into the etching groove to form a conductive path; and analyzing the test block and the substrate by using a secondary ion mass spectrometry method. The etching groove is formed by etching the test block of the upper semiconductor layer, penetrates through the upper semiconductor layer and the oxide layer, and is filled with a conductive medium to form a conductive path so as to connect the upper semiconductor layer and the lower semiconductor layer, so that an electric field formed by a large number of positive charges enriched in the test block is eliminated, and secondary ions can normally deflect towards the receiver when secondary ion mass spectrometry is carried out, so that secondary ion mass spectrometry is carried out. Further, by studying the secondary ion signal spectrograms of the test block and the substrate, the position of the oxide layer in the substrate and the thickness of the oxide layer can be roughly determined.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method of semiconductor structure analysis, comprising:
providing a substrate on an insulator, wherein the substrate comprises an upper semiconductor layer, a lower semiconductor layer and an oxide layer positioned between the upper semiconductor layer and the lower semiconductor layer; a test block is formed on the surface of the upper semiconductor;
etching the test block to form an etching groove, wherein the etching groove penetrates through the upper semiconductor layer and the oxide layer;
filling a conductive medium into the etching groove to form a conductive path; and
and analyzing the test block by using a secondary ion mass spectrometry method.
2. The method of claim 1, wherein the test block is etched to form at least four etched trenches.
3. The method of claim 2, wherein at least four of the etched grooves are arranged along a circumference of the test block.
4. The method of claim 1, wherein the step of etching the test block to form an etched trench comprises: and etching the test block by utilizing a focused ion beam process.
5. The method for analyzing a semiconductor structure according to claim 1, wherein the step of filling the etched trench with a conductive medium to form a conductive via comprises: and filling the conductive medium into the etching groove by utilizing a focused ion beam process.
6. The method of claim 1, wherein analyzing the test block using secondary ion mass spectrometry comprises:
bombarding the test block by using a primary ion beam to sputter a secondary ion beam on the surface of the test block;
and receiving the secondary ion beam by using a detector, and performing secondary ion mass spectrometry.
7. The method of claim 6, wherein analyzing the test block using secondary ion mass spectrometry prior to bombarding the test block with the primary ion beam further comprises; and loading a power supply to the substrate, and adjusting the voltage of the power supply to a preset value.
8. The method of claim 7, wherein one terminal of the power supply is grounded.
9. The method of claim 1, wherein the conductive medium comprises at least one of platinum and tungsten.
10. The method of claim 1, wherein the substrate comprises a fully depleted silicon-on-insulator substrate.
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