CN112886875A

CN112886875A - Brushless DC motor driving method

Info

Publication number: CN112886875A
Application number: CN202110176368.3A
Authority: CN
Inventors: 高源�; 任海波
Original assignee: Suzhou Continental Zhiyuan Robot Technology Co ltd; Dalu Zhiyuan Technology Beijing Co ltd
Current assignee: Suzhou Continental Zhiyuan Robot Technology Co ltd; Dalu Zhiyuan Technology Beijing Co ltd
Priority date: 2019-04-28
Filing date: 2019-04-28
Publication date: 2021-06-01
Also published as: CN109980996B; CN109980996A

Abstract

A brushless DC motor driving method for driving a plurality of brushless DC motors, comprising: adopting AD to collect BLDC current value data in the brushless DC motor; reading Hall code disc data of a brushless direct current motor in the FPGA chip by an ARM chip through a bus, calculating according to the Hall code disc data of the brushless direct current motor to obtain a motor control value, and transmitting the motor control value back to the FPGA chip through the bus; the FPGA chip is used for receiving a motor control value sent by the ARM chip and storing Hall code disc data of the brushless direct current motor, and is provided with a plurality of NMOS; the FPGA chip controls the corresponding NMOS to be opened or closed according to the motor control value so as to send out a BLDC current value, and therefore the brushless direct current motor is driven in a time synchronization mode.

Description

Brushless DC motor driving method

The application is a divisional application of an invention patent application with the application number of 201910347706.8, the application date of 2019, 4 and 28 and the name of 'brushless direct current motor driving integration system and driving method'.

Technical Field

The present invention provides a system and a method for integrating brushless dc motors, and more particularly, to a driving apparatus and a driving method for integrally controlling a plurality of brushless dc motors by an FPGA chip.

Background

Most of existing BLDC (Brushless direct current Motor) driving modules drive a single BLDC, and a single MCU (micro control unit) built by a single ARM chip architecture is used to drive the single BLDC. For example, some prior art discloses a BLDC control system that uses an MCU constructed with an ARM chip architecture to send out motor control signals to drive the BLDC. The Hall sensor is matched to detect the motor running direction and the sampling resistor detects the running speed, and the detected value is directly transmitted back to the MCU, so that the MCU sends out a control signal of the next time to adjust the motor control signal in real time. The MCU also has a means for determining whether to turn off the motor. The motor is determined to be turned off or not by judging whether the current of the motor exceeds the threshold current or not during operation. However, the brushless dc motor control system of the present invention can control only a single BLDC, and cannot simultaneously control a plurality of BLDCs at a time.

If a plurality of BLDCs need to be driven at the same time, a driving module consisting of a plurality of ARM chips is used for driving the BLDCs. Fig. 1 is a schematic diagram of another prior art brushless dc motor driving apparatus. The brushless DC motor driving device can drive at least 3 BLDCs. And the structure is similar to the traditional BLDC control system for driving a single BLDC, and the newly added cpu in the driving circuit board is used as a Master (Master) to drive a plurality of BLDC slaves (Slave). The central processor can also receive feedback signals transmitted when the plurality of BLDCs operate in real time so as to serve as a reference for transmitting the BLDC driving signals to the driving circuit board at the next time.

However, if a larger number of BLDCs are to be driven, for example, 10 BLDCs are to be driven, 10 ARM chips are required, which results in an increase in the space occupied by the driving circuit board; even if a central processing unit, an ARM chip, a motor driving circuit and a Hall coded disc processing circuit in the driving circuit board are integrated into a chip, a large chip area is still needed when a plurality of BLDCs are driven. Further, when the more BLDC is driven, the more complicated the procedure of the cpu changing the hardware configuration.

On the other hand, the BLDC requires more PWM resources, and a single BLDC needs to be connected to 6 complementary PWM signals, that is, one PWM401 in fig. 1 has 6 complementary PWM signals, and the integrated circuit pin of a single ARM chip built under the ARM chip architecture can only be connected to 32 complementary PWM signals at most, so that a single ARM chip cannot be connected to more than 6 BLDC resources.

Moreover, the plurality of driving modules respectively control the plurality of BLDCs via the plurality of buses, and the delay time of the bus communication mechanism is long, for example, as shown in fig. 2, there are time differences τ 1 and τ 2 between the time of the control signal sent by the single PWM401 and the Hall signal detected by the Hall code disc processing circuit 30 in real time, τ 1 is any value between 3ms and 5ms, and τ 2 is between 4ms and 6ms, so that the plurality of driving modules cannot effectively implement the synchronization of the motor control (generally, the synchronization of the single motor control means that τ 1 and τ 2 are less than 10 us). The existing BLDC driving module cannot achieve high-precision synchronous coordinated control of a plurality of BLDCs at all.

Furthermore, for the BLDC driving module that drives a plurality of BLDC with output power exceeding 1000 w, because the plurality of ARM chips in the BLDC driving module need to be integrated on a small-area printed circuit board (hereinafter, referred to as PCB), and the copper-laid on the surface of the PCB may be burned due to high power and high temperature exceeding the rated power generated by the large current flowing through the PCB. A plurality of ARM chips are integrated on a PCB, and the problem of mutual interference is easily caused by too close winding distance.

Disclosure of Invention

In order to overcome the drawbacks of the prior art, the present invention provides an integrated brushless dc motor driving system.

To achieve the above object, the present invention provides a brushless dc motor driving integration system for driving a plurality of brushless dc motors, comprising: ADC, for collecting BLDC current value data in the brushless DC motor; the ARM chip is used for reading Hall code disc data of the brushless direct current motor in the FPGA chip through a bus, calculating according to the Hall code disc data of the brushless direct current motor to obtain a motor control value, and transmitting the motor control value back to the FPGA chip through the bus; the FPGA chip is used for receiving the motor control value sent by the ARM chip and storing Hall code disc data of the brushless direct current motor, and the FPGA chip is provided with a plurality of NMOS; the FPGA chip controls the corresponding NMOS to be opened or closed according to the motor control value, and sends out a BLDC current value when the NMOS is closed, so that the brushless direct current motors are driven in a time synchronization mode.

Based on the above, the invention can directly insert one FPGA chip in an integrated circuit manner by arranging the FPGA chip in the brushless direct current motor driving device without changing the original FPGA chip hardware and adding additional control hardware, so as to synchronously control a single BLDC and a plurality of BLDCs. The number of the chips below 6 can be driven only by writing the control program into the existing FPGA chip in advance, so that the setting volume of the brushless direct current motor driving device is reduced, the time and money cost consumed when the brushless direct current motor driving device is modified can be reduced, and the method is convenient and quick.

In addition, the invention can solve the problem that the bus communication delay can not realize effective synchronous control of multiple motors. Enough PWM hardware resources are provided, and the problem of insufficient hardware resources in the prior art is solved. The copper bar is used for replacing a PCB (printed circuit board) in a traditional brushless direct current motor driving device to run, so that large driving current (greater than 100 amperes) can flow on the copper bar, and the problem that the large current cannot improve the driving current because a plurality of high-power motors are integrated on one board can be solved without passing through a PCB (printed circuit board).

Furthermore, the Hall code wheel data of the BLDC is processed by utilizing the hardware parallel processing advantage of the FPGA chip, the processed data is stored in the FPGA chip, the ARM chip reads the processed code wheel data from the FPGA chip through a bus, meanwhile, the ARM chip collects the current value data of the BLDC at a high speed, the ARM chip calculates a motor control value by utilizing the collected code wheel and the collected current data of the BLDC through an algorithm and sends the motor control value to the FPGA chip through the bus, the FPGA chip utilizes the abundant hardware resources of the FPGA chip and an NMOS formed by the FPGA chip to reduce the input and output delay time of signals, the input and output delay time is less than an ms level and reaches a us level, control information is output to a motor driving circuit, real-time synchronous control over a plurality of paths of motors is realized, and the brushless direct current motor driving module has higher competitiveness than the existing brushless.

In addition, the present invention provides a brushless dc motor driving method, including the steps of: except that the ARM chip is used for operating the Hall code disc data and the BLDC current value data to generate a motor control value and sending the motor control value to the FPGA chip; converting the motor control value into a plurality of synchronous motor control signals by using an FPGA chip to control the brushless DC motor, and further judging whether the BLDC current value data exceeds a threshold current; when the BLDC current value data does not exceed the threshold current, the BLDC current value data which is not 0 is transmitted back to the ARM chip, the motor control value which is not 0 is obtained by the ARM chip operation, and is transmitted back to the FPGA chip; when the BLDC current value data exceeds the threshold current, the ADC is used for directly converting the BLDC current value data into 0 and transmitting the 0 to the ARM chip, the ARM chip is used for calculating to obtain a motor control value which is 0 and transmitting the motor control value back to the FPGA chip so as to turn off the brushless direct current motor.

The brushless direct current motor driving method provided by the invention can generate a plurality of synchronous BLDC current value data to ensure that the control panel controls each BLDC synchronously in time, and also can protect the BLDC in real time through a threshold current judging means, so that the current is not overloaded when the BLDC is operated, and the operation safety of the BLDC is maintained.

Drawings

FIG. 1 is a schematic diagram of a prior art brushless DC motor driving apparatus;

FIG. 2 is a signal waveform diagram of each circuit pin of the prior art brushless DC motor driving device;

FIG. 3 is an architectural diagram illustrating an integrated brushless DC motor drive system in accordance with the teachings of the present invention;

FIG. 4 is a diagram illustrating the detailed architecture of an ARM chip in an integrated brushless DC motor drive system, according to the teachings of the present invention;

FIG. 5 is a diagram illustrating the architecture of an FPGA chip in a brushless DC motor drive integration system, according to the teachings of the present invention;

FIG. 6 is a signal waveform diagram illustrating various circuit pins of a brushless DC motor drive integration system in accordance with the teachings of the present invention;

FIG. 7 is a flow chart illustrating the general implementation of a driver in a brushless DC motor driving method according to the teachings of the present invention; and

fig. 8 is a flowchart showing the execution of a determination routine in the brushless dc motor driving method according to the technique of the present invention.

Detailed Description

So that the manner in which the above recited features and advantages of the present invention can be understood and attained by a person skilled in the art, a more particular description of the invention, briefly summarized above, may be had by reference to the appended drawings, in which like reference characters refer to the same parts throughout the several views. The drawings referred to below are schematic representations relating to the features of the invention and are not necessarily drawn to scale. The description of the embodiments related to the present invention will not be repeated, except for those skilled in the art.

Referring to fig. 3, fig. 3 is a schematic diagram of an integrated brushless dc motor driving system. The integrated brushless DC motor driving system disclosed in FIG. 3 is used to drive multiple BLDCs. The brushless dc motor driving integration system mainly includes a Field-Programmable Gate Array (FPGA) chip, an Advanced RISC Machines (Advanced RISC Machines) chip, and other chips for signal processing and control. In addition, the BLDC driving circuit also comprises circuit modules for driving the BLDC, such as a PWM (pulse-width modulation), a motor driving circuit, a Hall coded disc processing circuit and the like.

Figure 3 shows a simple architecture diagram of an ARM chip. An ARM chip is a processor built under a 32-bit Reduced Instruction Set (RISC) architecture, and generally serves as a signal processing device for interpreting and translating received instructions and issuing new instructions. The reason for adopting the simplified instruction set architecture to form the brushless direct current motor dynamic integration system is that the simplified instruction set does not contain microcode (microcode), and the design without microcode can reduce the number of transistors used by the ARM chip, and reduce the chip design complexity and the chip area.

The ARM chip internally includes modules such as an AHB bus, an ADC (Analog to Digital converter), Cortex _ M3, USART, a communication module, and a DMA channel. And each module in the ARM chip transmits and communicates data through an AHB bus. In the present embodiment, the data in the ARM chip is communicated with each other in the form of 32-bit data, but the invention is not limited thereto. The ADC is a device that converts BLDC current value data collected by an analog circuit from an analog form (analog) to a digital form (digital) so that the data is readable/writable and operable in an ARM chip. Because the signals readable and writable by the ARM chip are in digital form, the ADC is required to perform signal format conversion. In one embodiment, the ADC is implemented using

The reason for using the model AD7689 ADC chip with 24-bit (8-channel-24-bit) and a data Sampling Rate (Sampling Rate) of up to 250kSPS is that the ARM chip pin resource can be saved, a certain ADC Sampling precision is reserved, and 16-bit data can be processed at the same time, so that the information processing efficiency can be improved.

Cortex _ M3 is an Arithmetic Logic Unit (ALU) having a plurality of logic gates to perform data operations (computing). Various operations in the ARM chip are required to be performed through the Cortex _ M3 module. USART (universal synchronous/asynchronous transceiver) and DMA (Direct memory Access) channels constitute a transceiver for transmitting and receiving signals to and from an external personal computer, and are used for data exchange with other devices. In the transfer receiver, the USART is responsible for acquiring the instruction data format calculated by Cortex _ M3 and required to control the external personal computer through the AHB bus, converting the instruction data format, and transferring the converted instruction data format to the external personal computer through the DMA channel. Similarly, data from an external personal computer also enters the ARM chip through the DMA channel, and is sent to Cortex _ M3 for operation after being sent to USART through the AHB bus for data processing. The reason why the DMA channel is independent of the Cortex _ M3 is that the device connected to the DMA channel does not occupy the Cortex _ M3 resource when processing data, and the two devices operate independently, thereby reducing the burden of the Cortex _ M3 during operation. The communication module is also a transmission receiver, but in the invention, the function is to transmit and receive information by the ARM chip and the FPGA chip.

An FPGA chip is an Application Specific Integrated Circuit (ASIC) and is a semi-custom circuit. After describing a logic circuit with specific functions by hardware description language, the user can rapidly burn the logic circuit to FPGA chip after the conversion of hardware description language software (such as Verilog) logic summation, layout, interpretation and wiring software, so as to enable and operate the logic circuit. At other times, if the user needs to change or modify the function of the logic circuit, the hardware description language can be modified, and then the new logic circuit can be enabled and operated by converting the logic summation, the layout and the wiring software again. Therefore, if the function of the circuit is changed, the circuit can be realized without changing hardware in the circuit, and the operation is convenient and quick. The invention uses the advantages, when the number of BLDC to be controlled is changed, the Hall code disc data and the motor control value of the brushless DC motor are captured and stored by changing the content of hardware description language (program code) and using the characteristics of the FPGA chip, after the program is programmed on site, the number of BLDC to be controlled can be increased without changing the hardware architecture again and again, and the invention is very convenient. In the present invention, a user can program a control command required by the user through a hardware description language in a user side device (not shown in fig. 3) and burn the control command into an FPGA chip, so as to implement control of a single BLDC or a plurality of BLDCs.

In the invention, the ARM chip reads the processed Hall code disc data from the FPGA chip through an internal communication module and via another bus (not shown in FIG. 3), and the communication module transmits the processed Hall code disc data to Cortex _ M3 through an AHB bus to be calculated, i.e. interpreted and translated, with other data to obtain a motor control value. The motor control value is then transmitted back to the FPGA chip (a new command is issued) via the AHB bus and an additional bus (not shown in fig. 3), whereby the FPGA chip drives the PWM, the motor driving circuit, and the hall code wheel processing circuit according to the motor control value to control the BLDC operation.

Referring to fig. 3, the integrated system for driving a brushless dc motor further includes a plurality of PWMs, a plurality of motor driving circuits, and a plurality of hall code disc processing circuits. One PWM, one motor driving circuit and one Hall coded disc processing circuit are called as a group of BLDC driving modules. In the present invention, if 3 BLDCs are controlled, 3 sets of BLDC driving modules are required. PWM is a generally conventional pulse width modulation signal generating circuit; the motor driving circuit converts the pulse width modulation signal into a signal which can be read by the BLDC so as to drive the BLDC to operate; the Hall coded disc circuit converts a magnetic signal generated when the BLDC operates into an electric signal containing the rotating speed and the direction so as to process the data by the FPGA chip. According to the driving command from the FPGA chip, the PWM changes a duty cycle of a pulse width modulation signal generated by the PWM chip to change the rotation speed and direction of the BLDC.

Please refer to fig. 4 later. FIG. 4 is a detailed architecture diagram of an ARM chip in an integrated brushless DC motor drive system. The functions and methods of the AHB bus, ADC, Cortex _ M3, USART, communication module, and DMA channel included in the ARM chip have been described in the illustration of fig. 3. The functions of JTAG, TIME timer, SDRAM, memory device, power supply device and I/O module in ARM chip are described. Jtag (joint Test Action group) is a program programming and debugging interface, which is a testing interface, and can be electrically connected to a testing module, for example, an external tester of the present invention, and the hardware and the testing software of the external tester are used to perform a function Test on each module in the ARM chip, so as to detect whether the ARM chip can normally operate and meet the specification. The TIME timer is used for providing accurate timing. The SDRAM is a device that can temporarily store a program to be executed. The memory device is used to store the initial state of each BLDC. The memory device of the invention is formed by adopting Flash. The power supply device is used for maintaining the power of the whole ARM chip, and is also used for maintaining the direct current bias point of the signal of the whole ARM chip. The I/O is an interface for connecting the FPGA chip. In addition, Cortex _ M3 can also control the I/O interface level high-low to realize the function of communicating with the FPGA chip.

In actual operation, Cortex _ M3 obtains signals about TIME, BLDC, external personal computer and FPGA chip from TIME timer, ADC, USART and I/O through AHB bus, and then generates a motor (BLDC) running current value signal through calculation and transmits it to FPGA chip.

Please refer to fig. 3 and fig. 5 together. Fig. 5 shows an architecture diagram of an FPGA chip in the integrated brushless dc motor drive system. The FPGA chip comprises an FPGA communication bus, a Hall counting memory, a code disc counting memory, a PWM register, a Hall signal processing module, a code disc signal processing module and a PWM signal processing module. The FPGA chip 70 and the ARM chip 60 are linked by PCB traces on the circuit board. The hall count memory 702 is used to determine when to commute BLDC 2 based on the hall count. The code wheel count memory 703 is used to implement closed loop control of the BLDC 2 speed according to the code wheel count. Compared with the open loop control mode used in the prior art, the closed loop control has the advantages that the Hall counting memory and the code disc counting memory can not only store code disc counting signals of earlier time, but also store code disc counting signals of current time in real time, so that the code disc counting signals can be referenced in real time to send out more accurate control signals. The PWM register is used for controlling the duty ratio of a signal sent by PWM according to the value of the PWM register. The Hall signal processing module is used for eliminating the problems of noise and interference on Hall signals and realizing accurate phase conversion of BLDC 2. The code wheel signal processing module is used for eliminating the problems of noise and interference on code wheel signals and realizing the accurate control of the speed closed loop of the BLDC 2. The ARM chip is connected with the FPGA chip through a 16-bit bus through a communication module. By transmitting bits at a time, data transmission is made more efficient. In addition, the FPGA communication bus may further be provided with an additional interface (not shown in fig. 5) to receive information transmitted from the client device, and combine with information of the hall count memory and the code wheel count memory for information processing of the PWM signal processing module. Please refer to fig. 3, fig. 5 and fig. 6. Since the PWM is composed of multiple NMOS, these multiple NMOS can be equivalent to multiple switches. A single switch controls the operation of a single BLDC 2. The switches control the operation of a plurality of different BLDC 2. Wherein closing a single switch causes a single BLDC 2 to rotate, and opening a single switch causes a single BLDC 2 to stall. In other words, a single PWM signal processing module signaling a logic 1 may cause a single BLDC 2 to rotate, while a single PWM signal processing module signaling a logic 0 may cause a single BLDC 2 to stall. The single PWM signal processing module can refer to information transmitted from a Hall counting memory, a code disc counting memory and a user terminal device for operation and then sends out the BLDC current value. Controlling the on-time and the off-time of the PWM, that is, controlling the duration of the PWM signal processing module sending out the logic 1 signal and the duration of the PWM signal processing module sending out the logic 0 signal, can achieve controlling the on-off ratio of the PWM signal sent out by the PWM. Moreover, since the PWM is composed of NMOS, the NMOS itself has operation delay, so that the signal sent by the FPGA chip and the signal running on BLDC 2 will not be generated simultaneously, which results in τ 3 and τ 4 as shown in fig. 6. However, the maximum value of τ 3 and τ 4 does not exceed 0.02us, and is still smaller than the synchronization specification, which conforms to the definition of synchronization in the industry. And the values of tau 3 and tau 4 are far smaller than the time difference of the BLDC current value emitted when the traditional FPGA chip is not used. Therefore, the FPGA chip of the invention can keep the BLDC current value synchronous with the motor operation.

In addition, a single PWM signal processing module is also composed of multiple NMOS, and these multiple NMOS can also be equivalent to one switch. In the present invention, a single PWM can be controlled when a single switch is closed, and control of the individual PWM is lost when the single switch is open. In the present invention, if three PWMs are controlled to operate at a time, the PWM signal processing module has a Master (Master) switch and three slave (slave) switches, each of which is composed of an NMOS, one Master switch is coupled to the PWM register and the three slave switches, and one slave switch is coupled to one PWM. Because of manufacturing variations among the slave switches, the switch closing times of the slave switches will vary, allowing different values of the BLDC current to be emitted at different times. However, since the starting time of any two slave switches only differs by 0.2us at most, the method conforms to the definition of synchronization in the industry and is far smaller than the BLDC current value emitting time difference emitted when the traditional FPGA chip is not used. Therefore, with the FPGA chip of the present invention, the plurality of BLDC current values generated are synchronized.

By using the brushless direct current motor driving integration system provided by the invention, the FPGA chip is used as a control center, a plurality of BLDCs can be driven, and a plurality of ARM chips can be integrated in one integrated circuit driving chip, so that the system not only occupies small space, but also can be configured to drive more than 6 BLDCs in time synchronization, and can be connected with more than 36 PWM signals at one time. In addition, the input and output delay time of signals is reduced through an NMOS in the FPGA chip, the input and output delay time is smaller than an ms level and reaches a mu s level, and the brushless direct current motor driving module has higher competitiveness than the existing brushless direct current motor driving module.

The execution flow of the brushless DC motor driving method of the present invention is disclosed in FIG. 7 and FIG. 8. In the present invention, the brushless dc motor driving method includes a general driving program and a determination program, fig. 7 shows a flowchart for executing the general driving program, and fig. 8 shows a flowchart for executing the determination program. Please refer to fig. 7, and refer to the following general driver to perform the detailed description of steps S1-S6.

Step S1: and simultaneously receiving and processing a plurality of Hall code disc data from a plurality of BLDCs by utilizing the FPGA chip. Step S2 is performed subsequently.

Step S2: and storing the processed Hall code disc data into a Hall counting memory and a code disc counting memory in the FPGA chip. Step S3 is performed subsequently.

Step S3: and reading Hall coded disc data stored in the FPGA chip by utilizing the ARM chip. Step S4 is performed subsequently.

Step S4: and collecting a plurality of BLDC current value data in the brushless direct current motor, and transmitting the BLDC current value data to the ARM chip. Step S5 is performed subsequently.

Step S5: and the ARM chip is used for operating the Hall code disc data and the BLDC current value data to generate a motor control value and sending the motor control value to the FPGA chip. The motor control value is obtained by applying a PWM signal processing module to execute the formula as shown in the formula (1):

pwm + (Kp [ e (k) -e (k-1) ] + Ki × e (k) + Kd [ e (k) -2e (k-1) + e (k-2) ], formula (1)

Kp represents the PID coefficient P, Ki represents the PID coefficient i, Kd represents the PID coefficient d, and the three are all fixed correction coefficients of the machine. e (k) represents the deviation of the BLDC current value output for the current time and the BLDC output threshold current, e (k-1) represents the deviation of the BLDC current value output for the last time and the BLDC output threshold current, e (k-2) represents the deviation of the BLDC current value output for the second last time and the BLDC output threshold current, and pwm represents the BLDC current value output for the current time. Therefore, the closed loop circuit design of the present invention can calculate the actual BLDC current value output this time by considering the BLDC current deviation value output this time and two previous times. Step S6 is performed subsequently.

Step S6: and converting the motor control value into a plurality of motor control signals by using an FPGA chip so as to control the BLDC. The generic driver is subsequently ended.

Finally, referring to fig. 8, fig. 8 is a flow chart showing the execution of the determination procedure. And reference is made to the following description of the general driver performing steps T1-T8.

Step T1: and simultaneously receiving and simultaneously processing a plurality of Hall code disc data from a plurality of BLDCs at the first time by utilizing the FPGA chip, and simultaneously generating a plurality of processed Hall code disc data. Step T2 follows.

Step T2: and storing the processed Hall code disc data into a Hall counting memory in the FPGA chip. Step T3 follows.

Step T3: and the ARM chip reads a plurality of processed Hall code disc data from the FPGA chip. Step T4 follows.

Step T4: a plurality of BLDC current value data in a plurality of BLDCs is collected using an ADC. Step T5 follows.

Step T5: it is determined whether the BLDC current value data exceeds a threshold current. If yes, proceed to step T8. If not, the process proceeds to step T6.

Step T6: and transmitting the BLDC current value data which is not 0 back to the ARM chip, obtaining a motor control value which is not 0 by utilizing the operation of the ARM chip, and transmitting the motor control value back to the FPGA chip. Step T7 follows.

Step T7: and converting the motor control value into a motor control signal by using an FPGA chip so as to synchronously control the brushless direct current motor. Subsequently, the determination process is ended.

Step T8: and directly converting the BLDC current value data into 0 by using the ADC and transmitting the 0 back to the ARM chip, obtaining a motor control value of 0 by using the ARM chip for operation, and transmitting the motor control value back to the FPGA chip so as to turn off the brushless direct current motor. Subsequently, the determination process is ended.

By using the driving method of the brushless direct current motor provided by the invention, at least 6 BLDCs can be synchronously controlled, whether the current of the driving chip is overloaded can be judged, and the chip is automatically switched off (disable) when the current is overloaded, so that the driving chip and the BLDCs are protected in real time; the method further comprises a feedback program, and the BLDC rotating speed can be dynamically adjusted in real time to stabilize the BLDC rotating speed, so that the method has the advantages of taking a complete number.

The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; while the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A method for driving a brushless DC motor, comprising:

utilizing an FPGA chip to simultaneously receive and process a plurality of Hall coded disc data from a plurality of brushless direct current motors and store the data into a Hall counting memory and a coded disc counting memory in the FPGA chip;

reading the Hall coded disc data stored in the FPGA chip by utilizing an ARM chip;

collecting a plurality of BLDC current value data in the brushless direct current motor, and transmitting the BLDC current value data to the ARM chip;

the ARM chip is used for calculating the Hall code disc data and the BLDC current value data to generate a motor control value and sending the motor control value to the FPGA chip;

and converting the motor control value into a plurality of synchronous motor control signals by using the FPGA chip so as to control the brushless direct current motor.

2. The brushless dc motor driving method according to claim 1, wherein: the motor control value is specifically calculated as follows:

pwm+＝Kp[e(k)-e(k-1)]+Ki*e(k)+Kd[e(k)-2e(k-1)+e(k-2)]

kp represents a coefficient P of the PID, Ki represents a coefficient i of the PID, Kd represents a coefficient d of the PID, the three coefficients are fixed correction constants of the machine, e (k) represents the deviation of the BLDC current value output in the current scheduled time and the BLDC output threshold current, e (k-1) represents the deviation of the BLDC current value output in the last time and the BLDC output threshold current, e (k-2) represents the deviation of the BLDC current value output in the last time and the BLDC output threshold current, and pwm represents the BLDC current value output in the current time.

3. The brushless dc motor driving method according to claim 1, wherein:

the ARM chip is used for reading the Hall coded disc data in the FPGA chip through a bus, and then calculating according to the Hall coded disc data to obtain a motor control value, and the motor control value is transmitted back to the FGPA chip through the bus; and

the FPGA chip is used for receiving the motor control value sent by the ARM chip and storing Hall code disc data of the brushless direct current motor, and the FPGA chip is provided with a plurality of NMOSs;

the FPGA chip controls the corresponding NMOS to be opened or closed according to the motor control value so as to send out a BLDC current value, and therefore the brushless direct current motor is driven in a time synchronization mode.

4. The brushless dc motor driving method according to claim 1, wherein: the ARM chip internally includes an ADC that converts the data format of the BLDC current value data collected by an analog circuit from an analog format to a digital format.

5. The brushless dc motor driving method according to claim 1, wherein: the ARM chip internally comprises an AHB, all modules carry out data transmission and mutual communication through the AHB, and the data transmission and mutual communication in the ARM chip are in a 32-bit data form.

6. The brushless dc motor driving method according to claim 4, wherein: comprising the following steps T1 to T8,

step T1: simultaneously receiving and simultaneously processing a plurality of Hall code disc data from a plurality of BLDCs at the first time by utilizing an FPGA chip, simultaneously generating a plurality of processed Hall code disc data, and subsequently performing the step T2;

step T2: storing the processed Hall code disc data into a Hall counting register in an FPGA chip, and subsequently performing the step T3;

step T3: the ARM chip reads a plurality of processed Hall code disc data from the FPGA chip, and then the step T4 is carried out;

step T4: acquiring a plurality of BLDC current value data among the plurality of BLDCs using the ADC, followed by step T5;

step T5: judging whether the BLDC current value data exceeds a threshold current, if so, subsequently performing a step T8, and if not, subsequently performing a step T6;

step T6: transmitting the BLDC current value data which is not 0 back to the ARM chip, obtaining a motor control value which is not 0 by utilizing the operation of the ARM chip, transmitting the motor control value back to the FPGA chip, and subsequently performing the step T7;

step T7: converting the motor control value into a motor control signal by using an FPGA chip so as to synchronously control the brushless direct current motor;

step T8: and directly converting the BLDC current value data into 0 by using the ADC and transmitting the 0 back to the ARM chip, obtaining a motor control value of 0 by using the ARM chip for operation, and transmitting the motor control value back to the FPGA chip so as to turn off the brushless direct current motor.