CN112884678A - Debugging method and system of image algorithm - Google Patents
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Abstract
The invention provides a debugging method and a debugging system of an image algorithm, which relate to the technical field of image algorithms, the debugging system comprises a digital image processing system and an image algorithm debugging system, the digital image processing system comprises an image algorithm processing subsystem, a data transmission subsystem and an upper computer for data processing, the image algorithm processing subsystem comprises a storage module, an arithmetic unit and a control module, the data transmission subsystem comprises an asynchronous FIF0 data transmission module and a serial port communication module, a Field Programmable Gate Array (FPGA) is adopted, the FPGA has high-speed and parallel processing performance and has the advantages of programmability, high integration degree, high reliability and the like, a designer can modify configuration information to complete corresponding functions according to the functions of the system designed by the designer so as to meet the design requirements of the designer, and the FPGA can complete corresponding circuit logic function design through schematic diagram design or hardware language programming.
Description
Technical Field
The invention relates to the technical field of image algorithms, in particular to a debugging method and a debugging system of an image algorithm.
Background
Digital image processing is closely related to the development of computer, multimedia, intelligent robot, expert system and other technologies. With the rapid development trend of intelligent technology of computers in the aspect of processing images, the technology field irrelevant to the digital image processing technology almost does not exist, for example, the method is applied to the fields of life science, satellite remote sensing, aerospace, industry, military public safety and the like. Therefore, the design of digital image processing systems with features of real-time performance and high efficiency becomes more and more important, and the traditional design of digital image processing systems by software cannot meet the needs of designers well. On the other hand, with the rapid development of semiconductor technology, silicon processing technology in the deep submicron (less than 30nm) field has been entered, and the design that millions or even tens of millions of gate-level circuits are integrated on one chip can be realized, so that the problem of speed which is difficult to break through in digital image processing technology can be well solved by using various hardware development tools.
The digital image processing has huge data volume, and when processing an image, the algorithm execution time is long, so the algorithm is very necessary for realizing a high-performance image processing system, but the traditional image algorithm has low speed, low precision, large workload and low efficiency.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a debugging method and a debugging system of an image algorithm, and solves the problems of low speed, low accuracy, large workload and low efficiency of the traditional image algorithm.
In order to achieve the purpose, the invention is realized by the following technical scheme: a method and a system for debugging an image algorithm comprise a digital image processing system and an image algorithm debugging system, wherein the digital image processing system comprises an image algorithm processing subsystem, a data transmission subsystem and an upper computer for data processing, the image algorithm processing subsystem comprises a storage module, an arithmetic unit and a control module, the data transmission subsystem comprises an asynchronous FIF0 data transmission module and a serial port communication module, and the image algorithm processing subsystem comprises the following operation steps:
a storage module: storing gray image data prepared in advance;
an arithmetic unit: reading digital image gray data in the stored ROM, realizing digital image algorithm and outputting data;
a control module: the controllable unit reads data from the ROM in cooperation with the arithmetic unit, and controls the arithmetic unit to implement an image processing algorithm.
Preferably, the operation step of the asynchronous FIFO data transmission module of the data transmission subsystem is:
write digital circuitry: an address generation logic module;
a reading digital circuit: the address generation logic module is used for designing a synchronous detection module by reading and writing digital circuit addresses;
dual port ROM module: when the rising edge of the write clock comes, under the control of a write signal, the data writing operation is carried out on the ROM; when the rising edge of the read clock comes, the read data operation is carried out on the ROM under the control of the read signal. The algorithm of the image debugging system comprises a linear spatial filter, a nonlinear spatial filter, a maximum filter and a minimum filter, a new pixel is generated through filtering, the pixel value is the pixel value of the corresponding position in the newly created image, the center of the filter accesses each pixel in the input image, the digital image after filtering processing is obtained, and the optimal filtering algorithm is obtained.
Preferably, the linear spatial filter adopts a standard mean filter template through a mean filtering algorithm, the resolution is in the range of [ 0.1%, 1% ], 10 different gaussian noise concentrations with 0.1% as an interval are used, and the mean filtering algorithm is realized in three ways: the method comprises the steps of realizing a mean value filtering algorithm based on matlab, realizing a mean value filtering algorithm based on an FPGA single template and realizing a mean value filtering algorithm based on an FPGA parallel dual-template, recording three modes to process a digital image, and judging the digital image through the values of mean square error, peak signal-to-noise ratio, improved signal-to-noise ratio and mean absolute error.
Preferably, the nonlinear spatial filter adopts a fast median filter experiment, adopts a 3 × 3 median filter template, adopts 3-level comparison to output a median, the input data of the median is gray image data covered by a filter mask, 10 different salt and pepper noise concentrations at intervals of 3% in the range of [ 1%, 28% ] are added to the Lena image with the resolution of 192.192, 10 experiments are performed, and the mean filtering algorithm is realized in three ways: the method comprises the steps of realizing a rapid median filtering algorithm based on matlab, realizing a rapid median filtering algorithm based on an FPGA single template and realizing a rapid median filtering algorithm based on an FPGA parallel dual-template, recording three modes to process a digital image, and judging the digital image through the values of mean square error, peak signal-to-noise ratio, improved signal-to-noise ratio and average absolute error.
Preferably, the maximum filter and the minimum filter use maximum and minimum filter templates of 3 × 3 windows, and 10 different noise concentrations of pepper and salt grains are added to the Lena image with the resolution of 192.192 at intervals of 3% within the range of [ 1%, 28% ], and 10 experiments are performed to complete the mean filtering algorithm in three ways: the method comprises the steps of realizing a maximum value and minimum value filtering algorithm based on matlab, realizing a maximum value and minimum value filtering algorithm based on an FPGA single template and realizing a maximum value and minimum value filtering algorithm based on an FPGA parallel dual-template, recording three modes to process a digital image, and judging values through a mean square error, a peak signal-to-noise ratio, an improved signal-to-noise ratio and an average absolute error.
Preferably, the spatial filtering algorithm implementation based on matlab, the spatial filtering algorithm implementation based on the FPGA single template and the spatial filtering algorithm implementation based on the FPGA parallel dual-template are realized by recording the values of the mean square error, the peak signal-to-noise ratio, the improved signal-to-noise ratio and the average absolute error and the operation time of the algorithm of the digital image processing in three modes, and the spatial filtering algorithm based on the FPGA parallel dual-template is better debugged through comparison verification.
The invention also provides a debugging method of the image algorithm, which is applied to the system and comprises the following steps: acquiring video data processed by an image algorithm; analyzing the video data to determine whether the image algorithm needs to be adjusted according to the analysis result; and marking the analysis result or marking the analysis result and the adjustment result in the video data, and outputting the marked video data to a display.
The invention provides a debugging method and a debugging system of an image algorithm, which have the following beneficial effects:
1. the invention adopts the Field Programmable Gate Array (FPGA), which has high speed and parallel processing performance, and also has the advantages of programmability, high integration degree, high reliability and the like, a designer can modify configuration information to complete corresponding functions according to the functions of the system designed by the designer so as to meet the design requirements of the designer, the FPGA can complete corresponding circuit logic function design through schematic diagram design or hardware language programming, and then an I/O port corresponding to ten thousand square data is arranged, the design is actually carried out on an FPGA chip, compared with the traditional circuit design method, the FPGA realizes the characteristics of programmability, high speed and parallel execution, and simultaneously has high reliability, the original circuit board design idea is changed, and the stability, workload, difficulty, effectiveness, flexibility and efficiency of the circuit system design are greatly improved to realize the image processing algorithm based on the FPGA parallel double-mode board, on the premise of ensuring the image processing precision, experiments verify that the optimization of the strategy on the image processing algorithm implementation mode in time is feasible.
2. The invention adopts a general image algorithm processing system capable of repeated configuration, the system is composed of a plurality of modules which are independent to each other and have a certain specific function, when the function of a certain module needs to be further improved, the corresponding part of the module is modified, the modification scheme which needs to be ensured to be correct and feasible can not influence other modules in the whole system, and because the system has universality and repeated configuration, the system provides great convenience for the research of the text, and reduces the workload of realizing the image processing algorithm hardware.
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FIG. 1 is a schematic diagram of the system of the present invention;
FIG. 2 is a flow diagram of a bit data transfer module.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The first embodiment is as follows:
as shown in fig. 1, an image algorithm debugging system includes a digital image processing system and an image algorithm debugging system, the digital image processing system includes an image algorithm processing subsystem, a data transmission subsystem, and an upper computer data processing, the image algorithm processing subsystem includes a storage module, an arithmetic unit, and a control module, the data transmission subsystem includes an asynchronous FIF0 data transmission module and a serial port communication module, and the image algorithm processing subsystem executes the following steps: storing gray image data prepared in advance by a storage module; the arithmetic unit reads the stored digital image gray data in the ROM, the realization of the digital image algorithm and the output of the data; the controllable unit of the control module is matched with the arithmetic unit to read data from the ROM, and the arithmetic unit is controlled to realize the image processing algorithm.
The FPGA can complete corresponding circuit logic function design through schematic diagram design or hardware language programming, and then an I/O port corresponding to ten thousand square data is arranged, the design is actually carried out on an FPGA chip, compared with the traditional circuit design method, the FPGA has the characteristics of programmability, high speed and parallel execution, and simultaneously has high reliability, the original circuit board design idea is changed, and the image processing algorithm based on the FPGA parallel board is greatly improved on the stability, workload, difficulty, effectiveness, double-mode, flexibility and efficiency of the circuit system design, on the premise of ensuring the image processing precision, experiments verify that the optimization of the strategy on the image processing algorithm implementation mode in time is feasible.
The operation steps of the asynchronous FIFO data transmission module of the data transmission subsystem are as follows:
sp 1: a write digital circuit address generation logic module;
sp 2: a read word circuit address generation logic module;
sp 3: designing a synchronous detection module by reading and writing digital circuit addresses;
sp 4: selecting a dual-port ROM module, and performing data writing operation on the ROM under the control of a write signal when the rising edge of a write clock comes; when the rising edge of the read clock comes, the read data operation is carried out on the ROM under the control of the read signal. The algorithm of the image debugging system comprises a linear spatial filter, a nonlinear spatial filter, a maximum filter and a minimum filter, a new pixel is generated through filtering, the pixel value is the pixel value of the corresponding position in the newly created image, the center of the filter accesses each pixel in the input image, the digital image after filtering processing is obtained, and the optimal filtering algorithm is obtained.
The linear spatial filter adopts a standard mean filter template through a mean filtering algorithm, the resolution ratio is in the range of [ 0.1%, 1% ], 10 different Gaussian noise concentrations with 0.1% as intervals are used, and the mean filtering algorithm is realized by three modes: the method comprises the steps of realizing a mean value filtering algorithm based on matlab, realizing a mean value filtering algorithm based on an FPGA single template and realizing a mean value filtering algorithm based on an FPGA parallel dual-template, recording three modes to process a digital image, and judging the digital image through the values of mean square error, peak signal-to-noise ratio, improved signal-to-noise ratio and mean absolute error.
The nonlinear spatial filter adopts a 3 x 3 median filter template in a rapid median filter experiment, adopts 3-level comparison to output a median, input data of the nonlinear spatial filter is gray image data covered by a filter mask, 10 different salt and pepper noise concentrations which take 3% as intervals in the range of [ 1%, 28% ] are added to a Lena image with the resolution of 192.192, 10 experiments are carried out, and the mean filtering algorithm is realized in three modes: the method comprises the steps of realizing a rapid median filtering algorithm based on matlab, realizing a rapid median filtering algorithm based on an FPGA single template and realizing a rapid median filtering algorithm based on an FPGA parallel dual-template, recording three modes to process a digital image, and judging the digital image through the values of mean square error, peak signal-to-noise ratio, improved signal-to-noise ratio and average absolute error.
The maximum filter and the minimum filter adopt maximum and minimum filter templates of 3 × 3 windows, 10 different pepper and salt particle noise concentrations at intervals of 3% within the range of [ 1%, 28% ] are respectively added to the Lena image with the resolution of 192.192, 10 experiments are carried out, and the mean filtering algorithm is realized in three modes: the method comprises the steps of realizing a maximum value and minimum value filtering algorithm based on matlab, realizing a maximum value and minimum value filtering algorithm based on an FPGA single template and realizing a maximum value and minimum value filtering algorithm based on an FPGA parallel dual-template, recording three modes to process a digital image, and judging values through a mean square error, a peak signal-to-noise ratio, an improved signal-to-noise ratio and an average absolute error.
The method is characterized by comprising the following steps of realizing a spatial filtering algorithm based on matlab, realizing a spatial filtering algorithm based on an FPGA single template and realizing a spatial filtering algorithm based on an FPGA parallel dual-template, processing digital images by recording three modes, namely mean square error, peak signal-to-noise ratio, improving the signal-to-noise ratio and the value of the mean absolute error and the running time of the algorithm, and verifying that the debugging of the spatial filtering algorithm based on the FPGA parallel dual-template is better by comparison.
The spatial filter consists of a neighborhood (typically a small rectangle) on which predefined operations are performed on the image pixels enclosed by the neighborhood, often also referred to as a spatial mask, kernel, template, or window. And filtering to generate a new pixel, wherein the pixel value is the pixel value of the corresponding position in the newly created image, and the center of the filter accesses each pixel in the input image to obtain the digital image after filtering processing. A linear spatial filter refers to a spatial filter that performs algorithmic processing of an image by linear operations, whereas if non-linear operations are performed, the filter is a non-linear spatial filter. The nonlinear spatial filter, also commonly referred to as a statistical ordering filter, has an output response based on the ordering of the pixels contained in the image region covered by the filter template, and then replaces the value of the center pixel with the value determined by the statistical ordering result.
The universal and reconfigurable image algorithm processing system is adopted, the system is composed of a plurality of mutually independent modules with certain specific functions, when the functions of a certain module are required to be further improved, the corresponding parts of the modules are required to be modified, the modification scheme required to be ensured to be correct and feasible can not influence other modules in the whole system, and the system has universality and reconfigurable performance, thereby providing great convenience for the research of the text and reducing the workload of realizing the image processing algorithm hardware.
The debugging method of the image algorithm comprises the following steps: firstly, acquiring video data processed by an image algorithm; secondly, analyzing the video data to determine whether the image algorithm needs to be adjusted according to the analysis result; and thirdly, marking the analysis result or marking the analysis result and the adjustment result in the video data, and outputting the marked video data to a display.
The debugging device of the image algorithm comprises: the server internally comprises an information storage module, an information receiving module, an information sending module and a video analysis module, video information in the information storage module is analyzed through the video analysis module, videos are transmitted to the display screen of the upper computer, and image information is debugged through a debugging method.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a reference structure" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. The debugging system of an image algorithm is characterized by comprising a digital image processing system and an image algorithm debugging system, wherein the digital image processing system comprises an image algorithm processing subsystem, a data transmission subsystem and an upper computer for data processing, the image algorithm processing subsystem comprises a storage module, an operation unit and a control module, and the data transmission subsystem comprises an asynchronous FIF0 data transmission module and a serial port communication module;
the image algorithm processing subsystem comprises: the storage module is used for storing pre-prepared gray image data;
the arithmetic unit is used for reading the stored digital image gray data in the ROM, realizing the digital image algorithm and outputting the data;
and the control module is used for reading data from the ROM in cooperation with the operation unit and controlling the operation unit to realize an image processing algorithm.
2. The debugging system for image algorithm according to claim 1, wherein the asynchronous FIFO data transmission module of the data transmission subsystem comprises: the digital reading and writing circuit is used for reading and writing the digital circuit address and designing a synchronous detection module;
dual port ROM module: when the rising edge of the write clock comes, under the control of a write signal, the data writing operation is carried out on the ROM; when the rising edge of the read clock comes, the read data operation is carried out on the ROM under the control of the read signal.
3. The debugging system of an image algorithm according to claim 1, wherein: the algorithm of the debugging system comprises a linear spatial filter, a nonlinear spatial filter, a maximum filter and a minimum filter, a new pixel is generated through filtering, the pixel value is the pixel value of the corresponding position in the newly created image, the center of the filter accesses each pixel in the input image, the digital image after filtering processing is obtained, and the optimal filtering algorithm is obtained.
4. A debugging system for image algorithm according to claim 3, characterized in that: the linear spatial filter adopts a standard mean filter template through a mean filtering algorithm, the resolution ratio is in the range of [ 0.1%, 1% ], 10 different Gaussian noise concentrations with 0.1% as intervals are used, and the mean filtering algorithm is realized by three modes: the method comprises the steps of realizing a mean value filtering algorithm based on matlab, realizing a mean value filtering algorithm based on an FPGA single template and realizing a mean value filtering algorithm based on an FPGA parallel dual-template, recording three modes to process a digital image, and judging the digital image through the values of mean square error, peak signal-to-noise ratio, improved signal-to-noise ratio and mean absolute error.
5. A debugging system for image algorithm according to claim 3, characterized in that: the nonlinear spatial filter adopts a 3 x 3 median filter template in a rapid median filter experiment, adopts 3-level comparison to output a median, input data of the nonlinear spatial filter is gray image data covered by a filter mask, 10 different salt and pepper noise concentrations which take 3% as intervals in the range of [ 1%, 28% ] are added to a Lena image with the resolution of 192.192, 10 experiments are carried out, and the mean filtering algorithm is realized in three modes: the method comprises the steps of realizing a rapid median filtering algorithm based on matlab, realizing a rapid median filtering algorithm based on an FPGA single template and realizing a rapid median filtering algorithm based on an FPGA parallel dual-template, recording three modes to process a digital image, and judging the digital image through the values of mean square error, peak signal-to-noise ratio, improved signal-to-noise ratio and average absolute error.
6. A debugging system for image algorithm according to claim 3, characterized in that: the maximum filter and the minimum filter adopt maximum and minimum filter templates of 3 × 3 windows, 10 different pepper and salt particle noise concentrations which are 3% at intervals in the range of [ 1%, 28% ] are respectively added to the Lena image with the resolution of 192.192, 10 experiments are carried out, and the mean filtering algorithm is realized in three modes: the method comprises the steps of realizing a maximum value and minimum value filtering algorithm based on matlab, realizing a maximum value and minimum value filtering algorithm based on an FPGA single template and realizing a maximum value and minimum value filtering algorithm based on an FPGA parallel dual-template, recording three modes to process a digital image, and judging values through a mean square error, a peak signal-to-noise ratio, an improved signal-to-noise ratio and an average absolute error.
7. The debugging system for image algorithm according to claim 5, wherein: the spatial filtering algorithm implementation based on matlab, the spatial filtering algorithm implementation based on the FPGA single template and the spatial filtering algorithm implementation based on the FPGA parallel dual-template process the digital image by recording three modes, namely the mean square error, the peak signal-to-noise ratio, the values of improving the signal-to-noise ratio and the mean absolute error and the operation time of the algorithm, and the comparison verifies that the spatial filtering algorithm based on the FPGA parallel dual-template is better debugged.
8. A method for debugging an image algorithm, applied to the system according to any of claims 1 to 7, the method comprising:
acquiring video data processed by an image algorithm;
analyzing the video data to determine whether the image algorithm needs to be adjusted according to the analysis result;
and marking the analysis result or marking the analysis result and the adjustment result in the video data, and outputting the marked video data to a display.
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| US20080152248A1 (en) * | 2006-12-22 | 2008-06-26 | Kelly Sean C | Reduction of position dependent noise in a digital image |
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