CN112882754A - Function calling method and processor - Google Patents
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- CN112882754A CN112882754A CN201911205836.4A CN201911205836A CN112882754A CN 112882754 A CN112882754 A CN 112882754A CN 201911205836 A CN201911205836 A CN 201911205836A CN 112882754 A CN112882754 A CN 112882754A
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Abstract
The application provides a function calling method and a processor. In the method, first, a first processor determines a second processor to which a function to be operated belongs, and the first processor acquires various pieces of information of multi-level pointer parameters and sends the information to the second processor through a first network message; then, the second processor receives the first network message sent by the first processor, and analyzes the first network message to obtain various information of the multi-level pointer parameter; secondly, reconstructing the multi-level pointer parameters according to the analyzed various information of the multi-level pointer parameters and the information of the function to be operated; and finally, the second processor returns the calling result and the result of the function to be run to the first processor through a second network message. The method can effectively solve the problem that the traditional function calling method can not realize cross-processor function calling containing multi-level pointer parameters.
Description
Technical Field
The embodiment of the application relates to the technical field of computers, in particular to a function calling method and a processor.
Background
In a computing device, there may be multiple processors. The plurality of processors work in concert to implement the computing functionality of the computing device. Typically, during the execution of a program by a processor, a need arises to call functions in other processors.
In conventional function call methods, the processor only supports calls for functions that contain a shaping parameter, a string parameter, and a single level pointer parameter. Wherein all pointer variables in the single-level pointer parameter point to addresses.
Because the data lengths of the parameters are known, when determining that the functions need to be called, the processor a can directly notify the processor B of the data lengths of the parameters included in the functions, and the processor B can allocate memory addresses to the parameters according to the obtained data lengths, thereby running the functions. After the processor B runs the function to obtain the running result, the running result is notified to the processor A, so that the processor A can complete the function call.
However, some functions may involve multi-level pointer parameters, in which at least one pointer variable points to another pointer variable, and the addresses of the two processors are independent. Obviously, even if the processor a sends the multi-level pointer parameter to the processor B by using the above method, the processor B cannot determine the pointing relationship of the pointer variable in the multi-level pointer parameter, and thus cannot run the function including the multi-level pointer parameter. Therefore, the conventional function calling method is adopted to realize the function calling which is cross-processor and contains multi-level pointer parameters.
Therefore, there is a need in the art to provide a function call method that can implement a cross-processor function that includes multiple levels of pointer parameters.
Disclosure of Invention
The embodiment of the invention provides a function calling method, which is used for realizing cross-processor function calling containing multi-layer pointer parameters.
The embodiment of the invention provides the following specific technical scheme:
in a first aspect, an embodiment of the present application provides a function call method, where the method may be applied to a computing device having multiple processors, and the method specifically includes the following steps:
the first processor determines a second processor to which the function to be run belongs;
the first processor determines that the function to be run comprises a plurality of levels of pointer parameters, wherein the plurality of levels of pointer parameters comprise a plurality of pointer variables, and at least one pointer variable in the plurality of pointer variables points to other pointer variables;
the first processor acquires the structural information of the multi-level pointer parameter and stores the structural information into a cache with continuous addresses; wherein the structural information is used to characterize: the number of pointer variables, the variable information of each pointer variable and the pointing relationship among the pointer variables contained in the multi-level pointer parameter; the variable information of any pointer variable includes the length and the first address of the pointer variable;
the first processor acquires the number of pointer variables contained in the multi-level pointer parameter and the variable information of each pointer variable from the structure information;
the first processor sends a first network message to the second processor, wherein the first network message comprises: the structure information of the multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, the variable information of each pointer variable, and the information of the function to be run;
and the first processor receives a second network message sent by the second processor, wherein the second network message comprises an operation result of the second processor on the function to be operated.
According to the method, when a function call containing the multi-level pointer parameter is carried out between two processors, the first processor stores the related content of the called multi-level pointer parameter in the first network message according to the corresponding format, the first processor sends the first network message to the second processor, and the second processor analyzes the first network message so as to execute the function call and return the call execution result to the first processor through the second network message, so that the function call containing the multi-level pointer parameter across the processors is effectively realized.
In one possible implementation manner, the first processor determines that the function to be run includes a multi-level pointer parameter, and the method includes:
when the first processor determines that the function to be run comprises the specified parameter, and when the first processor determines that the length of the specified parameter is greater than or equal to the set length, the first processor determines that the function to be run comprises the multi-level pointer parameter.
By the method, the first processor can determine the pointer parameter contained in the function to be run as the multi-level pointer parameter.
In one possible implementation, the pointing relationship between the pointer variables includes:
the number of pointing relationships between pointer variables;
the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
In a second aspect, an embodiment of the present application further provides a function calling method, which is applied to a computing device having multiple processors, and the method includes:
the second processor receives a first network message sent by the first processor, wherein the first network message comprises: the method comprises the following steps of obtaining structure information of multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, variable information of each pointer variable and information of a function to be run; wherein the structural information is used to characterize: the number of pointer variables, the variable information of each pointer variable and the pointing relationship among the pointer variables contained in the multi-level pointer parameter; the variable information of any pointer variable includes the length and the first address of the pointer variable; the second processor stores the structure information of the multi-level pointer parameter into a cache with continuous addresses;
the second processor determines the absolute address offset of each pointer variable in the multi-level pointer parameters according to the number of pointer variables contained in the multi-level pointer parameters contained in the first network message and the variable information of each pointer variable;
the second processor calculates the address of a source pointer variable and the address of a destination pointer variable in the direction relation between each pointer variable according to the direction relation between the pointer variables in the structure information of the multi-level pointer parameter and the absolute address offset of each pointer variable;
the second processor assigns the address of the target pointer variable in the direction relation between each pointer variable to the source pointer, and reconstructs the multi-level pointer parameters according to the structural information of the multi-level pointer parameters;
the second processor operates the function to be operated according to the information of the function to be operated and the reconstructed multi-level pointer parameters to obtain an operation result;
and the second processor sends a second network message to the first processor, wherein the second network message comprises the operation result.
In one possible implementation, the pointing relationship between the pointer variables includes:
the number of pointing relationships between pointer variables;
the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
In one possible implementation manner, the calculating, by the second processor, an address of a source pointer variable and an address of a destination pointer variable in a pointing relationship between each pointer parameter according to a pointing relationship between pointer variables in the structure information of the multi-level pointer parameter and an absolute address offset of each pointer variable includes:
the second processor takes the first address of the structural information of the multi-level pointer parameter in the cache as the first address of the multi-level pointer parameter;
and the second processor calculates the address of the source pointer variable and the address of the destination pointer variable in the direction relationship between the pointer variables according to the initial address of the multi-stage pointer parameter and the absolute address offset of each pointer variable.
In a third aspect, the present application provides a first processor for use in a computing device having a plurality of processors, comprising:
the storage unit is used for caching data;
the processing unit is used for determining a second processor to which the function to be run belongs; determining that the function to be run comprises a plurality of levels of pointer parameters, wherein the plurality of levels of pointer parameters comprise a plurality of pointer variables, and at least one pointer variable in the plurality of pointer variables points to other pointer variables; acquiring the structural information of the multi-level pointer parameter, and storing the structural information into a cache with continuous addresses in the storage unit; wherein the structural information is used to characterize: the number of pointer variables, the variable information of each pointer variable and the pointing relationship among the pointer variables contained in the multi-level pointer parameter; the variable information of any pointer variable includes the length and the first address of the pointer variable; acquiring the number of pointer variables contained in the multi-level pointer parameter and variable information of each pointer variable from the structure information;
a communication unit, configured to send a first network message to the second processor, where the first network message includes: the structure information of the multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, the variable information of each pointer variable, and the information of the function to be run; and receiving a second network message sent by the second processor, wherein the second network message comprises an operation result of the second processor on the function to be operated.
In a possible implementation manner, when determining that the function to be run includes a plurality of levels of pointer parameters, the processing unit is specifically configured to: when the first processor determines that the function to be run comprises the specified parameter, and when the first processor determines that the length of the specified parameter is greater than or equal to the set length, the first processor determines that the function to be run comprises the multi-level pointer parameter.
In one possible implementation, the pointing relationship between the pointer variables includes: the number of pointing relationships between pointer variables; the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
In a fourth aspect, the present application provides a second processor for use in a computing device having a plurality of processors, comprising:
the storage unit is used for caching data;
a communication unit, configured to receive a first network message sent by a first processor, where the first network message includes: the method comprises the following steps of obtaining structure information of multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, variable information of each pointer variable and information of a function to be run; wherein the structural information is used to characterize: the number of pointer variables, the variable information of each pointer variable and the pointing relationship among the pointer variables contained in the multi-level pointer parameter; the variable information of any pointer variable includes the length and the first address of the pointer variable;
a processing unit, configured to store structure information of the multilevel pointer parameter in a cache with consecutive addresses in the storage unit, and determine an absolute address offset of each pointer variable in the multilevel pointer parameter according to the number of pointer variables included in the multilevel pointer parameter included in the first network message and variable information of each pointer variable; calculating the address of a source pointer variable and the address of a destination pointer variable in the pointing relationship between each pointer variable according to the pointing relationship between the pointer variables in the structure information of the multi-stage pointer parameters and the absolute address offset of each pointer variable; assigning the address of a target pointer variable in the direction relation between each pointer variable to a source pointer, and reconstructing the multi-level pointer parameters according to the structural information of the multi-level pointer parameters; running the function to be run according to the information of the function to be run and the reconstructed multi-level pointer parameters to obtain a running result;
the communication unit is further configured to send a second network message to the first processor, where the second network message includes the operation result.
In one possible implementation, the pointing relationship between the pointer variables includes: the number of pointing relationships between pointer variables; the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
In one possible implementation manner, when the processing unit calculates, according to the pointing relationship between the pointer variables in the structure information of the multi-stage pointer parameter and the absolute address offset of each pointer variable, an address of a source pointer variable and an address of a destination pointer variable in the pointing relationship between each pointer variable, the processing unit is specifically configured to:
taking the first address of the structure information of the multi-level pointer parameter in the cache as the first address of the multi-level pointer parameter; and calculating the address of the source pointer variable and the address of the destination pointer variable in the direction relation between the pointer variables according to the initial address of the multistage pointer parameter and the absolute address offset of each pointer variable.
In a fifth aspect, a computing device is provided in this embodiment of the present application, where the computing device is configured to execute the units of the steps in the above aspects.
In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium for storing a computer program, which, when run on an electronic device, causes the electronic device to perform the method provided in the above aspects or any one of the possible implementations.
In a seventh aspect, this application provides, in an embodiment, a computer program which, when run on a computer, causes the computer to perform the method provided in the above aspects or any one of the possible implementations.
In an eighth aspect, embodiments of the present application provide a chip, where the chip is configured to read a computer program stored in a memory, and perform the method according to the foregoing aspects.
Drawings
FIG. 1 is a block diagram of a computing device provided in an embodiment of the present application;
fig. 2 is a flowchart of a function calling method according to an embodiment of the present application;
fig. 3 is a block diagram of a processor a according to an embodiment of the present disclosure;
fig. 4 is a block diagram of a processor B according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be described in further detail with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the application provides a function calling method and device, which are used for solving the problem of function calling of a cross-processor and containing multi-level pointer parameters. The method and the device are based on the same inventive concept, and because the principles of solving the problems of the method and the device are similar, the implementation of the device and the method can be mutually referred, and repeated parts are not repeated.
In the technical scheme of the embodiment of the application, in the process of running a program, when it is determined that a function to be run in the program belongs to a second processor in the computing device and the function to be run includes a multi-level pointer parameter, the first processor may send structure information of the multi-level pointer parameter, the number and information of pointer variables included in the multi-level pointer parameter, and information of the function to be run to the second processor through a first network message; in this way, after receiving the first network message, the second processor may reconstruct the multi-level pointer parameter according to various information therein and operate the function to be operated, thereby obtaining an operation result; and finally, the second processor returns the operation result to the first processor through a second network message. This method may implement a function call across processors that contains multiple levels of pointer parameters.
Some terms in the embodiments of the present application will be explained below to facilitate understanding by those skilled in the art.
1. The computing device is a device with computing function. In the embodiment of the present application, the computing device is a device that realizes a computing function by cooperation of a plurality of processors. Some examples of computing devices are currently: computers, laptops, smart phones, base stations, and the like.
The plurality of processors in the computing device may be located on the same board card or on different board cards, which is not limited in this application.
Optionally, there is one processor a in the plurality of processors, and the program executed by the processor a may include functions belonging to other processors (taking the processor B as an example). When the processor a is running the program, the function needs to be called at the processor a to ensure the running of the program.
Illustratively, the processor a may be a master processor that performs the primary computing functions of the computer, including executing application code, and the processor B may be referred to as a slave processor that assists the master processor.
2. A function is a piece of program code that is grouped together to perform a computation and produce a result. Wherein the function may comprise at least one parameter. The types of parameters may be, but are not limited to: shaping parameters, string parameters, single level pointer parameters, multi-level pointer parameters, etc.
All pointer variables in the single-level pointer parameter point to addresses.
3. The multi-level pointer parameter comprises a plurality of pointer variables, and at least one pointer variable in the plurality of pointer variables points to other pointer variables.
For example: p, where p is a pointer variable, and the combination indicates that the pointer variable points to an address of a pointer variable.
As another example, the pointer structure of the multi-level pointer parameter is multi-level nested. For example: defining a pointer variable q, T q of type T; ≡ (int) × q; ≡ int × q, the variable q is called a secondary pointer variable whose base type is int.
4. A plurality of, at least two.
In addition, it is to be understood that the terms first, second, etc. in the description of the present application are used for distinguishing between the descriptions and not necessarily for describing a sequential or chronological order.
The embodiments of the present application will be described in detail below with reference to the accompanying drawings.
The application provides a structure diagram of a computing device to which a function calling method can be applied. Referring to fig. 1, the computing device 100 includes: a communication unit 101, a plurality of processors 102 (e.g., processor a and processor B shown in the figure), a memory 103, a display unit 105, an input unit 106. The various components of the computing device 100 are described in greater detail below in conjunction with FIG. 1.
The communication unit 101 is used for realizing communication interaction of the computing device 100 with other devices. Optionally, the communication unit 101 may include: the mobile communication device comprises a wireless communication module, a mobile communication module and a communication interface. The wireless communication module and the mobile communication module include antennas for implementing wireless communication functions of the computing device 100; the communication interface is capable of plugging into a cable for implementing wired communication functionality of the computing device.
The mobile communication module may provide a solution for applications on computing devices including 2G/3G/4G/5G wireless communication. The mobile communication module can receive electromagnetic waves by the antenna, filter and amplify the received electromagnetic waves, and transmit the electromagnetic waves to the modulation and demodulation processor for demodulation. The mobile communication module can also amplify the signal modulated by the modulation and demodulation processor and convert the signal into electromagnetic wave to radiate the electromagnetic wave through the antenna. In some embodiments, at least some of the functional modules of the mobile communication module may be disposed in the processor 102. In some embodiments, at least some of the functional modules of the mobile communication module may be provided in the same device as at least some of the modules of the processor 102.
The wireless communication module may provide solutions for wireless communication applied to electronic devices, including Wireless Local Area Networks (WLANs) (e.g., wireless fidelity (Wi-Fi) networks), Bluetooth (BT), Global Navigation Satellite System (GNSS), Frequency Modulation (FM), Near Field Communication (NFC), Infrared (IR), and the like. The wireless communication module may be one or more devices integrating at least one communication processing module. The wireless communication module receives electromagnetic waves via the antenna 2, performs frequency modulation and filtering processing on electromagnetic wave signals, and transmits the processed signals to the processor 102. The wireless communication module may also receive a signal to be transmitted from the processor 102, frequency-modulate and amplify the signal, and convert the signal into electromagnetic waves via the antenna 2 to radiate the electromagnetic waves.
And the communication interface is used for realizing physical connection with other equipment. Optionally, the communication interface is connected to the communication interface of the other device through a cable, so as to implement data transmission between the computing device 100 and the other device.
The processors 102 are a control center of the computing device 100, and may utilize various interfaces or lines to connect various components, run an operating system, execute software programs and/or modules stored in the memory 103, call stored data, and execute various functions or processes in the computing device 100, so as to implement various services based on the computing device 100.
In this embodiment, the number of the plurality of processors 102 is not limited to two, and may be two or more. Where either processor may call a function in the other processor. Optionally, there is one master processor in the plurality of processors 102, and the other processors are slave processors. The master processor may call a function belonging to the slave processor during the execution of the program. Any two of the processors 102 may interact to communicate with each other to transmit network messages to implement function calls across the processors.
Each of the plurality of processors 102 is further provided with a buffer 1021 for buffering instructions and data of the processor. In some embodiments, cache 1021 in the processor is a cache memory. The register 1021 may hold instructions or data that have just been used or recycled by the processor. If the processor needs to reuse the instruction or data, it can be called directly from the register 1021. Avoiding repeated accesses and reducing the latency of the processor, thereby increasing the efficiency of the system.
In the embodiment of the present application, any processor may save the function, the parameter in the function, and the related information of the parameter to its internal memory during the execution of the program.
The memory 103 may be used to store computing device executable program code, including instructions. The processor 102 executes various functional applications of the electronic device and data processing by executing instructions stored in the internal memory 103. The memory 103 may include a program storage area and a data storage area. The program storage area may store an operating system, and other programs such as program codes, instructions, and the like of applications. The storage data area may store data generated during use of the electronic device, and the like. In addition, the internal memory may include a high-speed random access memory, and may further include a nonvolatile memory, such as at least one of a magnetic disk storage device, a flash memory device, a universal flash memory (UFS), and the like.
The display unit 105 is used for a user interface. The display unit 105 may also be referred to as a display panel or a display screen. The display unit may be a Liquid Crystal Display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (active-matrix organic light-emitting diode, AMOLED), a flexible light-emitting diode (FLED), a miniature, a Micro-oeld, a quantum dot light-emitting diode (QLED), or the like.
The input unit 106 may be used to receive character information and instructions input by a user. Alternatively, the input unit 106 may include a touch screen 1061 and other input devices (e.g., function keys).
The touch screen 1061 is configured to collect information corresponding to a touch operation of a user, and the processor 102 executes a corresponding command after receiving the information. Optionally, the touch screen 1061 may be implemented by various types, such as a resistive type, a capacitive type, an infrared ray, and a surface acoustic wave. For example, a user may initiate the ambient activity sensing function via the touch screen 1061. The touch screen may be coupled with the display panel to be a touch display screen.
Those skilled in the art will appreciate that the configuration of the computing device shown in FIG. 1 does not constitute a limitation of the computing device, and that the computing device provided by embodiments of the present application may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.
The embodiment of the application provides a method for function calling, which is suitable for the computing device 100 shown in fig. 1. The first processor and the second processor involved in the following method may be any two processors of the plurality of processors 102 in the computing device 100, such as processor a and processor B. Referring to fig. 2, the flow of the method includes:
s201: and in the process of running the program, the first processor determines a second processor to which the function to be run belongs in the program.
Illustratively, the prototype of the remote call function in the first processor is as follows:
the dstsfold is a processor to which a function to be executed belongs, namely a second processor, u32Cmd is a cross-processor call function command word, OSP _ ADDR _ VAL represents different processor bit widths, u32 is defined when 32 bits are located, u64 is defined when 64 bits are located, Arg represents a user-specified parameter, and u32Arglen is the length of different types of parameters.
S202: the first processor determines that the function to be run contains a multi-level pointer parameter. The multi-level pointer parameter includes a plurality of pointer variables, and at least one of the pointer variables points to another pointer variable.
In one embodiment, the first processor may perform S202 by:
firstly, determining that the function to be run comprises specified parameters.
And then, determining whether the function to be run contains multi-level pointer parameters according to the length of the specified parameters in the function to be run.
Optionally, when the first processor determines that the length of the specified parameter in the function to be run is greater than or equal to a set length, it is determined that the function to be run includes the multi-level pointer parameter. Wherein, the set length can be 2048.
The description is continued by taking the above remote call function prototype as an example.
The first processor can determine whether the setting parameters in the function to be run contain multi-level pointer parameters by judging the size of the u32Arglen value:
in the first case: when the length u32Arglen of the parameter is 0, the first processor determines that the parameter type is integer data.
In the second case: when the length of the parameter is greater than 0 and less than 2047, the first processor determines that the parameter type is single-level pointer data.
In the third case: when the length of the parameter is equal to 2048, then the first processor determines that the parameter type is multi-level pointer data.
S203: the first processor acquires the structural information of the multi-level pointer parameters in the function to be run and stores the structural information into a cache with continuous addresses; wherein the structural information is used to characterize: the number of pointer variables, the variable information of each pointer variable and the pointing relationship among the pointer variables contained in the multi-level pointer parameter; the variable information of any one pointer variable contains the length and the first address of the pointer variable.
In an embodiment, the first processor may obtain, through a preset function, structure information of a multi-level pointer parameter in the function to be executed. The structural information may be represented by a global variable g _ struospioltlargpatch. The concrete structure is as follows:
specifically, the specific structure of the information OSP _ STRU _ RIOCTL _ ARG _ INFO of the pointer variable may include:
(1) 64bit data format
(2) 32bit data format
It can be seen from the above two formats that the variable information of any pointer variable contains the length and the first address of the pointer variable, and 32-bit and 64-bit data can be compatible.
Specifically, the pointing relationship of the pointer variable may be embodied by OSP _ STRU _ RIOCTL _ PTR _ INFO:
the OSP _ STRU _ RIOCTL _ PTR _ INFO structure records the pointing relationship among each pointer variable, and specifically comprises the identification and address offset of a source pointer variable and the identification and address offset of a destination pointer variable.
Through the above description, the structure information of the multi-level pointer parameter can be used to characterize: the number of pointer variables, the variable information of each pointer variable and the pointing relationship among the pointer variables contained in the multi-level pointer parameter; the variable information of any one pointer variable contains the length and the first address of the pointer variable.
Optionally, the structure information of the multi-level pointer parameter may be stored in the address-sequential buffer 1021.
S204: and the first processor acquires the number of pointer variables contained in the multi-level pointer parameter and the variable information of each pointer variable from the structure information. The information that the first processor can obtain is also stored in a cache contiguous with the structure information address.
Through S203 and S204, the first processor may spread the pointing relationship of the multi-level pointer parameter and tile the pointer parameter into a segment of cache with consecutive addresses.
S205: the first processor sends a first network message to the second processor through the first network message, wherein the first network message comprises: the structure information of the multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, the variable information of each pointer variable, and the information of the function to be run. And the second processor receives the first network message sent by the first processor.
In one embodiment, the first processor may send the first network message to the second processor through a communication interface. Optionally, the communication interface may be defined as:
OSP_STATUS Osp_Register_Rioct1_Hook(u32 u32Cmd,
void *pArg,
OSP_STRU_RIOCTL_ARG_PAT CH*pstruArgPatch)
s206: and the second processor determines the absolute address offset of each pointer variable in the multi-level pointer parameters according to the number of pointer variables contained in the multi-level pointer parameters contained in the first network message and the variable information of each pointer variable.
And after receiving the first network message, the second processor stores the structural information of the multi-level pointer parameter into a cache memory with continuous addresses. Then, the absolute address offset of each pointer variable in the multi-level pointer parameter is determined according to the number of pointer variables contained in the multi-level pointer parameter contained in the first network message and the variable information of each pointer variable. Optionally, the second processor may be determined by:
the second processor can sort all the pointer variables according to the first addresses of the pointer variables in each pointer variable information and the sequence of the addresses from small to large; determining the absolute address offset of the first pointer variable to be 0; then the second processor determines the absolute address offset of the second pointer variable to be the length of the first pointer variable; and the absolute offset address of the third pointer variable is the sum of the length of the first pointer variable and the length of the second pointer variable, and so on, thereby determining the absolute offset address of each pointer variable in the multi-stage pointer parameter.
Through S206, the second processor may determine an absolute offset address of each pointer variable in the multi-stage pointer parameter, so as to facilitate subsequent calculation of an address of a source pointer variable and an address of a destination pointer variable in a pointing relationship between each pointer variable.
S207: and the second processor calculates the address of the source pointer variable and the address of the destination pointer variable in the direction relation between each pointer variable according to the direction relation between the pointer variables in the structure information of the multi-level pointer parameter and the absolute address offset of each pointer variable.
The specific steps of the second processor executing S207 are as follows:
a 1: and the second processor takes the first address of the structural information of the multi-level pointer parameter in the cache as the first address of the multi-level pointer parameter.
a 2: and the second processor calculates the address of the source pointer variable and the address of the destination pointer variable in the direction relationship between the pointer variables according to the initial address of the multi-stage pointer parameter and the absolute address offset of each pointer variable.
Optionally, the second processor may execute step a2 by the following algorithm:
b 1: the second processor determines a source pointer variable and a destination pointer variable in the direction relationship between the first pointer variables according to the structural information of the multi-level pointer parameters;
b 2: the second processor determining an absolute address offset of the source pointer variable and an address offset of the destination pointer variable;
b 3: the second processor takes the sum of the head address determined in the a1 and the absolute address offset of the source pointer variable as the address of the source pointer variable; the second processor takes the sum of the head address determined in the a1 and the absolute address offset of the destination pointer variable as the address of the destination pointer variable;
b 4: and the second processor repeats the steps to determine the address of the source pointer variable and the address of the destination pointer variable in the pointing relationship between the next pointer variables until the address of the source pointer variable and the address of the destination pointer variable in the pointing relationship between each pointer variable are determined.
And S207, the second processor is used for realizing the recombination of the multi-level pointer parameters according to the address of the source pointer variable and the address of the destination pointer variable in the determined pointing relation between each pointer variable in the multi-level pointer parameters.
S208: and the second processor assigns the address of the target pointer variable in the direction relation between each pointer variable to the source pointer and reconstructs the multi-level pointer parameters according to the structural information of the multi-level pointer parameters.
Through S208, the second processor recombines the pointer parameters tiled in a segment of continuous-address cache in the second processor according to the structure information of the multi-level pointer parameters, thereby implementing the reconstruction of the multi-level pointer parameters.
S209: and the second processor operates the function to be operated according to the information of the function to be operated and the reconstructed multi-level pointer parameters to obtain an operation result.
S210: and the second processor sends a second network message to the first processor, wherein the second network message comprises the operation result.
S211: and the first processor receives the second network message from the second processor to obtain the operation result of the function to be operated, and then continuously operates the program according to the operation result.
In the method, when a first processor in a computing device determines that a function to be executed in a program belongs to a second processor in the computing device and the function to be executed comprises a multi-level pointer parameter in the program in the process of running the program, the first processor can send structure information of the multi-level pointer parameter, the number and information of pointer variables contained in the multi-level pointer parameter and information of the function to be executed to the second processor through a first network message; in this way, after receiving the first network message, the second processor may reconstruct the multi-level pointer parameter according to various information therein and operate the function to be operated, thereby obtaining an operation result; and finally, the second processor returns the operation result to the first processor through a second network message. This method may implement a function call across processors that contains multiple levels of pointer parameters.
Based on the above embodiments, the present application provides a first processor 300, where the first processor 300 is applied to a computing device having multiple processors, and referring to fig. 3, the first processor 300 includes: a storage unit 301, a processing unit 302, a communication unit 303, wherein:
the storage unit 301 is used for caching data.
A processing unit 302, configured to determine a second processor to which the function to be executed belongs; determining that the function to be run comprises a plurality of levels of pointer parameters, wherein the plurality of levels of pointer parameters comprise a plurality of pointer variables, and at least one pointer variable in the plurality of pointer variables points to other pointer variables; acquiring the structural information of the multi-level pointer parameter, and storing the structural information into a cache with continuous addresses in the storage unit; wherein the structural information is used to characterize: the number of pointer variables, the variable information of each pointer variable and the pointing relationship among the pointer variables contained in the multi-level pointer parameter; the variable information of any pointer variable includes the length and the first address of the pointer variable; and acquiring the number of pointer variables contained in the multi-level pointer parameter and the variable information of each pointer variable from the structure information.
A communication unit 303, configured to send a first network message to the second processor, where the first network message includes: the structure information of the multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, the variable information of each pointer variable, and the information of the function to be run; and receiving a second network message sent by the second processor, wherein the second network message comprises an operation result of the second processor on the function to be operated.
Optionally, when determining that the function to be run includes a multi-level pointer parameter, the processing unit 302 is specifically configured to: when the first processor determines that the function to be run comprises the specified parameter, and when the first processor determines that the length of the specified parameter is greater than or equal to the set length, the first processor determines that the function to be run comprises the multi-level pointer parameter.
Specifically, the pointing relationship between the pointer variables includes: the number of pointing relationships between pointer variables; the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
Based on the above embodiments, the present application further provides a second processor 400, where the second processor 400 is applied to a computing device having multiple processors, and referring to fig. 4, the first processor 400 includes: a storage unit 401, a processing unit 402, a communication unit 403, wherein:
the storage unit 401 is used for caching data.
A communication unit 403, configured to receive a first network message sent by a first processor, where the first network message includes: the method comprises the following steps of obtaining structure information of multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, variable information of each pointer variable and information of a function to be run; wherein the structural information is used to characterize: the number of pointer variables, the variable information of each pointer variable and the pointing relationship among the pointer variables contained in the multi-level pointer parameter; the variable information of any one pointer variable contains the length and the first address of the pointer variable.
A processing unit 402, configured to store the structure information of the multilevel pointer parameter in a cache with consecutive addresses in the storage unit, and determine an absolute address offset of each pointer variable in the multilevel pointer parameter according to the number of pointer variables included in the multilevel pointer parameter included in the first network message and the variable information of each pointer variable; calculating the address of a source pointer variable and the address of a destination pointer variable in the pointing relationship between each pointer variable according to the pointing relationship between the pointer variables in the structure information of the multi-stage pointer parameters and the absolute address offset of each pointer variable; assigning the address of a target pointer variable in the direction relation between each pointer variable to a source pointer, and reconstructing the multi-level pointer parameters according to the structural information of the multi-level pointer parameters; and operating the function to be operated according to the information of the function to be operated and the reconstructed multi-level pointer parameters to obtain an operation result.
The communication unit 403 is further configured to send a second network message to the first processor, where the second network message includes the operation result.
Specifically, the pointing relationship between the pointer variables includes: the number of pointing relationships between pointer variables; the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
Optionally, when calculating the address of the source pointer variable and the address of the destination pointer variable in the pointing relationship between each pointer variable according to the pointing relationship between the pointer variables in the structure information of the multi-stage pointer parameter and the absolute address offset of each pointer variable, the processing unit 402 is specifically configured to:
taking the first address of the structure information of the multi-level pointer parameter in the cache as the first address of the multi-level pointer parameter; and calculating the address of the source pointer variable and the address of the destination pointer variable in the direction relation between the pointer variables according to the initial address of the multistage pointer parameter and the absolute address offset of each pointer variable.
Based on the above embodiments, the present application provides a computing device for executing the units of the steps in the above embodiments.
Based on the above embodiments, the present application provides a computer-readable storage medium, in which computer instructions are stored, and when the computer instructions are executed by a computer, the computer causes the computer to execute a function calling method provided by the above embodiments.
Based on the above embodiments, the present application further provides a chip, where the chip is configured to read and execute the computer program stored in the memory, so as to implement the function calling method provided in the above embodiments. As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (16)
1. A function call method for use in a computing device having a plurality of processors, the method comprising:
the first processor determines a second processor to which the function to be run belongs;
the first processor determines that the function to be run comprises a plurality of levels of pointer parameters, wherein the plurality of levels of pointer parameters comprise a plurality of pointer variables, and at least one pointer variable in the plurality of pointer variables points to other pointer variables;
the first processor acquires the structural information of the multi-level pointer parameter and stores the structural information into a cache with continuous addresses; wherein the structural information is used to characterize: the number of pointer variables, the variable information of each pointer variable and the pointing relationship among the pointer variables contained in the multi-level pointer parameter; the variable information of any pointer variable includes the length and the first address of the pointer variable;
the first processor acquires the number of pointer variables contained in the multi-level pointer parameter and the variable information of each pointer variable from the structure information;
the first processor sends a first network message to the second processor, wherein the first network message comprises: the structure information of the multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, the variable information of each pointer variable, and the information of the function to be run;
and the first processor receives a second network message sent by the second processor, wherein the second network message comprises an operation result of the second processor on the function to be operated.
2. The method of claim 1, wherein the first processor determining that the function to be run includes a multi-level pointer parameter comprises:
when the first processor determines that the function to be run comprises the specified parameter, and when the first processor determines that the length of the specified parameter is greater than or equal to the set length, the first processor determines that the function to be run comprises the multi-level pointer parameter.
3. The method of claim 1, wherein the pointing relationships between pointer variables comprise:
the number of pointing relationships between pointer variables;
the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
4. A function call method for use in a computing device having a plurality of processors, the method comprising:
the second processor receives a first network message sent by the first processor, wherein the first network message comprises: the method comprises the following steps of obtaining structure information of multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, variable information of each pointer variable and information of a function to be run; wherein the structural information is used to characterize: the number of pointer variables, the variable information of each pointer variable and the pointing relationship among the pointer variables contained in the multi-level pointer parameter; the variable information of any pointer variable includes the length and the first address of the pointer variable; the second processor stores the structure information of the multi-level pointer parameter into a cache with continuous addresses;
the second processor determines the absolute address offset of each pointer variable in the multi-level pointer parameters according to the number of pointer variables contained in the multi-level pointer parameters contained in the first network message and the variable information of each pointer variable;
the second processor calculates the address of a source pointer variable and the address of a destination pointer variable in the direction relation between each pointer variable according to the direction relation between the pointer variables in the structure information of the multi-level pointer parameter and the absolute address offset of each pointer variable;
the second processor assigns the address of the target pointer variable in the direction relation between each pointer variable to the source pointer, and reconstructs the multi-level pointer parameters according to the structural information of the multi-level pointer parameters;
the second processor operates the function to be operated according to the information of the function to be operated and the reconstructed multi-level pointer parameters to obtain an operation result;
and the second processor sends a second network message to the first processor, wherein the second network message comprises the operation result.
5. The method of claim 4, wherein the pointing relationships between the pointer variables comprise:
the number of pointing relationships between pointer variables;
the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
6. The method of claim 4, wherein the second processor calculates an address of a source pointer variable and an address of a destination pointer variable in a pointing relationship between each pointer variable according to a pointing relationship between pointer variables in the structure information of the multi-level pointer parameter, an absolute address offset of each pointer variable, comprising:
the second processor takes the first address of the structural information of the multi-level pointer parameter in the cache as the first address of the multi-level pointer parameter;
and the second processor calculates the address of the source pointer variable and the address of the destination pointer variable in the direction relationship between the pointer variables according to the initial address of the multi-stage pointer parameter and the absolute address offset of each pointer variable.
7. A first processor for use in a computing device having a plurality of processors, comprising:
the storage unit is used for caching data;
the processing unit is used for determining a second processor to which the function to be run belongs; determining that the function to be run comprises a plurality of levels of pointer parameters, wherein the plurality of levels of pointer parameters comprise a plurality of pointer variables, and at least one pointer variable in the plurality of pointer variables points to other pointer variables; acquiring the structural information of the multi-level pointer parameter, and storing the structural information into a cache with continuous addresses in the storage unit; wherein the structural information is used to characterize: the number of pointer variables, the variable information of each pointer variable and the pointing relationship among the pointer variables contained in the multi-level pointer parameter; the variable information of any pointer variable includes the length and the first address of the pointer variable; acquiring the number of pointer variables contained in the multi-level pointer parameter and variable information of each pointer variable from the structure information;
a communication unit, configured to send a first network message to the second processor, where the first network message includes: the structure information of the multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, the variable information of each pointer variable, and the information of the function to be run; and receiving a second network message sent by the second processor, wherein the second network message comprises an operation result of the second processor on the function to be operated.
8. The first processor of claim 7, wherein the processing unit, when determining that the function to be run includes a multi-level pointer parameter, is specifically configured to:
when the first processor determines that the function to be run comprises the specified parameter, and when the first processor determines that the length of the specified parameter is greater than or equal to the set length, the first processor determines that the function to be run comprises the multi-level pointer parameter.
9. The first processor of claim 7, wherein the pointing relationships between pointer variables comprise:
the number of pointing relationships between pointer variables;
the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
10. A second processor for use in a computing device having a plurality of processors, comprising:
the storage unit is used for caching data;
a communication unit, configured to receive a first network message sent by a first processor, where the first network message includes: the method comprises the following steps of obtaining structure information of multi-level pointer parameters, the number of pointer variables contained in the multi-level pointer parameters, variable information of each pointer variable and information of a function to be run; wherein the structural information is used to characterize: the number of pointer variables, the variable information of each pointer variable and the pointing relationship among the pointer variables contained in the multi-level pointer parameter; the variable information of any pointer variable includes the length and the first address of the pointer variable;
the processing unit is used for storing the structural information of the multi-level pointer parameters into a cache with continuous addresses in the storage unit; determining the absolute address offset of each pointer variable in the multi-level pointer parameters according to the number of pointer variables contained in the multi-level pointer parameters and the variable information of each pointer variable contained in the first network message; calculating the address of a source pointer variable and the address of a destination pointer variable in the pointing relationship between each pointer variable according to the pointing relationship between the pointer variables in the structure information of the multi-stage pointer parameters and the absolute address offset of each pointer variable; assigning the address of a target pointer variable in the direction relation between each pointer variable to a source pointer, and reconstructing the multi-level pointer parameters according to the structural information of the multi-level pointer parameters; running the function to be run according to the information of the function to be run and the reconstructed multi-level pointer parameters to obtain a running result;
the communication unit is further configured to send a second network message to the first processor, where the second network message includes the operation result.
11. The second processor of claim 10, wherein the pointing relationships between the pointer variables comprise:
the number of pointing relationships between pointer variables;
the pointing relationship between each pointer variable contains the identity and address offset of the source pointer variable and the identity and address offset of the destination pointer variable.
12. The second processor according to claim 10, wherein the processing unit, when calculating an address of a source pointer variable and an address of a destination pointer variable in a pointing relationship between each pointer variable based on a pointing relationship between pointer variables in the structure information of the multi-stage pointer parameter, an absolute address offset of each pointer variable, is specifically configured to:
taking the first address of the structure information of the multi-level pointer parameter in the cache as the first address of the multi-level pointer parameter; and calculating the address of the source pointer variable and the address of the destination pointer variable in the direction relation between the pointer variables according to the initial address of the multistage pointer parameter and the absolute address offset of each pointer variable.
13. A computing device, comprising:
a first processor for performing the method of any one of claims 1-3;
a second processor for performing the method of any of claims 4-6.
14. A computer-readable storage medium, in which a computer program is stored which, when run on an electronic device, causes the electronic device to perform the method according to any one of claims 1-6.
15. A computer program, comprising instructions which, when run on a computer, cause the computer to perform the method of any of claims 1-6.
16. A chip for reading a computer program stored in a memory for performing the method according to any one of claims 1 to 6.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103135964A (en) * | 2011-12-05 | 2013-06-05 | 联想(北京)有限公司 | Method and electronic equipment of calling function across instruction set |
| CN106649084A (en) * | 2016-09-14 | 2017-05-10 | 腾讯科技（深圳）有限公司 | Function call information obtaining method and apparatus, and test device |
| JP2019144857A (en) * | 2018-02-21 | 2019-08-29 | 富士通株式会社 | Information processing device, compiling method, and compiling program |
-
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103135964A (en) * | 2011-12-05 | 2013-06-05 | 联想(北京)有限公司 | Method and electronic equipment of calling function across instruction set |
| CN106649084A (en) * | 2016-09-14 | 2017-05-10 | 腾讯科技（深圳）有限公司 | Function call information obtaining method and apparatus, and test device |
| JP2019144857A (en) * | 2018-02-21 | 2019-08-29 | 富士通株式会社 | Information processing device, compiling method, and compiling program |
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