CN112865849A

CN112865849A - Network for simulating phased array beam forming

Info

Publication number: CN112865849A
Application number: CN202110396312.9A
Authority: CN
Inventors: 兰冰; 邵宇杰; 刘东栋; 周利红; 余晨
Original assignee: Zhejiang Jisu Hexin Technology Co ltd
Current assignee: Zhejiang Jisu Hexin Technology Co ltd
Priority date: 2021-04-13
Filing date: 2021-04-13
Publication date: 2021-05-28
Anticipated expiration: 2041-04-13
Also published as: CN112865849B

Abstract

The invention relates to a network for simulating phased array beam forming. The array element beam synthesis network comprises an array element beam synthesis network and a PCB (printed circuit board) level synthesis network, wherein the array element beam synthesis network is arranged in an analog phase-shifting chip on a phase control array surface, a frequency mixer is arranged in each analog phase-shifting chip in the array element beam synthesis network, and the frequency of a beam synthesized in each analog phase-shifting chip is converted into an intermediate frequency signal through the frequency mixer; and the intermediate frequency signal generates a synthesized beam signal through the PCB level synthesis network. The invention can effectively reduce the realization difficulty and cost of the analog phased array surface, and is beneficial to the market popularization of the phased array satellite communication terminal and the 5G millimeter wave.

Description

Network for simulating phased array beam forming

Technical Field

The invention relates to the field of communication, in particular to a network for simulating phased array beam forming.

Background

The traditional analog phased array surface beam synthesis network comprises two parts, wherein one part is an array element beam synthesis network inside a chip, and the other part is a board-level synthesis network. Taking a single-beam receiving analog phased array surface of a Ka frequency band as an example, the array surface comprises N analog phase-shifting chips (BFC), each Chip comprises M receiving channels, the phase of each receiving channel is controlled by a phase shifter, the M receiving channels synthesize a beam inside the Chip and output the beam to a PCB, then the beam is synthesized by a multi-stage synthesis network of the PCB, finally the synthesized beam is converted to an intermediate frequency by down conversion and then digitized by an ADC, and a traditional analog phased array synthesis network is shown in fig. 1.

The wave beam synthesis method requires that signals transmitted by the array surface are all Ka frequency bands, such as signals of 30GHz, the loss of high-frequency signals in PCB wiring is large, and in order to reduce the signal transmission loss, the PCB is required to use high-speed plates, such as Rogers series models, so that the processing cost of the array surface PCB is very high, and the application and popularization of the phased array are limited.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a network for simulating phased array beam forming.

The invention is used for transmitting high-frequency signals, and comprises an array element wave beam synthesis network and a PCB (printed circuit board) level synthesis network, wherein the array element wave beam synthesis network is arranged inside an analog phase-shifting chip on a phase control array surface; and the intermediate frequency signal generates a synthesized beam signal through the PCB level synthesis network.

Furthermore, the local oscillator clock of the frequency mixer is input by an external clock source, and the external clock source forms the local oscillator clock after passing through a frequency multiplier inside the analog phase-shifting chip.

Furthermore, a high linear power amplifier is arranged between the clock source input and the frequency multiplier inside the analog phase shift chip and is used for ensuring the power and the phase noise of the local oscillator.

The invention has the beneficial effects that:

1. a lumped mixer in the prior art is changed into a distributed mixer, and mixing is realized in each phase-shifting chip.

2. The synthesis of the network signals synthesized by the PCB is completed by reducing the frequency of the previous radio frequency or millimeter wave signals to the intermediate frequency, thereby reducing the requirements of the array surface PCB and reducing the difficulty and the cost of the implementation of the array surface.

3. In order to realize phase synchronization among multiple chips, the local oscillator in the chips is realized by a low-frequency clock source in a frequency multiplier mode, so that phase ambiguity is avoided, and the basic function of the phased array is ensured.

4. In order to reduce the difficulty of realizing a clock source distribution system, a clock source high-linearity power amplifier circuit is provided in the chip, so that the technical realization difficulty and the power consumption of a front surface clock distribution network are reduced.

Drawings

FIG. 1 is a conventional analog phased array synthetic network;

fig. 2 is a diagram of an analog phased array synthesis network of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.

As shown in fig. 2, in order to reduce the cost of the analog phase array, the present invention distributes a mixer to each chip, and the implementation manner of the mixer is various and belongs to the prior art. After the synthesis of the beam is completed in the chip, the frequency is down-converted to an intermediate frequency signal, such as 2GHz, by the mixer, and then the intermediate frequency signal is used to complete the board-level synthesis network on the PCB to generate a synthesized beam signal. Because the signal frequency of the PCB synthetic network is lower, the PCB synthetic network can be realized by adopting a cheap PCB plate, such as an FR4 plate, so that the cost of transmitting high-frequency signals by the front PCB is effectively reduced, and the high-frequency signals comprise X/Ku/Ka/Q/V/W/F frequency band signals.

In the invention, because each chip is internally provided with a mixer, the local oscillator clock of the mixer needs to be input externally, the local oscillator frequency of one embodiment is a 32GHz clock signal, and in order to match the PCB with reduced cost, the frequency of the external local oscillator clock source input to the chip needs to be as low as possible, for example, the frequency of the external local oscillator clock source is 4GHz clock signal. Local oscillation signals of multiple channels or N chips have decisive influence on phase synchronization among the channels, and in order to ensure the phase synchronization of the frequency mixers or the local oscillations of the N chips, 32GHz local oscillation signals cannot be generated in a phase-locked loop mode. Therefore, the invention is realized by adopting a scheme of a frequency multiplier in a chip, for example, an 8-frequency multiplier is adopted, and a local oscillator signal of 32GHz is generated by multiplying a 4GHz clock by 8, so that the phase synchronization of the frequency mixers between the chips can be ensured. And because a group of local oscillation source distribution networks are added on the basis of the original beam power synthesis network, the input power of one local oscillation source reaching each chip is smaller, and therefore a high-linearity power amplifier is integrated in the chip to ensure the power and the phase noise of the local oscillation.

The invention can effectively reduce the realization difficulty and cost of the analog phased array surface, and is beneficial to the market popularization of the phased array satellite communication terminal and the 5G millimeter wave.

Claims

1. The utility model provides a network of simulation phased array beam forming for transmit high frequency signal, including on the phased array face simulation phase shift chip inside array element beam forming network and PCB board level synthetic network, its characterized in that: a frequency mixer is arranged in each analog phase-shifting chip in the array element wave beam synthesis network, and the wave beams synthesized in each analog phase-shifting chip are converted into intermediate frequency signals through the frequency mixer; and the intermediate frequency signal generates a synthesized beam signal through the PCB level synthesis network.

2. A network for analog phased array beamforming according to claim 1 wherein: the local oscillator clock of the frequency mixer is input by an external clock source, and the external clock source forms the local oscillator clock after passing through a frequency multiplier inside the analog phase-shifting chip.

3. A network for analog phased array beamforming according to claim 2 wherein: and a high-linearity power amplifier is also arranged between the clock source input and the frequency multiplier in the analog phase-shift chip and is used for ensuring the power and the phase noise of the local oscillator.