CN112865727A - Dynamic bias power amplifier - Google Patents
Dynamic bias power amplifier Download PDFInfo
- Publication number
- CN112865727A CN112865727A CN202110090071.5A CN202110090071A CN112865727A CN 112865727 A CN112865727 A CN 112865727A CN 202110090071 A CN202110090071 A CN 202110090071A CN 112865727 A CN112865727 A CN 112865727A
- Authority
- CN
- China
- Prior art keywords
- nmos
- bias
- tube
- gate
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003321 amplification Effects 0.000 claims abstract description 49
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 49
- 230000000903 blocking effect Effects 0.000 claims abstract description 28
- 239000003990 capacitor Substances 0.000 claims description 46
- 238000002955 isolation Methods 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 32
- 238000005070 sampling Methods 0.000 claims description 10
- 238000001514 detection method Methods 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
- 238000004088 simulation Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a dynamic bias power amplifier, comprising: the input and matching module is used for performing impedance matching and blocking on an input radio frequency signal; the laminated power amplification module is used for carrying out power amplification on the matched radio-frequency signal under the control of the dynamic bias voltage; the output and matching module is used for performing impedance matching and blocking on the output radio frequency signal of the stacked power amplification module; and the dynamic bias module is used for generating dynamic bias voltage to the power amplification tube of the stacked power amplification module according to the size of the input radio frequency signal.
Description
Technical Field
The present invention relates to a power amplifier, and more particularly, to a dynamically biased power amplifier.
Background
A Power Amplifier (PA) is used as a key device of a radio frequency front end transmission link, and the efficiency of the PA affects the power consumption of a system. In order to improve the communication rate, the 5G communication adopts a 64-QAM modulation technique, and the power amplifier PA needs to operate under a higher output power peak-to-average ratio PAPR, so that it is very important to improve the power backoff area PAE of the power amplifier PA to reduce the system power consumption.
Fig. 1 is a circuit configuration diagram of a power amplifier with a fixed bias in the prior art. As shown in fig. 1, the conventional fixed bias power amplifier includes an input and matching module 10, a stacked power amplifying module 20, an output and matching module 30, and a fixed bias module 40. The input and matching module 10 consists of an input matching inductor Lin and an input blocking matching capacitor Cin and is used for completing input matching and blocking; the stacked power amplification module 20 is composed of a common source NMOS power amplification tube M1And its gate isolation resistor R1Multi-stage common-grid NMOS power amplifier tube M2、M3、M4And its isolation resistance R2、R3、R4And gate grounded capacitance C2、C3、C4The component is used for completing the power amplification of the radio frequency signal; the output and matching module 30 is composed of a load inductor Ld and an output matching blocking capacitor Co, and is used for completing output matching and blocking; the fixed bias module 40 is formed by a plurality of NMOS bias tubes M connected by diodes5、M6、M7、M8Is used for providing a common source NMOS power amplifier tube M under the control of a reference current Iref1Common gate NMOS power amplifier tube M2、M3、M4A fixed bias voltage is set.
The radio frequency signal RFin is connected to the common end of the input matching inductor Lin and the input blocking matching capacitor Cin, the other end of the input matching inductor Lin is connected with the radio frequency ground RF GND, and the other end of the input blocking matching capacitor Cin is connected to the common source NMOS power amplifier tube M1Gate and isolation resistor R1One end of (a); common source NMOS power amplifier tube M1The source electrode and the substrate of the power amplifier are connected with a radio frequency ground RF GND and a common source NMOS power amplifier tube M1Is connected to the common-gate NMOS power amplifier tube M2Source and substrate of (1), common gate NMOS power amplifier tube M2Is connected to an isolation resistor R2One terminal of (1) and a gate grounding capacitor C2One end of (1), a common gate NMOS power amplifier tube M2Is connected to the common-gate NMOS power amplifier tube M3Source and substrate of (1), common gate NMOS power amplifier tube M3Is connected to an isolation resistor R3One terminal of (1) and a gate grounding capacitor C3One end of (1), a common gate NMOS power amplifier tube M3Is connected to the common-gate NMOS power amplifier tube M4Source and substrate of (1), common gate NMOS power amplifier tube M4Is connected to an isolation resistor R4One terminal of (1) and a gate grounding capacitor C4One terminal of (1), gate grounded capacitance C2、C3、C4The other end of the first and second electrodes is grounded; common-gate NMOS power amplifier tube M4Is connected to the common terminal of a load inductor Ld and an output matching blocking capacitor Co, the other terminal of the load inductor Ld is connected to a power supply Vdd, and the output matching blocking capacitor CoThe other end of the capacitor Co is the output end RFout of the power amplifier;
NMOS bias tube M5Is connected to the NMOS bias tube M after being shorted with the grid electrode6Source and substrate and isolation resistor R1The other end of the NMOS bias tube M5Source and substrate of (1) are connected with an analog ground, NMOS biasing tube M6Is connected to the NMOS bias tube M after being shorted with the grid electrode7Source and substrate and isolation resistor R2The other end of the NMOS bias tube M7Is connected to the NMOS bias tube M after being shorted with the grid electrode8Source and substrate isolation resistor R3The other end of the NMOS bias tube M8Is shorted to the other end of the reference current Iref and isolation resistor R4.
Although the fixed bias Power amplifier adopts a 4-FET laminated structure to improve the output Power, the fixed bias is required to be adopted according to the maximum Power design, the direct current (dc) current meets the requirement of the maximum Power output and needs larger current, and in a Power output backspacing area, the direct current (dc) current is larger than the current required by the Power output, so that the efficiency of the backspacing area PAE (Power-added efficiency) is reduced.
Disclosure of Invention
In order to overcome the above-mentioned deficiencies in the prior art, an object of the present invention is to provide a dynamic bias power amplifier, which effectively adjusts the gate bias voltage of a power amplifier tube according to the magnitude of the input power, controls the bias dc current to realize the dynamic adjustment of the power consumption adaptive input power, and effectively improves the PAE efficiency in the power backoff region.
To achieve the above and other objects, the present invention provides a dynamically biased power amplifier, comprising:
the input and matching module is used for performing impedance matching and blocking on an input radio frequency signal;
the laminated power amplification module is used for carrying out power amplification on the matched radio-frequency signal under the control of the dynamic bias voltage;
the output and matching module is used for performing impedance matching and blocking on the output radio frequency signal of the stacked power amplification module;
and the dynamic bias module is used for generating dynamic bias voltage to the power amplification tube of the stacked power amplification module according to the size of the input radio frequency signal.
Preferably, the dynamic bias module further comprises:
the input detection amplifier is used for acquiring input power, performing appropriate homodromous gain amplification and converting the input power into a radio frequency signal current to be injected into the bias adjusting module;
and the bias adjusting module is used for dynamically adjusting the bias voltages of the common source NMOS power amplifying tube and the common gate NMOS power amplifying tube of the stacked power amplifying module under the influence of the sampling radio frequency signal output by the input detection amplifier.
Preferably, the bias adjustment module includes:
the fixed bias module is used for sequentially adjusting the bias voltage of the gate leakage voltage to each common-gate NMOS power amplification tube of the stacked power amplification module under the constraint of the reference current to realize gate bias adjustment;
the variable bias module is used for adjusting the grid and drain voltage of an NMOS bias tube of the variable bias module according to the injection current so as to realize grid bias adjustment of a common source NMOS power amplification tube of the stacked power amplification module;
and the clamper is used for protecting each power amplification tube of the stacked power amplification module from entering a linear region when the grid bias is adjusted too much when the input power is maximum.
Preferably, the fixed bias module comprises a diode-connected sixth NMOS bias transistor (M)6) And a seventh NMOS bias transistor (M)7) And the eighth NMOS bias transistor (M)8) The eighth NMOS bias transistor (M)8) The grid-drain short circuit is connected to the reference current (Iref) and the stacked power amplification module, the seventh NMOS bias tube (M)7) The eighth NMOS bias tube (M) is connected after the grid leakage short circuit8) A source connected to the stacked power amplification module, the sixth NMOS bias transistor (M)6) The seventh NMOS bias tube (M) is connected after the grid leakage short circuit7) A source connected to the stacked power amplification module, the sixth NMOS bias transistor (M)6) And the source electrode is connected with the variable bias module.
Preferably, the variable bias module comprises an NMOS bias transistor (M)5) Bias resistor (R)5) And a rectifying capacitor (C)5) Said bias resistor (R)5) One end of the sixth NMOS bias tube (M) is connected with6) Source electrode, said bias resistor (R)5) The other end is connected to the NMOS bias tube (M)5) The rectifying capacitor (C)5) The clamp and the stacked power amplification module, the NMOS bias transistor (M)5) Source and substrate and said rectifying capacitor (C)5) The other end is connected with a radio frequency ground.
Preferably, the clamp includes a first diode (D)1) A second diode (D)2) The first diode (D)1) Is connected to the bias resistor (R)5) The rectifying capacitor (C)5) And the stacked power amplification module having a cathode connected to the second diode (D)2) The second diode (D)2) The cathode is connected to radio frequency ground.
Preferably, the clamp comprises a current limiting resistor (Rd) and a diode connected first NMOS transistor (MD)1) And a second NMOS transistor (MD)2) One end of the current limiting resistor (Rd) is connected with the NMOS bias tube (M)5) The other end of the grid is connected with a first NMOS tube (MD)1) Drain and gate of (1), first NMOS transistor (MD)1) Is connected with the substrate of the second NMOS tube (MD)2) The second NMOS transistor (MD)2) The source and the substrate of (1) are connected to radio frequency ground.
Preferably, the input sense amplifier comprises a sampling blocking capacitor (C)9) And a single-ended amplifier (Sa) to which the radio frequency signal RFin is connected9) One end, the sampling blocking capacitor (C)9) The other end is connected to the input end of the single-ended amplifier (Sa), and the output end of the single-ended amplifier (Sa) is connected to the NMOS bias tube (M)5) Drain electrode, bias resistor (R)5) And a sixth NMOS bias transistor (M)6) And a substrate.
PreferablyThe single-ended amplifier (Sa) comprises a ninth NMOS transistor (M)9) And the tenth NMOS transistor (M)10) And a ninth self-bias resistor (R)9) And a tenth self-bias resistor (R)10) The ninth self-bias resistor (R)9) And the ninth NMOS transistor (M)9) Is connected to form an input terminal of the single-ended amplifier, and the ninth self-biasing resistor (R)9) The other end of the first NMOS tube is connected with a ninth NMOS tube (M)9) Drain electrode of (1), tenth NMOS tube (M)10) And a tenth self-biasing resistor (R)10) One terminal of the tenth self-biasing resistor (R)10) And the other end of the first NMOS transistor (M) and a tenth NMOS transistor (M)10) Is connected to form the output end of the single-ended amplifier, a ninth NMOS transistor (M)9) And the tenth NMOS transistor (M)10) The gate and substrate of (a) are connected to analog ground.
Preferably, the stacked power amplification module comprises a common source NMOS power amplifier tube (M)1) And its gate isolation resistance (R)1) And a second common gate NMOS power amplifier tube (M)2) And a third common gate NMOS power amplifier tube (M)3) And the fourth common-gate NMOS power amplifier tube (M)4) And a second isolation resistance (R) thereof2) A third isolation resistor (R)3) And a fourth isolation resistor (R)4) And a second gate grounded capacitor (C)2) A third grid grounding capacitor (C)3) And a fourth gate grounded capacitor (C)4) The common source NMOS power amplifier tube (M)1) The grid is connected with the grid isolation resistor (R)1) And connected to the input and matching module, the source connected to RF ground, the drain connected to a second common-gate NMOS power amplifier transistor (M)2) The second common gate NMOS power amplifier tube (M)2) Is connected to a second isolation resistor (R)2) And a second gate grounded capacitance (C)2) The second common gate NMOS power amplifier tube (M)2) Is connected to a third common gate NMOS power amplifier tube (M)3) Source and substrate, third common gate NMOS power amplifier tube (M)3) Is connected to the isolation resistor (R)3) And a third gate grounded capacitance (C)3) One terminal of (1), a third common gate NMOS power amplifier tube (M)3) Drain electrode ofConnected to a fourth common-gate NMOS power amplifier transistor (M)4) Source and substrate, fourth common gate NMOS power amplifier tube (M)4) Is connected to a fourth isolation resistor (R)4) And a fourth gate grounded capacitance (C)4) Second gate grounded capacitance (C)2) A third grid grounding capacitor (C)3) And a fourth gate grounded capacitor (C)4) The other end of the first and second electrodes is grounded; fourth common gate NMOS power amplifier tube (M)4) The drain of which is connected to the output and matching module.
Compared with the prior art, the invention discloses a dynamic bias power amplifier, which can effectively adjust the grid bias voltage of a power amplifying tube according to the input power and control the bias dc current to realize the dynamic adjustment of power consumption self-adaptive input power and effectively improve the PAE efficiency of a power backoff area.
Drawings
Fig. 1 is a circuit configuration diagram of a power amplifier with a fixed bias in the prior art;
FIG. 2 is a circuit diagram of an embodiment of a dynamically biased power amplifier of the present invention;
FIG. 3 is a circuit diagram of another embodiment of a dynamically biased power amplifier according to the present invention;
FIG. 4 is a graph comparing simulation results of the present invention and the prior art.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
Fig. 2 is a circuit diagram of an embodiment of a dynamically biased power amplifier according to the present invention. As shown in fig. 2, the dynamic bias power amplifier of the present invention includes an input and matching module 10, a stacked power amplifying module 20, an output and matching module 30, and a dynamic bias module 40. Wherein the content of the first and second substances,the input and matching module 10 consists of an input matching inductor Lin and an input blocking matching capacitor Cin and is used for completing input matching and blocking; the stacked power amplification module 20 is composed of a common source NMOS power amplification tube M1And its gate isolation resistor R1Multi-stage common-grid NMOS power amplifier tube M2、M3、M4And its isolation resistance R2、R3、R4And gate grounded capacitance C2、C3、C4The component is used for completing the power amplification of the radio frequency signal; the output and matching module 30 is composed of a load inductor Ld and an output matching blocking capacitor Co, and is used for completing output matching and blocking; the dynamic bias module 40 is composed of an input detection amplifier 41 and a bias adjusting module 42, specifically, the input detection amplifier 41 includes a sampling blocking capacitor C9And a single-ended amplifier Sa for sampling and amplifying the RF signal, the bias adjusting module 42 includes a diode-connected NMOS bias transistor M6、M7、M8The fixed bias module 421 formed by NMOS bias tube M5Bias resistor R5And a rectifying capacitor C5Composed of a variable bias module 422 and a diode D1、D2 A clamping unit 423 for dynamically adjusting the common source NMOS power amplifier tube M under the influence of the sampled RF signal output from the input sense amplifier 411Common gate NMOS power amplifier tube M2、M3、M4The bias voltage of (1).
Specifically, the radio frequency signal RFin is connected to the input matching inductor Lin and the sampling blocking capacitor C9And the other end of the input blocking matching capacitor Cin is connected to a common end of the common source NMOS power amplifying tube M1Gate and isolation resistor R1One end of (a); common source NMOS power amplifier tube M1The source electrode of the NMOS power amplifier is connected with a radio frequency ground RF GND and a common source NMOS power amplifier tube M1Is connected to the common-gate NMOS power amplifier tube M2Source and substrate of (1), common gate NMOS power amplifier tube M2Is connected to an isolation resistor R2One terminal of (1) and a gate grounding capacitor C2One terminal of (1), common gate NMOS power amplificationPipe M2Is connected to the common-gate NMOS power amplifier tube M3Source and substrate of (1), common gate NMOS power amplifier tube M3Is connected to an isolation resistor R3One terminal of (1) and a gate grounding capacitor C3One end of (1), a common gate NMOS power amplifier tube M3Is connected to the common-gate NMOS power amplifier tube M4Source and substrate of (1), common gate NMOS power amplifier tube M4Is connected to an isolation resistor R4One terminal of (1) and a gate grounding capacitor C4One terminal of (1), gate grounded capacitance C2、C3、C4The other end of the first and second electrodes is grounded; common-gate NMOS power amplifier tube M4The drain of the power amplifier is connected to the common end of a load inductor Ld and an output matching blocking capacitor Co, the other end of the load inductor Ld is connected with a power supply Vdd, and the other end of the output matching blocking capacitor Co is the output end RFout of the power amplifier;
sampling blocking capacitor C9Is connected to the input end of the single-ended amplifier Sa, the output end of the single-ended amplifier Sa is connected to the NMOS bias tube M5Drain electrode of (3), bias resistor R5And NMOS bias transistor M6Source and substrate, bias resistor R5Is connected to the NMOS bias tube M at the other end5Grid and diode D1Anode and rectifying capacitor C5And an isolation resistor R1Another terminal of (2), diode D1Cathode of (D) is connected with a diode2Anode of (2), NMOS bias tube M5Source and substrate, diode D2Cathode and rectifying capacitor C5The other end of the ground is connected with a radio frequency ground RF GND; NMOS bias tube M6Is connected to the NMOS bias tube M after being shorted with the grid electrode7Source and substrate and isolation resistor R2The other end of the NMOS bias tube M7Is connected to the NMOS bias tube M after being shorted with the grid electrode8Source and substrate isolation resistor R3The other end of the NMOS bias tube M8Is connected to the reference current Iref and the isolation resistor R after being shorted4And the other end of the same.
It can be seen that the input sense amplifier 41 of the present invention operates by collecting the input power and performing appropriate homotropic gain amplificationThe current is converted into the radio frequency signal current to be injected into the bias adjusting module 42, and the self-bias adjusting tube M5 of the bias adjusting module 42 adjusts the grid and drain voltage according to the injected current to realize the common-source NMOS power amplifying tube M1The NMOS bias tube M is adjusted under the constraint of reference current Iref6/M7/M8Sequentially adjusting the grid-drain voltage to M according to the drain voltage of the NMOS bias tube M52/M3/M4The gate bias adjustment is realized, the gate bias voltage of the power amplifier tube can be effectively adjusted according to the input power, the bias dc current is controlled to realize the power consumption self-adaptive input power dynamic adjustment, the PAE efficiency of the power backoff region can be effectively improved, and meanwhile, the clamping device 423 can protect the overlarge gate bias adjustment when the input power is maximum, so that the laminated power amplifier tube enters a linear region and the linearity is degraded.
Fig. 3 is a circuit diagram of another embodiment of a dynamically biased power amplifier according to the present invention. Preferably, as shown in fig. 3, the single-ended amplifier Sa is composed of an NMOS transistor M9、M10Self-bias resistor R9、R10Composition, self-bias resistance R9And NMOS tube M9Is connected to form the input terminal of the single-ended amplifier Sa, and a self-bias resistor R9The other end of the NMOS tube M is connected with the NMOS tube9Drain electrode of (1), NMOS tube M10Gate and self-bias resistor R10One terminal of (1), a self-bias resistor R10And the other end of the NMOS tube M10The drain electrodes of the NMOS transistors are connected to form the output end of the single-ended amplifier Sa, and the NMOS transistor M9、M10The grid and the substrate of the grid are connected with an analog ground;
preferably, as shown in fig. 3, the clamp 423 is formed by a current limiting resistor Rd and a diode-connected NMOS transistor MD1、MD2One end of a current limiting resistor Rd is connected with an NMOS bias tube M5The other end of the grid is connected with an NMOS tube MD1Drain and gate of (1), NMOS transistor MD1Source electrode and substrate of (1) connecting NMOS tube MD2Drain and gate of (1), NMOS transistor MD2The source and the substrate are connected to a radio frequency ground RF GND.
That is, in this embodiment, the input sense amplifier is formed by two stages of self-biased common source amplification, and the clamp is implemented by connecting a diode-connected MOS and a resistor in series, so that the maximum bias voltage of the clamp protection can be adjusted according to the maximum power output.
FIG. 4 is a simulation comparison of the present invention and the prior art. Through the simulation comparison of fig. 4, it can be seen that the power backoff region PAE can be effectively improved by adopting the dynamic bias technique, and the 6dB backoff point PAE is improved by > 5%.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (10)
1. A dynamically biased power amplifier, comprising:
the input and matching module is used for performing impedance matching and blocking on an input radio frequency signal;
the laminated power amplification module is used for carrying out power amplification on the matched radio-frequency signal under the control of the dynamic bias voltage;
the output and matching module is used for performing impedance matching and blocking on the output radio frequency signal of the stacked power amplification module;
and the dynamic bias module is used for generating dynamic bias voltage to the power amplification tube of the stacked power amplification module according to the size of the input radio frequency signal.
2. A dynamically biased power amplifier as claimed in claim 1, wherein: the dynamic biasing module further comprises:
the input detection amplifier is used for acquiring input power, performing appropriate homodromous gain amplification and converting the input power into a radio frequency signal current to be injected into the bias adjusting module;
and the bias adjusting module is used for dynamically adjusting the bias voltages of the common source NMOS power amplifying tube and the common gate NMOS power amplifying tube of the stacked power amplifying module under the influence of the sampling radio frequency signal output by the input detection amplifier.
3. A dynamically biased power amplifier as claimed in claim 2, wherein: the bias adjustment module includes:
the fixed bias module is used for sequentially adjusting the bias voltage of the gate leakage voltage to each common-gate NMOS power amplification tube of the stacked power amplification module under the constraint of the reference current to realize gate bias adjustment;
the variable bias module is used for adjusting the grid and drain voltage of an NMOS bias tube of the variable bias module according to the injection current so as to realize grid bias adjustment of a common source NMOS power amplification tube of the stacked power amplification module;
and the clamper is used for protecting each power amplification tube of the stacked power amplification module from entering a linear region when the grid bias is adjusted too much when the input power is maximum.
4. A dynamically biased power amplifier as claimed in claim 3, wherein: the fixed bias module comprises a diode-connected sixth NMOS bias tube (M)6) And a seventh NMOS bias transistor (M)7) And the eighth NMOS bias transistor (M)8) The eighth NMOS bias transistor (M)8) The grid-drain short circuit is connected to the reference current (Iref) and the stacked power amplification module, the seventh NMOS bias tube (M)7) The eighth NMOS bias tube (M) is connected after the grid leakage short circuit8) A source connected to the stacked power amplification module, the sixth NMOS bias transistor (M)6) The seventh NMOS bias tube (M) is connected after the grid leakage short circuit7) A source connected to the stacked power amplification module, the sixth NMOS bias transistor (M)6) And the source electrode is connected with the variable bias module.
5. A dynamically biased power amplifier as in claim 4 wherein: the variable bias module comprises an NMOS bias tube (M)5) Bias resistor (R)5) And a rectifying capacitor (C)5) Said bias resistor (R)5) One end of the sixth NMOS bias tube (M) is connected with6) Source electrode, said bias resistor (R)5) Another one isTerminal connected to the NMOS bias transistor (M)5) The rectifying capacitor (C)5) The clamp and the stacked power amplification module, the NMOS bias transistor (M)5) Source and substrate and said rectifying capacitor (C)5) The other end is connected with a radio frequency ground.
6. A dynamically biased power amplifier as claimed in claim 5, wherein: the clamp comprises a first diode (D)1) A second diode (D)2) The first diode (D)1) Is connected to the bias resistor (R)5) The rectifying capacitor (C)5) And the stacked power amplification module having a cathode connected to the second diode (D)2) The second diode (D)2) The cathode is connected to radio frequency ground.
7. A dynamically biased power amplifier as claimed in claim 5, wherein: the clamp comprises a current limiting resistor (Rd) and a diode connected first NMOS transistor (MD)1) And a second NMOS transistor (MD)2) One end of the current limiting resistor (Rd) is connected with the NMOS bias tube (M)5) The other end of the grid is connected with a first NMOS tube (MD)1) Drain and gate of (1), first NMOS transistor (MD)1) Is connected with the substrate of the second NMOS tube (MD)2) The second NMOS transistor (MD)2) The source and the substrate of (1) are connected to radio frequency ground.
8. A dynamically biased power amplifier as claimed in claim 6 or 7, characterized in that: the input detection amplifier comprises a sampling blocking capacitor (C)9) And a single-ended amplifier (Sa) to which the radio frequency signal RFin is connected9) One end, the sampling blocking capacitor (C)9) The other end is connected to the input end of the single-ended amplifier (Sa), and the output end of the single-ended amplifier (Sa) is connected to the NMOS bias tube (M)5) Drain electrode, bias resistor (R)5) And a sixth NMOS bias transistor (M)6) And a substrate.
9. A dynamically biased power amplifier as in claim 8, wherein: the single-ended amplifier (Sa) comprises a ninth NMOS transistor (M)9) And the tenth NMOS transistor (M)10) And a ninth self-bias resistor (R)9) And a tenth self-bias resistor (R)10) The ninth self-bias resistor (R)9) And the ninth NMOS transistor (M)9) Is connected to form an input terminal of the single-ended amplifier, and the ninth self-biasing resistor (R)9) The other end of the first NMOS tube is connected with a ninth NMOS tube (M)9) Drain electrode of (1), tenth NMOS tube (M)10) And a tenth self-biasing resistor (R)10) Said tenth self-biasing resistance (R)10) And the other end of the first NMOS transistor (M) and a tenth NMOS transistor (M)10) Is connected to form the output end of the single-ended amplifier, a ninth NMOS transistor (M)9) And the tenth NMOS transistor (M)10) The gate and substrate of (a) are connected to analog ground.
10. A dynamically biased power amplifier as in claim 9, wherein: the stacked power amplification module comprises a common source NMOS power amplification tube (M)1) And its gate isolation resistance (R)1) And a second common gate NMOS power amplifier tube (M)2) And a third common gate NMOS power amplifier tube (M)3) And the fourth common-gate NMOS power amplifier tube (M)4) And a second isolation resistance (R) thereof2) A third isolation resistor (R)3) And a fourth isolation resistor (R)4) And a second gate grounded capacitor (C)2) A third grid grounding capacitor (C)3) And a fourth gate grounded capacitor (C)4) The common source NMOS power amplifier tube (M)1) The grid is connected with the grid isolation resistor (R)1) And connected to the input and matching module, the source connected to RF ground, the drain connected to a second common-gate NMOS power amplifier transistor (M)2) The second common gate NMOS power amplifier tube (M)2) Is connected to a second isolation resistor (R)2) And a second gate grounded capacitance (C)2) The second common gate NMOS power amplifier tube (M)2) Is connected to the third common gate NMOSPower amplifier tube (M)3) Source and substrate, third common gate NMOS power amplifier tube (M)3) Is connected to the isolation resistor (R)3) And a third gate grounded capacitance (C)3) One terminal of (1), a third common gate NMOS power amplifier tube (M)3) Is connected to a fourth common gate NMOS power amplifier tube (M)4) Source and substrate, fourth common gate NMOS power amplifier tube (M)4) Is connected to a fourth isolation resistor (R)4) And a fourth gate grounded capacitance (C)4) Second gate grounded capacitance (C)2) A third grid grounding capacitor (C)3) And a fourth gate grounded capacitor (C)4) The other end of the first and second electrodes is grounded; fourth common gate NMOS power amplifier tube (M)4) The drain of which is connected to the output and matching module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110090071.5A CN112865727B (en) | 2021-01-22 | 2021-01-22 | Dynamic bias power amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110090071.5A CN112865727B (en) | 2021-01-22 | 2021-01-22 | Dynamic bias power amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112865727A true CN112865727A (en) | 2021-05-28 |
| CN112865727B CN112865727B (en) | 2024-04-12 |
Family
ID=76008057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110090071.5A Active CN112865727B (en) | 2021-01-22 | 2021-01-22 | Dynamic bias power amplifier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112865727B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112803905A (en) * | 2021-04-14 | 2021-05-14 | 广州慧智微电子有限公司 | Compensation circuit |
| CN115580233A (en) * | 2022-12-08 | 2023-01-06 | 西安博瑞集信电子科技有限公司 | Dynamic bias method and system of low-noise amplifier and dynamic bias circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020171483A1 (en) * | 2000-06-30 | 2002-11-21 | Shintaro Shinjo | High-frequency amplifier |
| CN1551486A (en) * | 2003-05-19 | 2004-12-01 | 三星电子株式会社 | Integratable, voltage-controlled RF power amplifier |
| CN102045032A (en) * | 2009-10-19 | 2011-05-04 | 财团法人工业技术研究院 | Power amplifier |
| CN103795356A (en) * | 2014-01-21 | 2014-05-14 | 浙江大学 | Envelope tracking radio frequency power amplifier |
| US20140191806A1 (en) * | 2013-01-04 | 2014-07-10 | Advanced Semiconductor Engineering Inc. | Electronic system - radio frequency power amplifier and method for dynamic adjusting bias point |
| CN111313849A (en) * | 2020-02-26 | 2020-06-19 | 上海华虹宏力半导体制造有限公司 | High-linearity radio frequency power amplifier |
-
2021
- 2021-01-22 CN CN202110090071.5A patent/CN112865727B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020171483A1 (en) * | 2000-06-30 | 2002-11-21 | Shintaro Shinjo | High-frequency amplifier |
| CN1551486A (en) * | 2003-05-19 | 2004-12-01 | 三星电子株式会社 | Integratable, voltage-controlled RF power amplifier |
| CN102045032A (en) * | 2009-10-19 | 2011-05-04 | 财团法人工业技术研究院 | Power amplifier |
| US20140191806A1 (en) * | 2013-01-04 | 2014-07-10 | Advanced Semiconductor Engineering Inc. | Electronic system - radio frequency power amplifier and method for dynamic adjusting bias point |
| CN103795356A (en) * | 2014-01-21 | 2014-05-14 | 浙江大学 | Envelope tracking radio frequency power amplifier |
| CN111313849A (en) * | 2020-02-26 | 2020-06-19 | 上海华虹宏力半导体制造有限公司 | High-linearity radio frequency power amplifier |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112803905A (en) * | 2021-04-14 | 2021-05-14 | 广州慧智微电子有限公司 | Compensation circuit |
| CN115580233A (en) * | 2022-12-08 | 2023-01-06 | 西安博瑞集信电子科技有限公司 | Dynamic bias method and system of low-noise amplifier and dynamic bias circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112865727B (en) | 2024-04-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106571780B (en) | A kind of adaptive-biased radio-frequency power amplifier | |
| US7522001B2 (en) | Power amplifier | |
| CN106452377B (en) | A kind of radio-frequency power amplifier of adaptive equalization | |
| US8680928B2 (en) | Power amplifier including variable capacitor circuit | |
| US7439805B1 (en) | Enhancement-depletion Darlington device | |
| US20110006846A1 (en) | High-frequency amplifier | |
| CN101764580A (en) | Systems and methods for an adaptive bias circuit for a differential power amplifier | |
| US20150188500A1 (en) | Power amplifier | |
| WO2017107949A1 (en) | Method for improving linearity of radio frequency power amplifier, compensation circuit and communication terminal | |
| CN112865727B (en) | Dynamic bias power amplifier | |
| JP4094239B2 (en) | amplifier | |
| US9024689B2 (en) | Electronic system—radio frequency power amplifier and method for self-adjusting bias point | |
| CN114679140B (en) | High linearity radio frequency power amplifier | |
| CN112886932B (en) | Power amplifier with linearization design | |
| KR101498786B1 (en) | Power amplifier | |
| CN111293997A (en) | Overvoltage protection and gain bootstrap circuit of power amplifier | |
| US11431306B2 (en) | Compensation circuit for amplitude modulation-amplitude modulation of radio frequency power amplifier | |
| WO2021208391A1 (en) | Circuit of power amplifier | |
| KR20120125811A (en) | Power amplifier | |
| US11444582B2 (en) | Power amplifier circuit | |
| US11233485B2 (en) | Power amplifier linearization circuit and related apparatus | |
| US7202743B2 (en) | High frequency amplifier | |
| CN111262534A (en) | Self-adaptive bias circuit for power amplifier chip | |
| CN106559050B (en) | A kind of differential amplifier circuit of self-adapting load | |
| CN211791445U (en) | Self-adaptive bias circuit for power amplifier chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |