CN112864318B - Resistive random access memory and method for making the same - Google Patents
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Abstract
The invention provides a resistive random access memory and a manufacturing method thereof, wherein a bottom buffer layer is formed between a bottom electrode and a resistive layer, the thermal expansion coefficient of the bottom buffer layer is between that of the bottom electrode and that of the resistance change layer; and forming an upper buffer layer between the upper electrode and the resistance change layer, wherein the thermal expansion coefficient of the upper buffer layer is between that of the upper electrode and that of the resistance change layer, and further, through the arrangement of the bottom buffer layer and the upper buffer layer, the thermal stress mismatch condition between the resistance change layer and the electrode of the resistive random access memory is eliminated, and the reliability and the yield of the resistive random access memory are improved.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a resistive random access memory and a manufacturing method thereof.
Background
The resistive random access memory is a novel nonvolatile memory technology, has a simple Metal-insulating layer-Metal sandwich structure, is completely compatible with a traditional CMOS (Complementary Metal-Oxide-Semiconductor) back-end process, and has lower working voltage and good reliability. In the case of an embedded storage, the storage, the method has important application prospect in logic circuits and neuromorphic calculation. The resistive random access memory can be directly integrated on the drain short of a transistor, and can be subjected to the thermal budget process of a standard process in the whole preparation process. When thermal stress mismatch occurs at the interface between the functional layer and the device electrode in the device, this causes a problem of initial yield.
Specifically, under the excitation of an external electric field, a conductive filament in a dielectric layer of the resistive random access memory is formed and broken, and the resistance value of the resistive random access memory is switched between a high resistance state and a low resistance state in a circulating manner. The conductive filament is formed and broken respectively write and erase operations of the memory. For the resistive random access memory, the retention characteristic and the reliability are two important performance indexes. Device reliability and composition of functional layer films of the device, the interface states are closely related. When the thermal expansion coefficients of the resistive function layer and the device electrode are not matched, the devices in the array can cause a heat accumulation effect due to the thermal crosstalk in the circulation process; it also causes reliability degradation due to thermal stress mismatch, which causes yield problems.
Disclosure of Invention
In view of this, the invention provides a resistive random access memory and a manufacturing method thereof, which effectively solve the technical problems in the prior art, eliminate the thermal stress mismatch between the electrode and the resistive layer of the resistive random access memory, and improve the reliability and yield of the resistive random access memory.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a resistance change memory comprising:
a substrate;
a bottom electrode on the substrate;
the bottom buffer layer is positioned on one side, away from the substrate, of the bottom electrode;
the resistance change layer is positioned on one side, away from the substrate, of the bottom buffer layer, wherein the thermal expansion coefficient of the bottom buffer layer is positioned between the thermal expansion coefficient of the bottom electrode and the thermal expansion coefficient of the resistance change layer;
the upper buffer layer is positioned on one side, away from the substrate, of the resistance change layer;
and the upper electrode is positioned on one side of the upper buffer layer, which is far away from the substrate, wherein the thermal expansion coefficient of the resistive layer is smaller than that of the bottom electrode and that of the upper electrode, and the thermal expansion coefficient of the upper buffer layer is positioned between that of the upper electrode and that of the resistive layer.
Optionally, the bottom buffer layer includes a first sub bottom buffer layer to an nth sub bottom buffer layer sequentially stacked along a direction from the substrate to the bottom electrode, and a thermal expansion coefficient of the first sub bottom buffer layer to a thermal expansion coefficient of the nth sub bottom buffer layer is in a decreasing trend;
the thermal expansion coefficient of the first sub-bottom buffer layer is smaller than or equal to that of the bottom electrode, the thermal expansion coefficient of the Nth sub-bottom buffer layer is larger than or equal to that of the resistance change layer, and N is a positive integer larger than or equal to 2.
Optionally, the upper buffer layer includes a first sub upper buffer layer to an mth sub upper buffer layer sequentially stacked in a direction from the upper electrode to the substrate, and a thermal expansion coefficient of the first sub upper buffer layer to a thermal expansion coefficient of the mth sub upper buffer layer decrease;
the thermal expansion coefficient of the first sub upper buffer layer is less than or equal to that of the upper electrode, the thermal expansion coefficient of the buffer layer on the Mth sub-layer is larger than or equal to that of the resistance change layer, and M is a positive integer larger than or equal to 2.
Optionally, the bottom buffer layer and the upper buffer layer are both oxide layers, and the thermal expansion coefficient of the bottom buffer layer and the thermal expansion coefficient of the upper buffer layer are determined according to the oxygen concentration of the oxide layers.
Optionally, the oxide layer is made of HfOx, alOx, tiOx or Ta 2 O 5 。
Optionally, the bottom electrode and the upper electrode are made of TiN, taN, cu, ir, al, ru or Pd;
and the thickness of the bottom electrode and the upper electrode ranges from 20 nm to 500nm, inclusive.
Optionally, the material of the resistance change layer is a binary metal oxide.
Correspondingly, the invention also provides a manufacturing method of the resistive random access memory, which comprises the following steps:
providing a substrate;
forming a bottom electrode on the substrate;
forming a bottom buffer layer on one side of the bottom electrode, which is far away from the substrate;
forming a resistance change layer on one side of the bottom buffer layer, which is far away from the substrate, wherein the thermal expansion coefficient of the bottom buffer layer is between that of the bottom electrode and that of the resistance change layer;
forming an upper buffer layer on one side of the resistance change layer, which is far away from the substrate;
and forming an upper electrode on one side of the upper buffer layer, which is far away from the substrate, wherein the thermal expansion coefficient of the resistive layer is smaller than that of the bottom electrode and that of the upper electrode, and the thermal expansion coefficient of the upper buffer layer is between that of the upper electrode and that of the resistive layer.
Optionally, forming a bottom buffer layer on a side of the bottom electrode facing away from the substrate includes:
sequentially overlapping along the direction from the substrate to the bottom electrode to form a bottom buffer layer comprising a first sub bottom buffer layer to an Nth sub bottom buffer layer, wherein the thermal expansion coefficient of the first sub bottom buffer layer to that of the Nth sub bottom buffer layer is reduced; the thermal expansion coefficient of the first sub bottom buffer layer is smaller than or equal to that of the bottom electrode, the thermal expansion coefficient of the Nth sub bottom buffer layer is larger than or equal to that of the resistance change layer, and N is a positive integer larger than or equal to 2.
Optionally, forming an upper buffer layer on a side of the resistance change layer away from the substrate includes:
sequentially overlapping and forming an upper buffer layer comprising a first sub upper buffer layer to an Mth sub upper buffer layer along the direction from the upper electrode to the substrate, wherein the thermal expansion coefficient of the first sub upper buffer layer to the thermal expansion coefficient of the Mth sub upper buffer layer is reduced; the thermal expansion coefficient of the first sub upper buffer layer is smaller than or equal to that of the upper electrode, the thermal expansion coefficient of the Mth sub upper buffer layer is larger than or equal to that of the resistance change layer, and M is a positive integer larger than or equal to 2.
Compared with the prior art, the method has the advantages that, the technical scheme provided by the invention at least has the following advantages:
the invention provides a resistive random access memory and a manufacturing method thereof, wherein the resistive random access memory comprises the following steps: a substrate; a bottom electrode on the substrate; the bottom buffer layer is positioned on one side, away from the substrate, of the bottom electrode; the resistance change layer is positioned on one side, away from the substrate, of the bottom buffer layer, wherein the thermal expansion coefficient of the bottom buffer layer is positioned between the thermal expansion coefficient of the bottom electrode and the thermal expansion coefficient of the resistance change layer; the upper buffer layer is positioned on one side, away from the substrate, of the resistance change layer; and the upper electrode is positioned on one side of the upper buffer layer, which is far away from the substrate, wherein the thermal expansion coefficient of the resistive layer is smaller than that of the bottom electrode and that of the upper electrode, and the thermal expansion coefficient of the upper buffer layer is positioned between that of the upper electrode and that of the resistive layer.
As can be seen from the above, the present invention provides a method for manufacturing a thin film transistor, which comprises forming a bottom buffer layer between a bottom electrode and a resistance change layer, the thermal expansion coefficient of the bottom buffer layer is positioned between the thermal expansion coefficient of the bottom electrode and the thermal expansion coefficient of the resistance change layer; and forming an upper buffer layer between the upper electrode and the resistance change layer, wherein the thermal expansion coefficient of the upper buffer layer is between that of the upper electrode and that of the resistance change layer, and further, through the arrangement of the bottom buffer layer and the upper buffer layer, the thermal stress mismatch condition between the resistance change layer and the electrode of the resistive random access memory is eliminated, and the reliability and the yield of the resistive random access memory are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a resistive random access memory according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another resistive random access memory according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another resistive random access memory according to an embodiment of the present invention;
fig. 4 is a flowchart of a method for manufacturing a resistive random access memory according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background art, the resistive random access memory is excited by an external electric field, the conductive filament in the dielectric layer of the resistive random access memory is formed and broken, and the resistance value of the conductive filament is cyclically switched between a high resistance state and a low resistance state. The conductive filament formation and breakage correspond to the writing and erasing operations of the memory, respectively. For the resistive random access memory, the retention characteristic and the reliability are two important performance indexes. The reliability of the device is closely related to the composition and interface state of the functional layer film of the device. When the thermal expansion coefficients of the resistive function layer and the device electrode are not matched, the devices in the array can cause a heat accumulation effect due to the thermal crosstalk in the circulation process; and also causes reliability degradation due to thermal stress mismatch, resulting in yield problems.
Based on this, the embodiment of the invention provides a resistive random access memory and a manufacturing method thereof, which effectively solve the technical problems in the prior art, eliminate the thermal stress mismatch between the electrode and the resistive layer of the resistive random access memory, and improve the reliability and yield of the resistive random access memory.
To achieve the above object, the technical solutions provided by the embodiments of the present invention are described in detail below, specifically with reference to fig. 1 and fig. 4.
As shown in fig. 1, a schematic structural diagram of a resistive random access memory provided in an embodiment of the present invention is shown, where the resistive random access memory includes:
a substrate 100.
A bottom electrode 200 on the substrate 100.
A bottom buffer layer 300 on a side of the bottom electrode 200 facing away from the substrate 100.
And a resistive layer 400 located on a side of the bottom buffer layer 300 facing away from the substrate 100, wherein a thermal expansion coefficient of the bottom buffer layer 300 is between a thermal expansion coefficient of the bottom electrode 200 and a thermal expansion coefficient of the resistive layer 400.
And an upper buffer layer 500 positioned on a side of the resistance change layer 400 facing away from the substrate 100.
And an upper electrode 600 disposed on a side of the upper buffer layer 500 away from the substrate 100, wherein a thermal expansion coefficient of the resistive layer 400 is smaller than a thermal expansion coefficient of the bottom electrode 200 and a thermal expansion coefficient of the upper electrode 600, and a thermal expansion coefficient of the upper buffer layer 500 is between the thermal expansion coefficient of the upper electrode 600 and the thermal expansion coefficient of the resistive layer 400.
It can be understood that, in the technical solution provided by the embodiment of the present invention, a bottom buffer layer is formed between the bottom electrode and the resistance change layer, and the thermal expansion coefficient of the bottom buffer layer is located between the thermal expansion coefficient of the bottom electrode and the thermal expansion coefficient of the resistance change layer; and an upper buffer layer is formed between the upper electrode and the resistance change layer, the thermal expansion coefficient of the upper buffer layer is positioned between the thermal expansion coefficient of the upper electrode and the thermal expansion coefficient of the resistance change layer, and further, through the arrangement of the bottom buffer layer and the upper buffer layer, the thermal stress of the interface between adjacent layer structures is more matched, the thermal stress mismatch condition between the electrode of the resistance change memory and the resistance change layer is eliminated, and the reliability and the yield of the resistance change memory are improved.
In an embodiment of the invention, the buffer layer can be prepared into a multilayer structure with a gradient thermal expansion coefficient, so that the thermal expansion coefficients of adjacent layer structures are gradually changed, the thermal stress mismatch between the adjacent layer structures of the resistive random access memory is further eliminated, and the reliability and yield of the resistive random access memory are further improved. Specifically, as shown in fig. 2, a schematic structural diagram of another resistive random access memory according to an embodiment of the present invention is provided, wherein the bottom buffer layer 300 according to the embodiment of the present invention includes a first sub bottom buffer layer 301 to an nth sub bottom buffer layer 30N sequentially stacked along a direction from the substrate 100 to the bottom electrode 200, and a thermal expansion coefficient of the first sub bottom buffer layer 301 to a thermal expansion coefficient of the nth sub bottom buffer layer 30N are reduced.
The thermal expansion coefficient of the first sub-bottom buffer layer 301 is less than or equal to that of the bottom electrode 200, the thermal expansion coefficient of the nth sub-bottom buffer layer 30N is greater than or equal to that of the resistive layer 400, and N is a positive integer greater than or equal to 2.
It should be noted that, in the direction from the bottom electrode to the resistive layer provided in the embodiment of the present invention, the thermal expansion coefficient between adjacent layer structures may be reduced by 20% or less, that is, between the bottom electrode and the first sub-bottom buffer layer, between the i-th sub-bottom buffer layer and the i + 1-th sub-bottom buffer layer, and between the N-th sub-bottom buffer layer and the resistive layer, is reduced by 20% or less, where i is an integer greater than or equal to 1 and less than N.
Further, in the above-mentioned case, the upper buffer layer provided by the embodiment of the invention can also be made into a multilayer structure with a gradually-changed thermal expansion coefficient. As shown in fig. 3, which is a schematic structural diagram of another resistive random access memory according to an embodiment of the present invention, the upper buffer layer 500 includes a first sub upper buffer layer 501 to an mth sub upper buffer layer 50M sequentially stacked along a direction from the upper electrode 500 to the substrate 100, and a thermal expansion coefficient of the first sub upper buffer layer 501 to a thermal expansion coefficient of the mth sub upper buffer layer 50M are decreased.
The thermal expansion coefficient of the first sub upper buffer layer 501 is smaller than or equal to that of the upper electrode 600, the thermal expansion coefficient of the mth sub upper buffer layer 50M is larger than or equal to that of the resistive layer 400, and M is a positive integer larger than or equal to 2.
It should be noted that, in the direction from the upper electrode to the resistive layer provided in the embodiment of the present invention, the thermal expansion coefficient between adjacent layer structures may be reduced by 20% or less, that is, the thermal expansion coefficient between the upper electrode and the first sub upper buffer layer, between the jth sub upper buffer layer and the jth +1 sub upper buffer layer, and between the nth sub upper buffer layer and the resistive layer is reduced by 20% or less, where j is an integer greater than or equal to 1 and less than M. Optionally, N and M provided in the embodiment of the present invention may be the same or different, that is, the number of sub bottom buffer layers included in the bottom buffer layer and the number of sub top buffer layers included in the top buffer layer may be the same or different, and thus, the need for this may be specifically designed according to the actual application.
In the present inventionIn an embodiment, the bottom buffer layer and the upper buffer layer provided in the present invention are both oxide layers, where the oxide layers may be oxide layers of insulating materials or oxide layers of semiconductor materials, which is not specific to the present invention. And the thermal expansion coefficient of the bottom buffer layer and the thermal expansion coefficient of the upper buffer layer provided by the embodiment of the invention are determined according to the oxygen concentration of the oxide layer, wherein when the bottom buffer layer and the upper buffer layer are of a laminated structure of a plurality of sub-layers, the change of the thermal expansion coefficients of different sub-layers can be realized by controlling the change of the oxygen concentration of each sub-layer. Alternatively to this, the first and second parts may, the material of the oxide layer provided by the embodiment of the invention can be HfOx, alOx, tiOx or Ta 2 O 5 . The bottom buffer layer and the upper buffer layer provided in the embodiment of the present invention may be formed by using a reactive sputtering method or the like to prepare corresponding oxide layers, and the oxygen concentration of the oxide layers may be controlled by using a thermal oxidation method, a reactive sputtering method, or a doping method, which is not limited in particular.
In an embodiment of the invention, the bottom electrode and the top electrode provided in the invention are made of TiN, taN, cu, ir, al, ru or Pd, and the invention is not limited thereto.
The thickness range of the bottom electrode and the upper electrode provided by the embodiment of the invention is 20-500nm, including endpoint values; for example, the thickness of the bottom electrode and the upper electrode can be 40nm, 80nm, 200nm, 400nm, etc., and the design is specifically carried out according to the practical application.
In an embodiment of the invention, the material of the resistance change layer provided by the invention is a binary metal oxide. Specifically, the material of the resistance change layer provided by the embodiment of the invention can be HfOx, alOx, tiOx or TaO x And the like, and the specific selection is carried out according to the actual application.
Correspondingly, the invention also provides a manufacturing method of the resistive random access memory. Specifically, as shown in fig. 4, a flowchart of a manufacturing method of a resistive random access memory provided in an embodiment of the present invention is shown, where the manufacturing method includes:
s1, providing a substrate.
And S2, forming a bottom electrode on the substrate.
And S3, forming a bottom buffer layer on one side of the bottom electrode, which is far away from the substrate.
And S4, forming a resistance change layer on one side of the bottom buffer layer, which is far away from the substrate, wherein the thermal expansion coefficient of the bottom buffer layer is positioned between the thermal expansion coefficient of the bottom electrode and the thermal expansion coefficient of the resistance change layer.
And S5, forming an upper buffer layer on one side of the resistance change layer, which is far away from the substrate.
And S6, forming an upper electrode on one side of the upper buffer layer, which is far away from the substrate, wherein the thermal expansion coefficient of the resistive layer is smaller than that of the bottom electrode and that of the upper electrode, and the thermal expansion coefficient of the upper buffer layer is between that of the upper electrode and that of the resistive layer.
In an embodiment of the invention, the buffer layer can be prepared into a multilayer structure with a gradient change of the thermal expansion coefficient, so that the thermal expansion coefficients between adjacent layer structures are in a gradient mode, the thermal stress mismatch between the adjacent layer structures of the resistive random access memory is further eliminated, and the reliability and the yield of the resistive random access memory are further improved. Specifically, the forming of the bottom buffer layer on the side of the bottom electrode away from the substrate according to the embodiment of the present invention includes:
sequentially overlapping along the direction from the substrate to the bottom electrode to form a bottom buffer layer comprising a first sub-bottom buffer layer to an Nth sub-bottom buffer layer, wherein the thermal expansion coefficient from the first sub-bottom buffer layer to the Nth sub-bottom buffer layer is in a decreasing trend; the thermal expansion coefficient of the first sub-bottom buffer layer is smaller than or equal to that of the bottom electrode, the thermal expansion coefficient of the Nth sub-bottom buffer layer is larger than or equal to that of the resistance change layer, and N is a positive integer larger than or equal to 2.
Furthermore, the upper buffer layer provided by the embodiment of the invention can also be made into a multi-layer structure with a gradually changing thermal expansion coefficient. That is, the forming of the upper buffer layer on the side of the resistance change layer away from the substrate according to the embodiment of the present invention includes:
sequentially overlapping and forming an upper buffer layer comprising a first sub upper buffer layer to an Mth sub upper buffer layer along the direction from the upper electrode to the substrate, wherein the thermal expansion coefficient of the first sub upper buffer layer to the thermal expansion coefficient of the Mth sub upper buffer layer is in a decreasing trend; the thermal expansion coefficient of the first sub upper buffer layer is smaller than or equal to that of the upper electrode, the thermal expansion coefficient of the Mth sub upper buffer layer is larger than or equal to that of the resistive layer, and M is a positive integer larger than or equal to 2.
It should be noted that, in the direction from the bottom electrode to the resistance change layer provided in the embodiment of the present invention, the thermal expansion coefficient between adjacent layer structures may decrease by 20% or less, that is, between the bottom electrode and the first sub-bottom buffer layer, between the ith sub-bottom buffer layer and the (i + 1) th sub-bottom buffer layer, and between the nth sub-bottom buffer layer and the resistance change layer decrease by 20% or less, where i is an integer greater than or equal to 1 and less than N.
The embodiment of the invention provides a resistive random access memory and a manufacturing method thereof, wherein the resistive random access memory comprises the following steps: a substrate; a bottom electrode on the substrate; the bottom buffer layer is positioned on one side, away from the substrate, of the bottom electrode; the resistance changing layer is positioned on one side, away from the substrate, of the bottom buffer layer, and the thermal expansion coefficient of the bottom buffer layer is positioned between that of the bottom electrode and that of the resistance changing layer; the upper buffer layer is positioned on one side, away from the substrate, of the resistance change layer; and the upper electrode is positioned on one side of the upper buffer layer, which is far away from the substrate, wherein the thermal expansion coefficient of the resistive layer is smaller than that of the bottom electrode and that of the upper electrode, and the thermal expansion coefficient of the upper buffer layer is positioned between that of the upper electrode and that of the resistive layer.
As can be seen from the above, in the technical solution provided in the embodiments of the present invention, the bottom buffer layer is formed between the bottom electrode and the resistive layer, and the thermal expansion coefficient of the bottom buffer layer is between the thermal expansion coefficient of the bottom electrode and the thermal expansion coefficient of the resistive layer; and forming an upper buffer layer between the upper electrode and the resistance change layer, wherein the thermal expansion coefficient of the upper buffer layer is between that of the upper electrode and that of the resistance change layer, and further, through the arrangement of the bottom buffer layer and the upper buffer layer, the thermal stress mismatch condition between the resistance change layer and the electrode of the resistive random access memory is eliminated, and the reliability and the yield of the resistive random access memory are improved.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A resistance change memory, characterized by comprising:
a substrate;
a bottom electrode on the substrate;
the bottom buffer layer is positioned on one side, away from the substrate, of the bottom electrode;
the resistance changing layer is positioned on one side, away from the substrate, of the bottom buffer layer, and the thermal expansion coefficient of the bottom buffer layer is positioned between that of the bottom electrode and that of the resistance changing layer;
the upper buffer layer is positioned on one side, away from the substrate, of the resistance change layer;
and the upper electrode is positioned on one side of the upper buffer layer, which is far away from the substrate, wherein the thermal expansion coefficient of the resistive layer is smaller than that of the bottom electrode and that of the upper electrode, and the thermal expansion coefficient of the upper buffer layer is positioned between that of the upper electrode and that of the resistive layer.
2. The resistive random access memory according to claim 1, wherein the bottom buffer layer comprises a first sub bottom buffer layer to an Nth sub bottom buffer layer which are sequentially stacked along a direction from the substrate to the bottom electrode, and a thermal expansion coefficient of the first sub bottom buffer layer to a thermal expansion coefficient of the Nth sub bottom buffer layer is reduced;
the thermal expansion coefficient of the first sub-bottom buffer layer is smaller than or equal to that of the bottom electrode, the thermal expansion coefficient of the Nth sub-bottom buffer layer is larger than or equal to that of the resistance change layer, and N is a positive integer larger than or equal to 2.
3. The resistive random access memory according to claim 1, wherein the upper buffer layer comprises a first sub upper buffer layer to an Mth sub upper buffer layer which are sequentially stacked in a direction from the upper electrode to the substrate, and a thermal expansion coefficient of the first sub upper buffer layer to a thermal expansion coefficient of the Mth sub upper buffer layer is reduced;
the thermal expansion coefficient of the first sub upper buffer layer is smaller than or equal to that of the upper electrode, the thermal expansion coefficient of the Mth sub upper buffer layer is larger than or equal to that of the resistive layer, and M is a positive integer larger than or equal to 2.
4. The resistive random access memory according to any one of claims 1 to 3, wherein the bottom buffer layer and the upper buffer layer are both oxide layers, and a thermal expansion coefficient of the bottom buffer layer and a thermal expansion coefficient of the upper buffer layer are determined according to an oxygen concentration of the oxide layers.
5. The RRAM of claim 4, wherein the oxide layer is made of HfOx, alOx, tiOx or Ta 2 O 5 。
6. The resistive random access memory according to claim 1, wherein the bottom electrode and the top electrode are made of TiN, taN, cu, ir, al, ru or Pd;
and the thickness of the bottom electrode and the upper electrode is in the range of 20-500nm, including the endpoint values.
7. The resistive random access memory according to claim 1, wherein the material of the resistive layer is a binary metal oxide.
8. A manufacturing method of a resistive random access memory is characterized by comprising the following steps:
providing a substrate;
forming a bottom electrode on the substrate;
forming a bottom buffer layer on one side of the bottom electrode, which is far away from the substrate;
forming a resistance change layer on one side of the bottom buffer layer, which is far away from the substrate, wherein the thermal expansion coefficient of the bottom buffer layer is between that of the bottom electrode and that of the resistance change layer;
forming an upper buffer layer on one side of the resistance change layer, which is far away from the substrate;
and forming an upper electrode on one side of the upper buffer layer, which is far away from the substrate, wherein the thermal expansion coefficient of the resistive layer is smaller than that of the bottom electrode and that of the upper electrode, and the thermal expansion coefficient of the upper buffer layer is between that of the upper electrode and that of the resistive layer.
9. The method for manufacturing a resistive random access memory according to claim 8, wherein forming a bottom buffer layer on a side of the bottom electrode facing away from the substrate includes:
sequentially overlapping along the direction from the substrate to the bottom electrode to form a bottom buffer layer comprising a first sub bottom buffer layer to an Nth sub bottom buffer layer, wherein the thermal expansion coefficient of the first sub bottom buffer layer to that of the Nth sub bottom buffer layer is reduced; the thermal expansion coefficient of the first sub bottom buffer layer is smaller than or equal to that of the bottom electrode, the thermal expansion coefficient of the Nth sub bottom buffer layer is larger than or equal to that of the resistance change layer, and N is a positive integer larger than or equal to 2.
10. The method for manufacturing the resistive random access memory according to claim 8, wherein forming an upper buffer layer on a side of the resistive layer away from the substrate includes:
sequentially overlapping and forming an upper buffer layer comprising a first sub upper buffer layer to an Mth sub upper buffer layer along the direction from the upper electrode to the substrate, wherein the thermal expansion coefficient of the first sub upper buffer layer to the thermal expansion coefficient of the Mth sub upper buffer layer is in a decreasing trend; the thermal expansion coefficient of the first sub upper buffer layer is smaller than or equal to that of the upper electrode, the thermal expansion coefficient of the Mth sub upper buffer layer is larger than or equal to that of the resistive layer, and M is a positive integer larger than or equal to 2.
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