CN112842312A - Heart rate sensor and self-adaptive heartbeat lock ring system and method thereof - Google Patents

Heart rate sensor and self-adaptive heartbeat lock ring system and method thereof Download PDF

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CN112842312A
CN112842312A CN202110135524.1A CN202110135524A CN112842312A CN 112842312 A CN112842312 A CN 112842312A CN 202110135524 A CN202110135524 A CN 202110135524A CN 112842312 A CN112842312 A CN 112842312A
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heart rate
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CN112842312B (en
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王国兴
马周辰
赵健
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Wang Guoxing
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Shanghai Jiaotong University
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    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/02—Detecting, measuring or recording pulse, heart rate, blood pressure or blood flow; Combined pulse/heart-rate/blood pressure determination; Evaluating a cardiovascular condition not otherwise provided for, e.g. using combinations of techniques provided for in this group with electrocardiography or electroauscultation; Heart catheters for measuring blood pressure
    • A61B5/024—Detecting, measuring or recording pulse rate or heart rate
    • A61B5/02416—Detecting, measuring or recording pulse rate or heart rate using photoplethysmograph signals, e.g. generated by infrared radiation
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/02—Detecting, measuring or recording pulse, heart rate, blood pressure or blood flow; Combined pulse/heart-rate/blood pressure determination; Evaluating a cardiovascular condition not otherwise provided for, e.g. using combinations of techniques provided for in this group with electrocardiography or electroauscultation; Heart catheters for measuring blood pressure
    • A61B5/024—Detecting, measuring or recording pulse rate or heart rate
    • A61B5/02438—Detecting, measuring or recording pulse rate or heart rate with portable devices, e.g. worn by the patient
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/68—Arrangements of detecting, measuring or recording means, e.g. sensors, in relation to patient
    • A61B5/6801—Arrangements of detecting, measuring or recording means, e.g. sensors, in relation to patient specially adapted to be attached to or worn on the body surface
    • A61B5/6802—Sensor mounted on worn items
    • A61B5/681—Wristwatch-type devices
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/72—Signal processing specially adapted for physiological signals or for diagnostic purposes
    • A61B5/7203—Signal processing specially adapted for physiological signals or for diagnostic purposes for noise prevention, reduction or removal
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/72—Signal processing specially adapted for physiological signals or for diagnostic purposes
    • A61B5/7225—Details of analog processing, e.g. isolation amplifier, gain or sensitivity adjustment, filtering, baseline or drift compensation
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/72—Signal processing specially adapted for physiological signals or for diagnostic purposes
    • A61B5/7235—Details of waveform analysis

Abstract

The invention provides a heart rate sensor and a self-adaptive heartbeat lock ring system and a method thereof, wherein the heart rate sensor comprises the following steps: the frequency digital converter receives the PPG clock signal and converts the PPG clock signal into a digital signal; the divider receives the digital signal and the frequency division multiple, and divides the digital signal by the frequency division multiple to obtain a frequency division digital signal; the digital filter filters high-frequency noise to obtain a digital heart rate signal; the heart rate differentiator receives the digital heart rate signal and the external clock signal and calculates the heart rate change rate signal in each external clock signal period; the comparator compares the ratio of the heart rate change rate signal to the critical out-of-lock heart rate change rate signal to obtain a frequency divider control signal; the window generator receives the digital heart rate signal and generates a window signal; the frequency divider receives the frequency divider control signal and the window signal to obtain the self-adaptive window signal after frequency division and the frequency division multiple and then outputs the self-adaptive window signal and the frequency division multiple. The invention adaptively adjusts the duty ratio of the output pulse of the LED driver, so that the power consumption of the LED is obviously reduced.

Description

Heart rate sensor and self-adaptive heartbeat lock ring system and method thereof
Technical Field
The invention relates to the technical field of wearable human body signal monitoring, in particular to a heart rate sensor and a low-power-consumption self-adaptive heartbeat lock ring system and method thereof.
Background
Heart rate is one of the most important health information, reflecting many cardiovascular problems. 24-hour heart rate monitoring is in widespread demand in people's daily lives. How to realize low-power consumption and wearable heart rate sensor is the key problem in the wearable human signal monitoring field. The existing heartbeat monitoring techniques mainly include Electrocardiography (ECG), Phonocardiography (PCG), ultrasonography and photoplethysmography (PPG). However, the photoplethysmography has been widely applied to wearable devices such as smart bracelets due to its advantages of small size, low cost, no electrode, etc.
However, in wearable devices, the battery capacity is limited, and therefore, there is a need to reduce the power consumption of the PPG chip. In the PPG chip, driving the LEDs to emit light consumes a significant portion of the power consumption. The power consumption of the LED driver must be reduced in order to extend the life cycle of the sensor. For reducing the power consumption of the LED driver, the following technologies are mainly used:
at, M.Wang, and G.Wang, "A full integrated high-sensitivity with a dynamic range sensor and an automatic dimming control driver," IEEE Sensors Journal, vol.18, No.2, pp.652-659,2018. A way to reduce the duty cycle and pulse repetition frequency of an LED is used, which can reduce the effective duty cycle of the LED to 1%, but the LED still consumes most of the power consumption.
The method of compressive sampling is adopted in P.V.Rajesh, J.M.Valero-Sarmiento et al, "a 172 μ w compressive sampling photoplethysmographic readout with embedded direct-heart-rate and variable-reliability extraction data," IEEE International Solid-State Circuit reference (ISSCC), pp.386-387,2016. the sparsity of PPG signal is utilized to reduce the effective duty cycle of LED to 0.0125%, but a large amount of power consumption is consumed for reconstructing the compressive sampling signal.
Jang and s.cho, "a 43.4 μ w photopolystemgram-based heart-beat-locked loop," IEEE International Solid State Circuits Conference (ISSCC), pp.474-476,2018. The LED is only on when the window is high, achieving a duty cycle of 0.0175%. Although in existing operation the turn-on time of the LEDs is significantly reduced, the power consumption is reduced accordingly. The LED still consumes the main power consumption in the PPG chip.
At present, no explanation or report of the similar technology of the invention is found, and similar data at home and abroad are not collected.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a heart rate sensor and a low-power-consumption self-adaptive heartbeat lock ring system and method thereof.
According to an aspect of the present invention, there is provided an adaptive heartbeat lock ring system, including: a heart rate calculator module and an adaptive window generator module; wherein:
the heart rate calculator module comprising:
the frequency digital converter submodule receives a PPG clock signal synchronous with heartbeat, converts the frequency of the PPG clock signal into a digital signal and outputs the digital signal;
the divider submodule receives the digital signal and the frequency division multiple, divides the digital signal by the frequency division multiple to obtain a frequency division digital signal and outputs the frequency division digital signal;
the digital filter submodule receives the frequency division digital signal, filters high-frequency noise to obtain a digital heart rate signal and outputs the digital heart rate signal;
the adaptive window generator module comprising:
the heart rate differentiator submodule receives the digital heart rate signal and the external clock signal, calculates a heart rate change rate signal in each external clock signal period and outputs the heart rate change rate signal;
the comparator submodule receives the heart rate change rate signal and the critical out-of-lock heart rate change rate signal, compares the ratio of the heart rate change rate signal to the critical out-of-lock heart rate change rate signal, obtains a frequency divider control signal and outputs the frequency divider control signal;
a window generator submodule which receives the digital heart rate signal, generates a window signal with the frequency consistent with that of the digital heart rate signal and outputs the window signal;
and the frequency divider submodule receives the frequency divider control signal and the window signal, determines the frequency division multiple of the window signal according to the frequency divider control signal, and outputs the self-adaptive window signal after frequency division and the frequency division multiple.
Preferably, the frequency-to-digital converter sub-module comprises: the clock generating device comprises a clock reference unit, a counter unit, a first register unit, a second register unit and a first subtracter unit; wherein:
the output end of the clock reference unit is connected with the input end of the counter unit, and the counter unit calculates and outputs the number of trigger edges of the reference clock output by the clock reference unit;
the input end of the first register unit is connected with the output end of the counter unit, the trigger port of the first register unit is connected with a PPG clock signal, the number of trigger edges of a reference clock output by the counter unit is sampled by using the input PPG clock signal, and the obtained output signal of the first register unit is accessed to the positive end of the first subtractor unit;
the input end of the second register unit is connected with the output end of the first register unit, the trigger port of the second register unit is connected with a PPG clock signal, the input PPG clock signal is used for sampling the output signal of the first register unit, and the obtained output signal of the second register unit is accessed to the negative end of the first subtracter unit.
The first subtractor unit receives output signals of the first register unit and the second register unit, and an output signal generated by subtraction is a digital signal obtained by converting the frequency signal of the PPG clock signal.
Preferably, the heart rate differentiator submodule comprises: a third register unit, a fourth register unit and a second subtractor unit; wherein:
the input end of the third register unit is connected with the digital filter submodule of the heart rate calculator module, the trigger port of the third register unit is connected with an external clock signal, the external clock signal is used for sampling the input digital heart rate signal, and the obtained output signal of the third register unit is accessed to the positive end of the second subtracter unit;
the input end of the fourth register unit is connected with the output end of the third register unit, the trigger port of the fourth register unit is connected with an external clock signal, the input output signal of the third register unit is sampled by the external clock signal, and the obtained output signal of the fourth register unit is accessed to the negative end of the second subtracter unit;
and the second subtracter unit receives the output signals of the third register unit and the fourth register unit, and the output signals generated by subtraction are the heart rate change rate signals in each external clock signal period.
According to another aspect of the present invention, there is provided an adaptive heartbeat lock loop method, including:
acquiring a PPG clock signal synchronous with heartbeat, and converting the frequency of the PPG clock signal into a digital signal;
acquiring a frequency division multiple, and dividing the digital signal by the frequency division multiple to obtain a frequency division digital signal;
filtering high-frequency noise from the frequency division digital signal to obtain a digital heart rate signal;
acquiring an external clock signal, and calculating a heart rate change rate signal in each external clock signal period based on the digital heart rate signal;
acquiring a critical loss-of-lock heart rate change rate signal, and calculating the ratio of the heart rate change rate signal to the critical loss-of-lock heart rate change rate signal to obtain a frequency divider control signal;
generating a window signal in accordance with the digital heart rate signal frequency based on the digital heart rate signal;
determining the frequency division multiple of the window signal according to the frequency divider control signal to obtain the self-adaptive window signal after frequency division and the frequency division multiple; the frequency division multiple is used for obtaining the frequency division digital signal, and the self-adaptive window signal is used for controlling the working time of the LED lamp.
Preferably, the obtaining a critical out-of-lock heart rate change rate signal, calculating a ratio of the heart rate change rate to the critical out-of-lock heart rate change rate, and obtaining a frequency divider control signal includes:
the change rate of the critical unlocked heart rate when the heart rate is increased is HR'up-criticalThe change rate in the case of heart rate reduction is HR'down-criticalAnd then:
Figure BDA0002926550250000041
Figure BDA0002926550250000042
wherein N is frequency division multiple, T is heartbeat period, and T is1Is the time distance, t, from the peak position of the PPG signal to the rising edge of the last window signal2The time distance from the peak position of the PPG signal to the falling edge of the last window signal;
calculating the heart rate change rate HR 'and the critical loss-of-lock heart rate change rate HR'criticalThe ratio of (b) is then:
Figure BDA0002926550250000043
when the LLF is smaller than 1/4, outputting a frequency divider control signal with an increased frequency division multiple, namely increasing the number of PPG signal waveforms spaced once when the LED is turned on;
when the LLF is greater than or equal to 1/4 and less than 1/2, outputting a frequency divider control signal with constant frequency division multiple, namely, the number of PPG signal waveforms spaced once when the LED is turned on is constant;
when the LLF is greater than or equal to 1/2 and less than 1, outputting a frequency divider control signal with a reduced frequency division multiple, namely, reducing the number of PPG signal waveforms spaced once when the LED is turned on;
and when the LLF is more than or equal to 1, not outputting a frequency divider control signal, and increasing the pulse width of the LED until the peak value of the PPG signal is detected.
Preferably, the rate of change of the critical loss of lock heart rate as the heart rate increases or decreases assumes the minimum of the absolute values of the rate of change.
According to a third aspect of the present invention, there is provided a heart rate sensor comprising: the system comprises an analog front-end circuit module, a PPG clock converter module, an LED driver module, a pulse generator module and the self-adaptive heartbeat lock ring system; wherein:
the analog front end circuit module is connected with the PPG clock converter module, the PPG clock converter module is connected with the self-adaptive heartbeat lock ring system, and the self-adaptive heartbeat lock ring system and the pulse generator module are respectively connected with the LED driver module.
Preferably, the analog front-end circuit module receives a current output by the photodiode and converts the current into a voltage signal; the voltage signal is amplified, filtered, sampled and held and then output to the PPG clock converter module;
the PPG clock converter module converts the voltage signal into a PPG clock signal and outputs the PPG clock signal to the self-adaptive heartbeat lock ring system;
and the self-adaptive window signal output by the self-adaptive heartbeat lock ring system and the pulse signal phase output by the pulse generator module are in phase-inversion to generate a driving signal, and the driving signal is output to the LED driver module to control the opening and closing of the LED.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following beneficial effects:
the self-adaptive heartbeat lock ring system and the method provided by the invention are applied to a heart rate sensor based on PPG signals, and can self-adaptively adjust the duty ratio of the output pulse of an LED driver according to the change speed of the heart rate, thereby reducing the opening time of an LED and obviously reducing the power consumption of the LED under the condition of ensuring that the heart rate reading is not influenced.
The heart rate sensor and the self-adaptive heartbeat lock ring system and method thereof provided by the invention solve the problem that the LED power consumption is larger in the existing heartbeat lock ring technology when the heart rate of a human body is calculated by utilizing a PPG signal acquisition chip.
The heart rate sensor and the self-adaptive heartbeat lock ring system and method thereof provided by the invention can sense the heart rate change speed of a human body and self-adaptively adjust the luminous duty ratio of the LED.
According to the heart rate sensor and the self-adaptive heartbeat lock ring system and method thereof provided by the invention, when the heart rate is stable, the peak position of the PPG signal is sampled once every N (N >1) intervals of PPG signal cycles, so that the power consumption of an LED can be saved, and the accuracy of heart rate calculation can not be influenced.
According to the heart rate sensor and the self-adaptive heartbeat lock ring system and method thereof, the change of the heart rate derivative is detected and sensed by introducing the heart rate change rate, the frequency division multiple of the output window of the heartbeat lock ring is self-adaptively adjusted, the duty ratio of the output pulse of the LED driver is reduced, and further the power consumption consumed by the LED in the PPG signal acquisition chip is reduced.
Compared with the traditional heartbeat lock ring technology, the heart rate sensor and the self-adaptive heartbeat lock ring system and method thereof provided by the invention have the advantage that the heart rate is reduced by 2.2-3.3 times when the PPG signal acquisition chip is used for calculating the heart rate of a human body.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a schematic block diagram of the structure of a heart rate sensor and its adaptive heartbeat lock ring system in a preferred embodiment of the present invention;
FIG. 2 is a block diagram of the heart rate calculator module of the adaptive heart beat locking ring system in a preferred embodiment of the invention;
FIG. 3 is a block diagram of the adaptive window generator module of the adaptive heartbeat loop system in a preferred embodiment of the present invention;
FIG. 4 is a schematic diagram of the heartbeat lock ring output window signal of the adaptive heartbeat lock ring system just under out-of-lock in accordance with a preferred embodiment of the present invention; the signal is (a) an output window signal of an adaptive heartbeat lock ring when the heart rate is constant, (b) an output window signal condition of the adaptive heartbeat lock ring when the heart rate is increased, and (c) an output window signal condition of the adaptive heartbeat lock ring when the heart rate is decreased.
Detailed Description
The following examples illustrate the invention in detail: the embodiment is implemented on the premise of the technical scheme of the invention, and a detailed implementation mode and a specific operation process are given. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.
An embodiment of the present invention provides an adaptive heartbeat lock loop system, which may include: a heart rate calculator module and an adaptive window generator module; wherein:
a heart rate calculator module comprising:
the frequency digital converter submodule receives a PPG clock signal synchronous with the heartbeat, converts the frequency of the PPG clock signal into a digital signal and outputs the digital signal;
the divider submodule receives the digital signal and the frequency division multiple output by the frequency divider submodule, divides the digital signal by the frequency division multiple to obtain a frequency division digital signal and outputs the frequency division digital signal;
the digital filter submodule receives the frequency division digital signal, filters high-frequency noise to obtain a digital heart rate signal and outputs the digital heart rate signal;
an adaptive window generator module comprising:
the heart rate differentiator submodule receives the digital heart rate signal and the external clock signal, calculates a heart rate change rate signal in each external clock signal period and outputs the heart rate change rate signal;
the comparator submodule receives the heart rate change rate signal and the critical out-of-lock heart rate change rate signal, compares the ratio of the heart rate change rate signal to the critical out-of-lock heart rate change rate signal, obtains a frequency divider control signal and outputs the frequency divider control signal;
the window generator submodule receives the digital heart rate signal, generates a window signal with the frequency consistent with that of the digital heart rate signal and outputs the window signal;
and the frequency divider submodule receives the frequency divider control signal and the window signal, determines the frequency division multiple of the window signal according to the frequency divider control signal, obtains the self-adaptive window signal after frequency division and the frequency division multiple, and outputs the self-adaptive window signal after frequency division and the frequency division multiple.
As a preferred embodiment, the frequency-to-digital converter sub-module may include: the clock generating device comprises a clock reference unit, a counter unit, a first register unit, a second register unit and a first subtracter unit; wherein:
the output end of the clock reference unit is connected with the input end of the counter unit, and the counter unit calculates and outputs the number of trigger edges of the reference clock output by the clock reference unit;
the input end of the first register unit is connected with the output end of the counter unit, the trigger port of the first register unit is connected with a PPG clock signal, the number of trigger edges of a reference clock output by the counter is sampled by using the input PPG clock signal, and the obtained output signal of the first register unit is accessed to the positive end of the first subtracter unit;
the input end of the second register unit is connected with the output end of the first register unit, the trigger port of the second register unit is connected with a PPG clock signal, the input PPG clock signal is used for sampling the output signal of the first register unit, and the obtained output signal of the second register unit (the output signal is the digital signal registered by the first register unit at the last PPG clock signal sampling moment when the PPG clock signal is sampled) is accessed to the negative end of the first subtracter unit;
the first subtracter unit receives output signals of the first register unit and the second register unit, and output signals generated by subtraction are digital signals obtained after conversion of the frequency signals of the PPG clock signals and then output.
As a preferred embodiment, the heart rate differentiator submodule may comprise: a third register unit, a fourth register unit and a second subtractor unit; wherein:
the input end of the third register unit is connected with a digital filter submodule of the heart rate calculator module, a trigger port of the third register unit is connected with an external clock signal, the external clock signal is used for sampling the input digital heart rate signal, and the obtained output signal of the third register unit (the output signal refers to the digital value of the real-time heart rate HR when the external clock signal triggers the third register unit) is accessed to the positive end of the second subtracter unit;
the input end of the fourth register unit is connected with the output end of the third register unit, the trigger port of the fourth register unit is connected with an external clock signal, the input output signal of the third register unit is sampled by the external clock signal, and the obtained output signal of the fourth register unit (the output signal is a digital signal registered by the third register unit at the previous sampling moment of the external clock signal when the external clock signal triggers sampling at the moment) is accessed to the negative end of the second subtracter unit;
and the second subtracter unit receives the output signals of the third register unit and the fourth register unit, subtracts the output signals to generate output signals, and outputs the output signals, namely the heart rate change rate signals in each external clock signal period.
Another embodiment of the present invention provides a method for adaptive heartbeat lock loop, which may include the following steps:
s1, obtaining a PPG clock signal synchronous with the heartbeat, and converting the frequency of the PPG clock signal into a digital signal;
s2, obtaining a frequency division multiple, and dividing the digital signal by the frequency division multiple to obtain a frequency division digital signal;
s3, filtering high-frequency noise of the frequency division digital signal to obtain a digital heart rate signal;
s4, acquiring an external clock signal, and calculating a heart rate change rate signal in each external clock signal period based on the digital heart rate signal;
s5, acquiring a critical out-of-lock heart rate change rate signal, and calculating the ratio of the heart rate change rate signal to the critical out-of-lock heart rate change rate signal to obtain a frequency divider control signal;
s6, generating a window signal with the frequency consistent with the frequency of the digital heart rate signal based on the digital heart rate signal;
s7, according to the frequency divider control signal, determining the frequency division multiple of the window signal, and obtaining the self-adaptive window signal after frequency division and the frequency division multiple; the frequency division multiple is used for obtaining a frequency division digital signal, and the self-adaptive window signal is used for controlling the working time of the LED lamp.
As a preferred embodiment, in S5, obtaining a critical out-of-lock heart rate variation rate signal, calculating a ratio of the heart rate variation rate to the critical out-of-lock heart rate variation rate, and obtaining a divider control signal includes:
the rate of change of critical loss-of-lock heart rate when heart rate increases is HR'up-criticalThe change rate in the case of heart rate reduction is HR'down-criticalAnd then:
Figure BDA0002926550250000081
Figure BDA0002926550250000082
wherein N is frequency division multiple, T is heartbeat period, and T is1Is the time distance, t, from the peak position of the PPG signal to the rising edge of the last window signal2The time distance from the peak position of the PPG signal to the falling edge of the last window signal;
calculating heart rate change rate HR 'and critical loss-of-lock heart rate change rate HR'criticalThe ratio of (b) is then:
Figure BDA0002926550250000091
when the LLF is smaller than 1/4, outputting a frequency divider control signal with the increased frequency division multiple, namely increasing the number of PPG signal waveforms spaced once when the LED is turned on;
when the LLF is greater than or equal to 1/4 and less than 1/2, outputting a frequency divider control signal with constant frequency division multiple, namely the number of PPG signal waveforms spaced once when the LED is turned on is constant;
when the LLF is greater than or equal to 1/2 and less than 1, outputting a frequency divider control signal with reduced frequency division multiple, namely, reducing the number of PPG signal waveforms spaced once when the LED is turned on;
when the LLF is larger than or equal to 1, the frequency divider control signal is not output, and the pulse width of the LED is increased until the peak value of the PPG signal is detected.
As a preferred embodiment, the rate of change of the critical loss of lock heart rate as the heart rate increases or decreases assumes the minimum of the absolute values of the rate of change.
A third embodiment of the present invention provides a heart rate sensor, which may include: the system comprises an analog front-end circuit module, a PPG clock converter module, an LED driver module, a pulse generator module and any one of the self-adaptive heartbeat lock ring systems; wherein:
the analog front end circuit module is connected with the PPG clock converter module, the PPG clock converter module is connected with the self-adaptive heartbeat lock ring system, and the self-adaptive heartbeat lock ring system and the pulse generator module are respectively connected with the LED driver module.
As a preferred embodiment, the analog front-end circuit module receives the current output by the photodiode and converts the current into a voltage signal; the voltage signal is amplified, filtered, sampled and held and then output to a PPG clock converter module;
the PPG clock converter module converts the voltage signal into a PPG clock signal and outputs the PPG clock signal to the self-adaptive heartbeat lock ring system;
and the self-adaptive window signal output by the self-adaptive heartbeat lock ring system and the pulse signal phase output by the pulse generator module are in phase-inversion to generate a driving signal, and the driving signal is output to the LED driver module to control the opening and closing of the LED.
The technical solutions provided by the above embodiments of the present invention are further described in detail below with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a heart rate sensor and an adaptive heartbeat lock ring system thereof according to the above embodiment of the present invention.
As shown in fig. 1, the adaptive heartbeat lock ring system provided by the above embodiment of the present invention may include the following modules: a heart rate calculator and an adaptive window generator.
Further, the heart rate sensor implemented by the adaptive heartbeat loop system may include the following modules: an analog front end circuit, a PPG clock converter, an LED driver, a pulse generator, and an adaptive heartbeat lock loop system according to any of the above embodiments of the invention.
One end of the analog front-end circuit is connected with the photodiode, and the other end of the analog front-end circuit is connected with the PPG clock converter. The analog front-end circuit receives current from the photodiode, converts the current into a voltage signal, and outputs the voltage signal after amplification, filtering, sampling and holding.
One end of the PPG clock converter is connected with the analog front-end circuit, and the other end of the PPG clock converter is connected with the heart rate calculator. The PPG clock converter module receives a voltage signal from the analog front-end circuit and converts the voltage signal into a PPG clock signal PPGCLKAnd output to the outside.
One end of the heart rate calculator is connected with the PPG clock converter, and the other end of the heart rate calculator is connected with the self-adaptive window generator and outputs the heart rate. As shown in fig. 2, the heart rate calculator is composed of 3 sub-modules, including: frequency-to-digital converter, divider, digital filter.
The frequency digital converter receives PPG clock signal synchronous with heartbeat from PPG clock converterCLKAnd PPG clock signal PPGCLKIs converted into a digital signal DFAnd output to the outside.
The divider receives the digital signal D output from the frequency-to-digital converterFAnd a frequency division multiple N, a digital signal D output from the frequency-to-digital converterFDividing by the frequency division multiple N to obtain the frequency division digital signal D of the dividerDAnd output to the outside.
The digital filter receives the frequency division digital signal D of the dividerDAnd filtering high-frequency noise to obtain a digital heart rate signal HR, and outputting the digital heart rate signal HR.
One end of the self-adaptive window generator is connected with the digital filter and receives the digital heart rate signal HR, and the other end is connected with the input end of the AND gate and outputs a self-adaptive window signal Wa. As shown in fig. 2, the adaptive window generator is mainly composed of 4 sub-modules, including: heart rate differentiator, comparator, frequency divider and window generator.
The heart rate differentiator receives the digital heart rate signal HR from the heart rate calculator and the external clock signal CLK, calculates a heart rate change rate signal HR 'in each period of the external clock signal CLK, and outputs the heart rate change rate signal HR' to the outside.
The comparator receives a heart rate change signal HR 'from the heart rate differentiator and a critical out-of-lock heart rate change signal HR'criticalA comparator compares the rate of change signal of heart rate HR 'with a critical out-of-lock heart rate of change signal HR'criticalTo obtain the divider control signal CfdAnd output to the outside.
The window generator receives the digital heart rate signal HR from the heart rate calculator, generates a window signal W in accordance with the frequency of the digital heart rate signal HR, and outputs the window signal W to the outside.
The frequency divider receives a frequency divider control signal C from the comparatorfdAnd a window signal W of the window generator. According to divider control signal CfdDetermining the frequency division multiple of the window signal W to obtain the self-adaptive window signal W after frequency divisionaAnd a frequency division multiple N, and outputting the frequency division multiple N to the outside.
LED driver receiving adaptive window signal WaSignal L after and of pulse generatorDThe output of the LED driver controls the turning on and off of the LEDs.
The principle of the self-adaptive heartbeat lock ring system is as follows:
the time interval of the peak position of the PPG signal is the heart rate period, so that the heart rate can be measured as long as the peak position of the PPG signal is sampled. Since the heart rate is stationary for most of the day, it is not necessary to sample the peak of the PPG signal for each heart beat. By the self-adaptive heartbeat lock ring technology, the change condition of the heart rate is automatically sensed, and the luminous duty ratio of the LED is self-adaptively adjusted. When the heart rate is stable, the LED is turned on once due to the PPG signal waveforms with more intervals, one peak of the PPG signal waveform is sampled, and the LED is turned on once due to the 4 PPG signal waveforms with the maximum intervals. When the heart rate fluctuates, the PPG waveform LED with less intervals is turned on once, the peak value of the PPG signal is sampled, and each PPG signal waveform LED is turned on once at least.
In the self-adaptive heartbeat lock ring system, a heart rate calculator calculates a PPG clock signal PPGCLKI.e. the real-time heart rate HR. The window generator will generate a window W with a frequency that coincides with the real-time heart rate HR. A heart rate differentiator in the self-adaptive window generator differentiates the real-time heart rate to calculate the heart rate change rate HR'. Comparing the heart rate variation rate HR ' with a critical loss-of-lock heart rate variation rate HR ' by a comparator 'criticalDetermines the frequency division multiple of the output window of the window generator by the frequency divider. Adaptive window signal W output by frequency divideraThe LED is controlled to be switched on and off, so that the heart rate change condition can be automatically sensed, and the LED light-emitting duty ratio can be adaptively adjusted.
As shown in fig. 2, the frequency-to-digital converter module in the heart rate calculator is composed of a clock reference, a counter, a first register 1, a second register 2 and a first subtracter. The output of the clock reference is connected with the input end of the counter, and the counter calculates and outputs the number of the triggering edges of the reference clock. The input port of the first register 1 is connected with the output of the counter, and the trigger port is connected with a PPG clock signal PPGCLKThe input signal is sampled, and the output signal obtained by sampling is connected to the positive end of the subtracter. The input port of the second register 2 is connected with the output of the first register 1, and the trigger port is connected with a PPG clock signal PPGCLKAnd sampling the input signal, and accessing the output signal obtained by sampling to the negative end of the first subtracter. The first subtracter receives the output signals of the first register 1 and the second register 2, and the output signals are generated by subtracting and output outwards.
As shown in fig. 3, the heart rate differentiator module in the adaptive window generator is composed of a third register 3, a fourth register 4 and a second subtractor. The input port of the third register 3 is connected with the heart rate calculator, the trigger port is connected with an external clock signal CLK, the input signal is sampled, and the output signal obtained by sampling is connected to the positive end of the subtracter. An input port of the fourth register 4 is connected with the output of the third register 3, a trigger port is connected with an external clock signal CLK, an input signal is sampled, and an output signal obtained by sampling is accessed to the negative end of the second subtracter. The second subtracter receives the output signals of the third register 3 and the fourth register 4, and the output signals are generated by subtracting and output outwards.
Based on the output window signal of the adaptive heart beat lock loop when the heart rate is constant as shown in fig. 4 (a), fig. 4 (b) and (c) show the situation that the window of the next moment just fails to lock the peak of the PPG signal when the heart rate increases or decreases, respectively. The critical loss-of-lock heart rate change rate at increased heart rate is HR'up-criticalAnd the critical unlocked heart rate change rate when the heart rate is reduced is HR'down-criticalRespectively as follows:
Figure BDA0002926550250000121
Figure BDA0002926550250000122
where N is the frequency division multiple, T is the heartbeat period, T is1Is the time distance, t, from the peak position of the PPG signal to the rising edge of the last window2Is the time distance from the peak position of the PPG signal to the last window falling edge. Critical loss-of-lock heart rate change rate HR'criticalThe lesser of the absolute values of the critical unlocked rate of change of heart rate as the heart rate increases or decreases.
The loss-of-lock factor LLF is defined as a heart rate change rate HR 'and a critical loss-of-lock heart rate change rate HR'criticalThe ratio of (a) to (b).
Figure BDA0002926550250000123
The loss-of-lock factor LLF is compared with 1/4, 1/2, 1 by a comparator. When the loss-of-lock factor LLF is less than 1/4, the frequency division multiple is increased, namely the number of PPG waveforms spaced after the LED is turned on once is increased. When the LLF is between 1/4 and 1/2, the frequency dividing ratio is unchanged, namely the number of PPG waveforms spaced once the LED is turned on is unchanged. When the loss-of-lock factor LLF is between 1/2 and 1, the frequency division multiple is reduced, namely the number of PPG waveforms spaced when the LED is turned on once is reduced. When the unlocking factor is larger than 1, the LED can not lock the peak position of the PPG signal at the moment. Therefore, the frequency is not divided, and the pulse width of the window generator is increased, i.e. the pulse width of the LED is increased from the lowest 100 ms to 400 ms, if the PPG peak is not detected yet, the LED is always on until the PPG signal peak is detected.
In this embodiment, the PPG signal refers to the number of cycles of the human PPG signal across which the LED is turned on once. As shown in fig. 4, when the second window comes, three PPG signal cycles apart from the first window.
The technical solutions or common technical means in the above embodiments of the present invention are not described herein again.
The self-adaptive heartbeat lock ring system and the method provided by the embodiment of the invention are applied to a heart rate sensor based on PPG signals, and can self-adaptively adjust the duty ratio of the output pulse of an LED driver according to the change speed of the heart rate, so that the on-time of an LED is reduced under the condition of ensuring that the heart rate reading is not influenced, and the power consumption of the LED is remarkably reduced; when the PPG signal acquisition chip is used for calculating the heart rate of a human body, the problem that the LED power consumption is large in the conventional heartbeat lock ring technology is solved; the heart rate change speed of a human body can be sensed, and the luminous duty ratio of the LED can be adjusted in a self-adaptive manner; when the heart rate is stable, the peak position of the PPG signal is sampled once every N (N is more than 1) intervals, so that the power consumption of an LED can be saved, and the accuracy of heart rate calculation can not be influenced; the change of heart rate derivative is detected and sensed by introducing the heart rate change rate, the frequency division multiple of an output window of a heartbeat lock ring is adaptively adjusted, the duty ratio of output pulses of an LED driver is reduced, and further the power consumption consumed by an LED in a PPG signal acquisition chip is reduced; when utilizing PPG signal acquisition chip to calculate human heart rate, compare current heartbeat catch ring technique and reduced 2.2 ~ 3.3 times.
It should be noted that, the steps in the method provided by the present invention can be implemented by using corresponding modules, devices, units, and the like in the system, and those skilled in the art can implement the step flow of the method by referring to the technical scheme of the system, that is, the embodiment in the system can be understood as a preferred example of the implementation method, and details are not described herein.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes and modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention.

Claims (8)

1. An adaptive heartbeat lock ring system, comprising: a heart rate calculator module and an adaptive window generator module; wherein:
the heart rate calculator module comprising:
the frequency digital converter submodule receives a PPG clock signal synchronous with heartbeat, converts the frequency of the PPG clock signal into a digital signal and outputs the digital signal;
the divider submodule receives the digital signal and the frequency division multiple, divides the digital signal by the frequency division multiple to obtain a frequency division digital signal and outputs the frequency division digital signal;
the digital filter submodule receives the frequency division digital signal, filters high-frequency noise to obtain a digital heart rate signal and outputs the digital heart rate signal;
the adaptive window generator module comprising:
the heart rate differentiator submodule receives the digital heart rate signal and the external clock signal, calculates a heart rate change rate signal in each external clock signal period and outputs the heart rate change rate signal;
the comparator submodule receives the heart rate change rate signal and the critical out-of-lock heart rate change rate signal, compares the ratio of the heart rate change rate signal to the critical out-of-lock heart rate change rate signal, obtains a frequency divider control signal and outputs the frequency divider control signal;
a window generator submodule which receives the digital heart rate signal, generates a window signal with the frequency consistent with that of the digital heart rate signal and outputs the window signal;
and the frequency divider submodule receives the frequency divider control signal and the window signal, determines the frequency division multiple of the window signal according to the frequency divider control signal, and outputs the self-adaptive window signal after frequency division and the frequency division multiple.
2. The adaptive heartbeat lock loop system as in claim 1, wherein said frequency-to-digital converter sub-module comprises: the clock generating device comprises a clock reference unit, a counter unit, a first register unit, a second register unit and a first subtracter unit; wherein:
the output end of the clock reference unit is connected with the input end of the counter unit, and the counter unit calculates and outputs the number of trigger edges of the reference clock output by the clock reference unit;
the input end of the first register unit is connected with the output end of the counter unit, the trigger port of the first register unit is connected with a PPG clock signal, the number of trigger edges of a reference clock output by the counter unit is sampled by using the input PPG clock signal, and the obtained output signal of the first register unit is accessed to the positive end of the first subtractor unit;
the input end of the second register unit is connected with the output end of the first register unit, the trigger port of the second register unit is connected with a PPG clock signal, the input PPG clock signal is used for sampling the output signal of the first register unit, and the obtained output signal of the second register unit is accessed to the negative end of the first subtracter unit.
The first subtractor unit receives output signals of the first register unit and the second register unit, and an output signal generated by subtraction is a digital signal obtained by converting the frequency signal of the PPG clock signal.
3. The adaptive heart beat locking ring system of claim 1, wherein the heart rate differentiator submodule comprises: a third register unit, a fourth register unit and a second subtractor unit; wherein:
the input end of the third register unit is connected with the digital filter submodule of the heart rate calculator module, the trigger port of the third register unit is connected with an external clock signal, the external clock signal is used for sampling the input digital heart rate signal, and the obtained output signal of the third register unit is accessed to the positive end of the second subtracter unit;
the input end of the fourth register unit is connected with the output end of the third register unit, the trigger port of the fourth register unit is connected with an external clock signal, the input output signal of the third register unit is sampled by the external clock signal, and the obtained output signal of the fourth register unit is accessed to the negative end of the second subtracter unit;
and the second subtracter unit receives the output signals of the third register unit and the fourth register unit, and the output signals generated by subtraction are the heart rate change rate signals in each external clock signal period.
4. An adaptive heartbeat lock loop method, comprising:
acquiring a PPG clock signal synchronous with heartbeat, and converting the frequency of the PPG clock signal into a digital signal;
acquiring a frequency division multiple, and dividing the digital signal by the frequency division multiple to obtain a frequency division digital signal;
filtering high-frequency noise from the frequency division digital signal to obtain a digital heart rate signal;
acquiring an external clock signal, and calculating a heart rate change rate signal in each external clock signal period based on the digital heart rate signal;
acquiring a critical loss-of-lock heart rate change rate signal, and calculating the ratio of the heart rate change rate signal to the critical loss-of-lock heart rate change rate signal to obtain a frequency divider control signal;
generating a window signal in accordance with the digital heart rate signal frequency based on the digital heart rate signal;
determining the frequency division multiple of the window signal according to the frequency divider control signal to obtain the self-adaptive window signal after frequency division and the frequency division multiple; the frequency division multiple is used for obtaining the frequency division digital signal, and the self-adaptive window signal is used for controlling the working time of the LED lamp.
5. The adaptive heartbeat lock loop method of claim 4, wherein said obtaining a critical out-of-lock heart rate of change signal, calculating a ratio of said rate of change to said critical out-of-lock heart rate of change, and deriving a divider control signal comprises:
the change rate of the critical unlocked heart rate when the heart rate is increased is HR'up-criticalThe change rate in the case of heart rate reduction is HR'down-criticalAnd then:
Figure FDA0002926550240000031
Figure FDA0002926550240000032
wherein N is frequency division multiple, T is heartbeat period, and T is1Is the time distance, t, from the peak position of the PPG signal to the rising edge of the last window signal2The time distance from the peak position of the PPG signal to the falling edge of the last window signal;
calculating the heart rate change rate HR 'and the critical loss-of-lock heart rate change rate HR'criticalThe ratio of (b) is then:
Figure FDA0002926550240000033
when the LLF is smaller than 1/4, outputting a frequency divider control signal with an increased frequency division multiple, namely increasing the number of PPG signal waveforms spaced once when the LED is turned on;
when the LLF is greater than or equal to 1/4 and less than 1/2, outputting a frequency divider control signal with constant frequency division multiple, namely, the number of PPG signal waveforms spaced once when the LED is turned on is constant;
when the LLF is greater than or equal to 1/2 and less than 1, outputting a frequency divider control signal with a reduced frequency division multiple, namely, reducing the number of PPG signal waveforms spaced once when the LED is turned on;
and when the LLF is more than or equal to 1, not outputting a frequency divider control signal, and increasing the pulse width of the LED until the peak value of the PPG signal is detected.
6. The adaptive heart beat locking ring method according to claim 5, wherein the rate of change of the critical heart rate at increasing or decreasing heart rate assumes the minimum of the absolute values of the rate of change.
7. A heart rate sensor, comprising: an analog front end circuit module, a PPG clock converter module, an LED driver module, a pulse generator module, and the adaptive heartbeat lock loop system of any of claims 1 to 3; wherein:
the analog front end circuit module is connected with the PPG clock converter module, the PPG clock converter module is connected with the self-adaptive heartbeat lock ring system, and the self-adaptive heartbeat lock ring system and the pulse generator module are respectively connected with the LED driver module.
8. The heart rate sensor of claim 1, wherein the analog front end circuit module receives a current output by a photodiode and converts the current into a voltage signal; the voltage signal is amplified, filtered, sampled and held and then output to the PPG clock converter module;
the PPG clock converter module converts the voltage signal into a PPG clock signal and outputs the PPG clock signal to the self-adaptive heartbeat lock ring system;
and the self-adaptive window signal output by the self-adaptive heartbeat lock ring system and the pulse signal phase output by the pulse generator module are in phase-inversion to generate a driving signal, and the driving signal is output to the LED driver module to control the opening and closing of the LED.
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