CN112838850A

CN112838850A - Power-on reset circuit, integrated circuit and electronic equipment

Info

Publication number: CN112838850A
Application number: CN202011613915.1A
Authority: CN
Inventors: 刘帅锋
Original assignee: Hefei Chipsea Electronics Technology Co Ltd
Current assignee: Hefei Chipsea Electronics Technology Co Ltd
Priority date: 2020-12-30
Filing date: 2020-12-30
Publication date: 2021-05-25
Also published as: WO2022143301A1

Abstract

The embodiment of the application provides a power-on reset circuit, an integrated circuit and an electronic device, wherein the power-on reset circuit comprises a current generation circuit, a threshold control circuit and a reset output circuit, wherein the current generation circuit is used for generating a reference voltage and a first current signal with a positive temperature coefficient; the threshold control circuit is used for generating a first driving voltage with a negative temperature coefficient according to the power supply voltage and determining a reset threshold voltage according to the first current signal and the first driving voltage; the reset output circuit is used for outputting a reset signal when the power supply voltage crosses a reset threshold voltage, wherein when the first driving voltage is equal to the reference voltage, the power supply voltage is equal to the reset threshold voltage. The reset threshold voltage in the embodiment of the application can be properly valued through the positive temperature coefficient and the negative temperature coefficient, so that the reset threshold voltage can have a zero temperature coefficient, and the reset threshold voltage is not influenced by conditions such as process, power supply and temperature.

Description

Power-on reset circuit, integrated circuit and electronic equipment

Technical Field

The application relates to the technical field of electronic circuits, in particular to a power-on reset circuit, an integrated circuit and electronic equipment.

Background

The circuit of the microprocessor chip is a digital sequential circuit, and the normal operation of the circuit needs to ensure that the power supply voltage is within a certain range and the clock signal is stable. Therefore, in the power-on process of the power supply, in order to avoid the situations of dead halt, program runaway and the like, a power-on reset signal is needed to reset the chip, and the reset is released only after the voltage rises to a certain range and the clock is stably output. The circuit that generates the power-on reset signal is referred to as a power-on reset circuit.

The accuracy of the power-on and power-off reset threshold is one of the important indexes of the power-on reset threshold. The power-on and power-off reset threshold value has a certain variation range under the influence of application conditions such as process variation, power supply and temperature. Taking a power-on reset release threshold as an example, if the threshold is too large, the lowest available voltage of the chip is limited; if the threshold is too small, the reset may be released in advance when the power supply voltage does not reach the normal working voltage of the chip, which may cause system abnormality. Therefore, how to make the power-on reset threshold not affected by the conditions of the process, the power supply, the temperature, and the like is a hot spot studied by those skilled in the art.

Disclosure of Invention

In view of the above problems, embodiments of the present application provide a power-on reset circuit, an integrated circuit, and an electronic device to solve the above technical problems.

The embodiment of the application is realized by adopting the following technical scheme:

a power-on reset circuit comprises a current generation circuit, a threshold control circuit and a reset output circuit, wherein the current generation circuit is used for generating a reference voltage and a first current signal with a positive temperature coefficient; the threshold control circuit is connected with the current generation circuit and used for generating a first driving voltage with a negative temperature coefficient according to the power supply voltage and determining a reset threshold voltage according to the first current signal and the first driving voltage; the reset output circuit is connected to the threshold control circuit for outputting a reset signal when the power supply voltage crosses a reset threshold voltage, wherein the power supply voltage is equal to the reset threshold voltage when the first driving voltage is equal to the reference voltage.

In some embodiments, the threshold control circuit includes a current mirror branch and a voltage divider circuit: the current mirror branch circuit is used for generating a second current signal mirrored in the first current signal according to the reference voltage; the first end of the voltage division circuit is used for being connected with a power supply, the second end of the voltage division circuit is grounded, a voltage division node is arranged between the first end and the second end of the voltage division circuit and connected to the current mirror branch, and the voltage division circuit is used for generating a first driving voltage at the voltage division node according to the power supply voltage and determining a reset threshold signal according to a second current signal and the first driving voltage.

In some embodiments, the reset output circuit is connected to the voltage dividing node and the current generating circuit, and is configured to generate a third current signal according to the first driving voltage, and output a reset signal according to the third current signal when the power supply voltage crosses the reset threshold voltage; when the first driving voltage is equal to the reference voltage, the third current signal is the same as the first current signal, and when the third current signal is the same as the first current signal, the power voltage is equal to the reset threshold voltage.

In some embodiments, the reset threshold voltage comprises a power-on reset threshold voltage and a power-down reset threshold voltage; the threshold control circuit comprises a hysteresis circuit, and the hysteresis circuit is respectively connected with the voltage division circuit and the current mirror branch circuit and is used for determining the difference value between the power-on reset threshold voltage and the power-off reset threshold voltage.

In some embodiments, the current generation circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a first impedance unit; the source electrode of the first MOS tube is connected with a power supply, the drain electrode of the first MOS tube is connected with the first end of the first impedance unit, and the grid electrode of the first MOS tube is connected with the grid electrode of the third MOS tube; the grid electrode of the second MOS tube is connected to the first end of the first impedance unit, the drain electrode of the second MOS tube is connected to the second end of the first impedance unit, and the source electrode of the second MOS tube is grounded; the source electrode of the third MOS tube is connected with the power supply, the drain electrode of the third MOS tube is connected with the drain electrode of the fourth MOS tube, and the drain electrode of the third MOS tube is connected with the grid electrode; the source electrode of the fourth MOS tube is grounded, and the grid electrode of the fourth MOS tube is connected to the second end of the first impedance unit; the second end of the first impedance unit is used for outputting a reference voltage, and the drain electrode of the third MOS tube and the drain electrode of the fourth MOS tube are used for outputting a first current signal.

In some embodiments, the current mirror branch comprises a fifth MOS transistor, a drain of the fifth MOS transistor is connected to the voltage dividing node, a source of the fifth MOS transistor is grounded, and a gate of the fifth MOS transistor is connected to a gate of the fourth MOS transistor; the voltage division circuit comprises a second impedance unit and a third impedance unit, wherein the first end of the second impedance unit is connected with the power supply, and the second end of the second impedance unit is connected with the first end of the third impedance unit; the second end of the third impedance unit is grounded; the connection node of the second impedance unit and the third impedance unit is a voltage division node.

In some embodiments, the reset output circuit includes a sixth MOS transistor, a seventh MOS transistor, and a first inverter; the source electrode of the sixth MOS tube is connected with the power supply, the drain electrode of the sixth MOS tube is connected with the drain electrode of the seventh MOS tube, and the grid electrode of the sixth MOS tube is connected with the drain electrode of the third MOS tube; the source electrode of the seventh MOS tube is grounded, and the grid electrode of the seventh MOS tube is connected to the voltage division node; the input end of the first phase inverter is connected between the drain electrode of the sixth MOS tube and the drain electrode of the seventh MOS tube, and the output end of the first phase inverter is used for outputting a reset signal.

In some embodiments, the current mirror branch further includes an eighth MOS transistor, a drain of the eighth MOS transistor is connected to the voltage dividing node, a source is grounded, and a gate is used for receiving a reference voltage; the hysteresis circuit comprises a second inverter, a fourth impedance unit, a ninth MOS (metal oxide semiconductor) transistor and a tenth MOS transistor; the drain electrode of the ninth MOS tube is connected to the source electrode of the eighth MOS tube, and the source electrode of the ninth MOS tube is grounded; the fourth impedance unit is connected between the second end of the voltage division circuit and the ground; the drain electrode and the source electrode of the tenth MOS tube are connected with two ends of the fourth impedance unit in parallel; the input end of the second phase inverter is connected to the output end of the reset output circuit, and the output end of the second phase inverter is connected to the grid electrode of the ninth MOS tube and the grid electrode of the tenth MOS tube.

In some embodiments, the power-on-reset threshold voltage satisfies the following relationship:

wherein, V_por+A power-on reset threshold voltage; v_gs4Is a reference voltage; (I)₃+I₆) The second current signal is generated by the current mirror branch circuit when the first driving voltage rises to the reference voltage in the power-on process; r₂Is the resistance between the first end of the voltage division circuit and the voltage division node; r₃Is the resistance between the voltage dividing node and the second terminal of the voltage dividing circuit.

In some embodiments, the power down reset threshold voltage satisfies the following relationship:

wherein, V_por-Reset for power-downA threshold voltage; v_gs4Is a reference voltage; i is₃A second current signal generated by the current mirror branch when the first driving voltage is reduced to the reference voltage in the power-down process; r₂Is the resistance between the first end of the voltage division circuit and the voltage division node; r₃Is the resistance between the voltage dividing node and the second end of the voltage dividing circuit; r₄Is the resistance value of the fourth impedance unit.

In some embodiments, the power-on reset circuit further includes a resistance adjusting circuit, and the resistance adjusting circuit is connected to the voltage dividing circuit and the fourth impedance unit and configured to adjust the resistances of the voltage dividing circuit and the fourth impedance unit so as to make the temperature coefficient of the reset threshold voltage zero.

An embodiment of the present application further provides an integrated circuit, including any one of the power-on reset circuits described above.

The embodiment of the application also provides electronic equipment which comprises an equipment main body and the integrated circuit arranged in the equipment main body.

The power-on reset circuit comprises a current generation circuit, a threshold control circuit and a reset output circuit, wherein the current generation circuit is used for generating a reference voltage and a first current signal with a positive temperature coefficient; the threshold control circuit is connected with the current generation circuit and used for generating a first driving voltage with a negative temperature coefficient according to the power supply voltage and determining a reset threshold voltage according to the first current signal and the first driving voltage; the reset output circuit is connected to the threshold control circuit for outputting a reset signal when the power supply voltage crosses a reset threshold voltage, wherein the power supply voltage is equal to the reset threshold voltage when the first driving voltage is equal to the reference voltage. The reset threshold voltage in the embodiment of the application is determined by the first current signal and the first driving voltage, so that the reset threshold voltage simultaneously comprises a positive temperature coefficient and a negative temperature coefficient, and the reset threshold voltage can have a zero temperature coefficient by properly taking values of the positive temperature coefficient and the negative temperature coefficient, so that the reset threshold voltage is not influenced by conditions such as process, power supply and temperature.

These and other aspects of the present application will be more readily apparent from the following description of the embodiments.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 shows a block diagram of a power-on reset circuit according to an embodiment of the present disclosure.

Fig. 2 shows a block diagram of a threshold control circuit provided in an embodiment of the present application.

Fig. 3 shows a schematic circuit structure diagram of a power-on reset circuit provided in an embodiment of the present application.

Fig. 4 shows a schematic circuit structure diagram of another power-on reset circuit provided in an embodiment of the present application.

Fig. 5 is a circuit configuration diagram of the power-on reset circuit in fig. 4 in a power-on condition.

Fig. 6 is a schematic diagram showing a circuit configuration of the power-on reset circuit in fig. 4 in a power-off situation.

Fig. 7 shows a schematic structural diagram of an integrated circuit provided in an embodiment of the present application.

Fig. 8 shows a schematic structural diagram of an electronic device provided in an embodiment of the present application.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.

In order to make the technical solutions of the present application better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

A conventional power-on reset circuit uses a bandgap reference circuit to generate a reference voltage, and then compares the reference voltage with a power supply voltage. When the power supply voltage is greater than the reference voltage, the comparator outputs a high level to generate a reset release signal.

However, the accuracy of the power-on-power-off reset threshold is one of the important indicators of the power-on reset threshold. The power-on and power-off reset threshold value has a certain variation range under the influence of application conditions such as process variation, power supply and temperature. Taking a power-on reset release threshold as an example, if the threshold is too large, the lowest available voltage of the chip is limited; if the threshold is too small, the reset may be released in advance when the power supply voltage does not reach the normal working voltage of the chip, which may cause system abnormality. Therefore, how to make the power-on reset threshold not affected by the conditions of the process, the power supply, the temperature, and the like is a hot spot studied by those skilled in the art.

Through long-term research and testing of the inventor, the embodiment of the application provides a power-on reset circuit, an integrated circuit and an electronic device, wherein the power-on reset circuit comprises a current generation circuit, a threshold control circuit and a reset output circuit, wherein the current generation circuit is used for generating a reference voltage and a first current signal with a positive temperature coefficient; the threshold control circuit is connected with the current generation circuit and used for generating a first driving voltage with a negative temperature coefficient according to the power supply voltage and determining a reset threshold voltage according to the first current signal and the first driving voltage; the reset output circuit is connected to the threshold control circuit for outputting a reset signal when the power supply voltage crosses a reset threshold voltage, wherein the power supply voltage is equal to the reset threshold voltage when the first driving voltage is equal to the reference voltage. The reset threshold voltage in the embodiment of the application is determined by the first current signal and the first driving voltage, so that the reset threshold voltage simultaneously comprises a positive temperature coefficient and a negative temperature coefficient, and the reset threshold voltage can have a zero temperature coefficient by properly taking values of the positive temperature coefficient and the negative temperature coefficient, so that the reset threshold voltage is not influenced by conditions such as process, power supply and temperature.

As shown in fig. 1, the present embodiment provides a power-on reset circuit 100, where the power-on reset circuit 100 includes a current generation circuit 110, a threshold control circuit 120, and a reset output circuit 130. The threshold control circuit 120 is connected to the current generating circuit 110, and the reset output circuit 130 is connected to the threshold control circuit 120. The current generating circuit 110 is used for generating a reference voltage and a first current signal, wherein the first current signal has a positive temperature coefficient. The threshold control circuit 120 is used for generating a first driving voltage according to the power voltage, wherein the first driving voltage has a negative temperature coefficient. The threshold control circuit 120 may determine the reset threshold voltage according to the first current signal and the first driving voltage. The reset output circuit 130 is configured to output a reset signal when the power supply voltage crosses a reset threshold voltage, wherein the power supply voltage is equal to the reset threshold voltage when the first driving voltage is equal to the reference voltage.

The reset threshold voltage may include a power-on reset threshold voltage and a power-down reset threshold voltage. The power-on reset threshold voltage is a critical point at which the power supply voltage gradually increases at power-on, so that the reset output circuit 130 outputs a reset signal; the power-down reset threshold signal is a critical point at which the power supply voltage gradually decreases when power is down, so that the reset output circuit 130 outputs a reset signal. The time when the power supply voltage crosses the reset threshold voltage refers to the time when the power supply voltage rises from zero to the reset threshold voltage in the process of gradually rising the power supply voltage; and a time when the power supply voltage drops to the reset threshold voltage in a process in which the power supply voltage gradually drops. Further, when the power supply voltage rises to the power-on reset threshold voltage, the reset output circuit 130 outputs a power-on reset signal; when the power supply voltage drops to the power-down reset threshold voltage, the reset output circuit 130 outputs a power-down reset signal. In this embodiment, the power-down reset threshold voltage may be equal to the power-up reset threshold voltage; or may be less than the power-on reset threshold voltage to avoid repeated generation of reset signals when the power supply voltage fluctuates.

In this embodiment, the threshold control circuit 120 generates the first driving voltage according to the power supply voltage, and thus the first driving voltage can follow the rise or fall of the power supply voltage. When the first driving voltage rises to be equal to the reference voltage along with the power supply voltage, the power supply voltage rises to be equal to the power-on reset threshold voltage, and when the power supply voltage continues to rise to be greater than the reset threshold voltage, the reset circuit outputs a power-on reset signal. When the first driving voltage is reduced to be equal to the reference voltage along with the power supply voltage, the power supply voltage is reduced to be equal to the power-down reset threshold voltage, and when the power supply voltage continues to be reduced to be smaller than the reset threshold voltage, the reset circuit outputs a power-down reset signal.

Further, the first current signal has a positive temperature coefficient, and the first driving voltage has a negative temperature coefficient. The threshold control circuit 120 determines a reset threshold voltage according to the first current signal and the first driving voltage such that the reset threshold voltage has a positive temperature coefficient of the first current signal and a negative temperature coefficient of the first driving voltage. In this embodiment, the positive temperature coefficient of the first current signal and the negative temperature coefficient of the first driving voltage are both adjustable, so that the reset threshold voltage has a zero temperature coefficient by appropriately taking the positive temperature coefficient and the negative temperature coefficient, and thus, in the process of rising and falling of the power supply voltage, the power-on reset threshold voltage and the power-off reset threshold voltage are both not affected by conditions such as a process, a power supply, a temperature and the like, so that the power-on reset threshold voltage and the power-off reset threshold voltage have good temperature deviation resistance.

Specifically, as shown in fig. 2, the threshold control circuit 120 includes a current mirror branch 121 and a voltage divider circuit 122. The current mirror branch 121 is configured to generate a second current signal mirrored from the first current signal according to a reference voltage. The first terminal of the voltage divider circuit 122 is used for connecting a power supply, the second terminal is grounded, a voltage dividing node is arranged between the first terminal and the second terminal of the voltage divider circuit 122, the voltage dividing node is connected to the current mirror branch 121, and the voltage divider circuit 122 is used for generating a first driving voltage at the voltage dividing node according to a power supply voltage and determining a reset threshold signal according to a second current signal and the first driving voltage.

The reset output circuit 130 is connected to the voltage dividing node and the current generating circuit 110, and is configured to generate a third current signal according to the first driving voltage, and output a reset signal according to the third current signal when the power supply voltage crosses the reset threshold voltage; when the first driving voltage is equal to the reference voltage, the third current signal is the same as the first current signal, and when the third current signal is the same as the first current signal, the power voltage is equal to the reset threshold voltage.

In this embodiment, the third current signal generated by the reset output circuit 130 is related to the first driving voltage, that is, the change of the first driving voltage may cause the change of the third current signal. The first driving voltage rises or falls along with the power voltage, and when the first driving voltage rises or falls to be equal to the reference voltage, the third current signal generated by the reset output circuit 130 is the same as the first current signal of the current generation circuit 110, so that the reset output circuit 130 reaches an equilibrium state. As the first driving voltage continues to rise or fall, when the first driving voltage rises or falls to cross the reference voltage, the third current signal generated by the reset output circuit 130 changes accordingly, so that the balanced state of the reset output circuit 130 is broken, when the reset output circuit 130 is changed from the balanced state to the unbalanced state, the reset output circuit 130 outputs the reset signal, and the power supply voltage at this time is the reset threshold voltage.

In other words, when the power voltage rises or falls to be equal to the reset threshold voltage, the first driving voltage correspondingly rises or falls to be equal to the reference voltage, so that the third current signal is the same as the first current signal, and the reset output circuit 130 reaches a balanced state, and when the first driving voltage continues to rise to be greater than the reset threshold voltage or continues to fall to be less than the reset threshold voltage, the reset output circuit 130 is changed from the balanced state to an unbalanced state, and at this time, the reset output circuit 130 outputs the reset signal.

In this embodiment, the current voltage level of the power voltage can be expressed by the second current signal and the first driving voltage. Since the second current signal is the mirror current of the first current signal, the second current signal has the same positive temperature coefficient as the first current signal, and since the power supply voltage is the reset threshold voltage when the first driving voltage is equal to the reference voltage, the reset threshold voltage can be expressed by the second current signal and the first driving voltage, so that the reset threshold voltage has both the positive temperature coefficient and the negative temperature coefficient. Therefore, by properly taking the positive temperature coefficient and the negative temperature coefficient, the reset threshold voltage can have a zero temperature coefficient, and the power-on reset threshold voltage and the power-off reset threshold voltage can be free from the influence of conditions such as process, power supply, temperature and the like in the rising and falling processes of the power supply voltage, so that the power-on reset threshold voltage and the power-off reset threshold voltage have good temperature deviation resistance.

Fig. 3 is a schematic circuit diagram of a power-on reset circuit 100 according to an embodiment. In some embodiments, as shown in fig. 3, the current generating circuit 110 includes a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, and a first impedance unit. In this embodiment, the first MOS transistor Q1 and the third MOS transistor Q3 are P-MOS transistors, the second MOS transistor Q2 and the fourth MOS transistor Q4 are N-MOS transistors, the first impedance unit is the first resistor R1, the source of the first MOS transistor Q1 is connected to the power supply VDD, the drain is connected to the first end of the first resistor R1, and the gate is connected to the gate of the third MOS transistor Q3. The gate of the second MOS transistor Q2 is connected to the first end of the first impedance unit (i.e., the first resistor R1), the drain is connected to the second end of the first impedance unit (i.e., the first resistor R1), and the source is grounded. The source of the third MOS transistor Q3 is connected to the power supply, the drain is connected to the drain of the fourth MOS transistor Q4, and the drain and the gate of the third MOS transistor Q3 are connected to each other. The source of the fourth MOS transistor Q4 is grounded, and the gate is connected to the second end of the first resistor R1. The first MOS transistor Q1 and the third MOS transistor Q3 form a PMOS current mirror, and the second MOS transistor Q2 and the fourth MOS transistor Q4 work in a subthreshold region. The second end of the first impedance unit is used for outputting a reference voltage, and the drain electrode of the third MOS tube and the drain electrode of the fourth MOS tube are used for outputting a first current signal.

The current mirror branch 121 includes a fifth MOS transistor Q5, and the fifth MOS transistor Q5 is used for mirroring the fourth MOS transistor Q4, so that the channel type of the fifth MOS transistor Q5 is the same as that of the fourth MOS transistor Q4. In this embodiment, taking the fifth MOS transistor Q5 as an N-MOS transistor as an example, the drain of the fifth MOS transistor Q5 is connected to the voltage dividing node, the source is grounded, and the gate is connected to the gate of the fourth MOS transistor Q4, so as to mirror the fourth MOS transistor Q4. The voltage divider circuit 122 includes a second impedance unit and a third impedance unit. In this embodiment, taking the second impedance unit as the second resistor R2 and the third impedance unit as the third resistor R3 as an example, the first end of the second resistor R2 is connected to the power VDD and the second end is connected to the first end of the third resistor R3. The second terminal of the third resistor R3 is connected to ground. The connection node of the second resistor R2 and the third resistor R1 is a voltage dividing node.

The reset output circuit 130 includes a sixth MOS transistor Q6, a seventh MOS transistor Q7, and a first inverter INV 0. In this embodiment, the sixth MOS transistor Q6 is a P-MOS transistor, and the seventh MOS transistor Q7 is an N-MOS transistor. The sixth MOS transistor Q6 has a source connected to the power supply VDD, a drain connected to the drain of the seventh MOS transistor Q7, and a gate connected to the drain of the third MOS transistor Q3. The source of the seventh MOS transistor Q7 is grounded, and the gate is connected between the second resistor R2 and the third resistor R3. The input end of the first inverter INV0 is connected between the drain of the sixth MOS transistor Q6 and the drain of the seventh MOS transistor Q7, and the output end is used for outputting a reset signal. The first inverter may be an inverter with a schmitt trigger function, and is configured to output the reset signal when the trigger condition is reached (i.e., the moment when the branch formed by the sixth MOS transistor Q6 and the seventh MOS transistor Q7 changes from the balanced state to the unbalanced state), and maintain the state unchanged (not output the reset signal) at other times.

It should be understood that the channel type of each MOS transistor described above in this embodiment is merely an example, and in practical applications, the channel type of each MOS transistor may be changed as needed. Similarly, in the present embodiment, each of the impedance units is exemplified by 1 resistor, but in practical applications, each of the impedance units may be formed by connecting a plurality of resistive elements in series and parallel.

In this embodiment, the principle of the power-on reset circuit 100 is as follows:

in this embodiment, an external start circuit provides a bias voltage to the first MOS transistor Q1 and the third MOS transistor Q3 to turn on the first MOS transistor Q1 and the third MOS transistor Q3, so as to generate a first current I flowing through the first MOS transistor Q1, the first resistor Q1, and the second MOS transistor Q3₁And a second current I flowing through the third MOS transistor Q3 and the fourth MOS transistor Q4₂。

As can be seen from FIG. 3, the first current I₁Can be calculated from the voltage across the first resistor R1 and the resistance of the first resistor R1. The following formula is thus obtained:

wherein, V_gs2Is the gate-source voltage, V, of the second MOS transistor Q2_gs4Is the gate-source voltage, R, of the fourth MOS transistor Q4₁Is the resistance of the first resistor R1.

In this embodiment, the third MOS transistor Q3 and the fourth MOS transistor Q4 operate in the sub-threshold region. The voltage and current formula of the MOS tube working in the subthreshold region is as follows:

wherein, I_dsIs the drain-source current; i is_d0Is a characteristic current; w is the gate width; l is the gate length; v_gsIs the gate-source voltage; n is a process factor; v_TIs a thermal voltage, which has a positive temperature coefficient.

From equation (2), the gate-source voltage equation of the MOS transistor operating in the sub-threshold region is:

in the embodiment, the ratio of the width-to-length ratio of the first MOS transistor Q1 to the width-to-length ratio of the third MOS transistor Q3 is p: 1; the ratio of the width-to-length ratio of the second MOS transistor Q2 to the width-to-length ratio of the fourth MOS transistor Q4 is 1: m, wherein p and m are positive integers.

Combining the formula (1) and the formula (3), the first current I can be obtained₁Comprises the following steps:

since the first MOS transistor Q1 and the third MOS transistor Q3 form a current mirror with the ratio of p:1, the second current I can be obtained₂Comprises the following steps:

in this embodiment, the second current I₂The first current signal has a positive temperature coefficient; v_gs4The aforementioned reference voltage.

The current generating circuit 110 generates a stable second current I through the first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3, the fourth MOS transistor Q4 and the first resistor R1₂The second current I₂Is not affected by the power supply voltage VDD. It is worth noting that the current I generated by the third MOS transistor Q3_P3And the current I generated by the fourth MOS transistor Q4_N4A second current I in the branch where the third MOS transistor Q3 and the fourth MOS transistor Q4 are located₂At this time, the third MOS transistor Q3 and the fourth MOS transistor Q4 are in a balanced state.

Further, in the present embodiment, the ratio of the width-to-length ratio of the fifth MOS transistor Q5 to the width-to-length ratio of the fourth MOS transistor Q4 is a:1, where a is a positive integer. Due to the grid-source voltage V of the fifth MOS transistor Q5_gs5And the gate-source voltage V of the fourth MOS transistor Q4_gs4Is at the same potential, so the third current I flowing through the branch of the fifth MOS transistor Q5₃Is in response to a second current I₂Proportional mirror current, i.e. third current I₃Comprises the following steps:

it should be noted that the aforementioned second current signal includes a third current I₃It is known from equation (6) that it has a positive temperature coefficient.

Further, as shown in fig. 3, the power voltage VDD is the sum of the voltages of the second resistor R2 and the third resistor R3, and the voltage of the third resistor R3 is the gate-source voltage V of the seventh MOS transistor Q7_gs7. Thus, the supply voltage VDD can be expressed as:

VDD＝I_R2R₂+V_gs7 (7)

wherein, I_R2Is the current flowing through the second resistor R2, also called the fourth current; v_gs7Is the gate-source voltage of the seventh MOS transistor Q7, which has a negative temperature coefficient. Note that, the gate-source voltage V of the seventh MOS transistor Q7_gs7I.e. the first driving voltage.

Further, a fourth current I flowing through a second resistor R2_R2Is the sum of the current mirror branch 121 and the current flowing through the third resistor R3. In this embodiment, only one current mirror branch 121 is shown, that is, the current of the current mirror branch 121 is the third current I flowing through the fifth MOS transistor Q5₃. In some embodiments, the current mirror branch 121 may also include a plurality of branches, where the current of the current mirror branch 121 is the sum of the currents flowing through the plurality of branches. In this embodiment, the fourth current I_R2Comprises the following steps:

wherein R is₃Is the resistance of the third resistor R3.

Accordingly, by combining formula (6), formula (7), and formula (8), it is possible to obtain:

in this embodiment, the width-to-length ratio of the sixth MOS transistor Q6 is equal to the width-to-length ratio of the third MOS transistor Q3, and the width-to-length ratios of the seventh MOS transistor Q7 and the fourth MOS transistor Q4 are equal. That is, the sixth MOS transistor Q6 and the seventh MOS transistor Q7 can be regarded as a duplicate of the branch formed by the third MOS transistor Q3 and the fourth MOS transistor Q4. Since the sixth MOS transistor Q6 and the seventh MOS transistor Q7 are connected in series, the current I flowing through the sixth MOS transistor Q6_P6And the current I flowing through the seventh MOS transistor Q7_N7Similarly, the current flowing through the sixth MOS transistor Q6 and the seventh MOS transistor Q7 is referred to as the fifth current I in the present embodiment₅。

It is obvious that the gate-source voltage V of the seventh MOS transistor Q7_Vgs7May vary with variations in the supply voltage VDD. Since the gate of the sixth MOS transistor Q6 and the gate of the third MOS transistor Q3 are maintained at the same potential, but the gate of the seventh MOS transistor Q7 and the gate of the fourth MOS transistor Q4 are not maintained at the same potential, but vary with the change of the power supply voltage VDD, the replica branch formed by the sixth MOS transistor Q6 and the seventh MOS transistor Q7 is not always in a balanced state.

When the gate-source voltage V of the seventh MOS transistor Q7_Vgs7And the gate-source voltage V of the fourth MOS transistor Q4_gs4When the currents are not equal, the sixth MOS transistor Q6 and the seventh MOS transistor Q7 are not balanced, and the fifth current I flowing through the branch of the sixth MOS transistor Q6 and the branch of the seventh MOS transistor Q7 is the fifth current I₅And a second current I flowing through the branch of the third MOS transistor Q3 and the fourth MOS transistor Q4₂Are not identical.

When the gate-source voltage V of the seventh MOS transistor Q7_Vgs7The grid-source voltage V is changed to the grid-source voltage V of the fourth MOS tube Q4 along with the power voltage VDD_gs4When the currents are equal, the sixth MOS transistor Q6 and the seventh MOS transistor Q7 reach a balance, and at this time, the fifth current I flowing through the branch of the sixth MOS transistor Q6 and the seventh MOS transistor Q7₅And a second current I flowing through the branch of the third MOS transistor Q3 and the fourth MOS transistor Q4₂The same is true.

When the gate-source voltage V of the seventh MOS transistor Q7_Vgs7Continuously changes to the gate-source voltage V of the fourth MOS transistor Q4 along with the power supply voltage VDD_gs4When the voltage is not equal to the voltage, the balance between the sixth MOS transistor Q6 and the seventh MOS transistor Q7 is broken, and the sixth MOS transistor Q6 and the seventh MOS transistor Q7 are connected to each otherA signal output to the first inverter INV0 at a connection node between Q7 is inverted, so that the first inverter INV0 outputs a reset signal.

In this embodiment, the reset signal includes a power-on reset signal and a power-off reset signal. The power-on reset signal is a reset signal output by the first inverter INV0 in the rising process of the power supply voltage VDD, and the power-down reset signal is a reset signal output by the first inverter INV0 in the falling process of the power supply voltage VDD.

Taking the power-on reset signal as an example, the power supply voltage VDD starts to rise from zero when power is turned on. In the initial stage, the gate-source voltage V of the seventh MOS transistor Q7_gs7At this time, a high level signal is output to the first inverter INV0 at the connection node between the sixth MOS transistor Q6 and the seventh MOS transistor Q7, and the signal output by the first inverter INV0 is a low level.

Gate source voltage V of seventh MOS transistor Q7_gs7When the gate-source voltage V of the seventh MOS transistor Q7 rises along with the gradual rise of the power supply voltage VDD_gs7Rising to the gate-source voltage V of the fourth MOS transistor Q4_gs4When the current I is equal, the branch where the sixth MOS transistor Q6 and the seventh MOS transistor Q7 are located is balanced, and the branch where the third MOS transistor Q3 and the fourth MOS transistor Q4 are located can be copied normally, so that the fifth current I flowing through the branch where the sixth MOS transistor Q6 and the seventh MOS transistor Q7 are located at this time₅And a second current I flowing through a branch of the third MOS transistor Q3 and the fourth MOS transistor Q4₂The same is true.

As the power supply voltage VDD continues to rise, when the gate-source voltage V of the seventh MOS transistor Q7_gs7Rises to a gate-source voltage V larger than that of the fourth MOS transistor Q4_gs4Meanwhile, the balance between the sixth MOS transistor Q6 and the seventh MOS transistor Q7 is broken, a signal output to the first inverter INV0 at a connection node between the sixth MOS transistor Q6 and the seventh MOS transistor Q7 is inverted, a low-level signal is output to the first inverter INV0, and at this time, the first inverter INV0 outputs a high-level power-on reset signal.

Note that the gate-source voltage V of the fourth MOS transistor Q4_gs4I.e. the reference voltage generated by the current generating circuit 110; the second current I flows through the branch of the third MOS transistor Q3 and the fourth MOS transistor Q4₂I.e. currentGenerating a first current signal generated by the circuit 110; gate source voltage V of seventh MOS transistor Q7_gs7I.e., the first driving voltage generated by the threshold control circuit 120; a fifth current I flowing through the branch of the sixth MOS transistor Q6 and the seventh MOS transistor Q7₅I.e., the third current signal generated by the reset output circuit 130.

Therefore, when the first driving voltage is equal to the reference voltage, the power-on reset circuit 100 makes the third current signal generated by the reset output circuit 130 be the same as the first current signal generated by the current generating circuit 110, so that the reset output circuit 130 reaches the same equilibrium state as the current generating circuit 110. When the first driving voltage crosses the reference voltage, the equilibrium state of the reset output circuit 130 is broken, thereby outputting a reset signal.

When the first driving voltage is equal to the reference voltage, the power voltage VDD is the reset threshold voltage V_por. When the power supply voltage VDD crosses the reset threshold voltage V_porAccordingly, the first driving voltage also crosses the reference voltage, so that the reset output circuit 130 outputs the reset signal.

Further, according to equation (9), the expression of the power supply voltage VDD is:

due to reset threshold voltage V_porIs a first driving voltage V_gs7＝V_gs4Voltage of time, thus, reset threshold voltage V_porThe expression of (a) is:

wherein, (10)

Thus, the reset threshold voltage comprises V with a positive temperature coefficient_TAnd V having a negative temperature coefficient_gs4. By properly taking the values of the first resistor R1, the second resistor R2 and the third resistor R3, the positive temperature coefficient and the negative temperature coefficient can be mutually offset, so that the reset threshold is electrically connectedPressure V_porHas a zero temperature coefficient.

Further, the reset threshold voltage comprises a power-on reset threshold voltage V_por+And a power down reset threshold voltage V_por-. Power-on reset threshold voltage V in this embodiment_por+Threshold voltage V capable of resetting with power failure_por-The same is true. In some embodiments, the power down reset threshold voltage V_por-Can be less than power-on reset threshold voltage V_por+. Therefore, the power-on reset circuit 100 in the present embodiment can cause the power-on reset threshold voltage V to be_por+And a power down reset threshold voltage V_por-All have zero temperature coefficient, thereby leading the power supply voltage VDD to be at the power-on reset threshold voltage V in the power-on process and the power-off process_por+And a power down reset threshold voltage V_por-Can not be influenced by conditions such as process, power supply, temperature and the like, so that the power-on reset threshold voltage V_por+And a power down reset threshold voltage V_por-Has good temperature deviation resistance.

Optionally, one or more of the first impedance unit, the second impedance unit, and the third impedance unit may be a resistor network. The power-on reset circuit 100 may further include a resistance value adjusting circuit (not shown), which may be connected to the voltage dividing circuit 122 and configured to adjust a resistance value of the voltage dividing circuit, so that a temperature coefficient of the reset threshold voltage is zero. Specifically, the resistance value adjusting circuit may be connected to the first impedance unit, the second impedance unit, and the third impedance unit, so as to adjust the resistance values of the first impedance unit, the second impedance unit, and the third impedance unit, so that the reset threshold voltage has a zero temperature coefficient.

Alternatively, the resistances of the first impedance unit, the second impedance unit, and the third impedance unit may be preset, so that the reset threshold voltage has a zero temperature coefficient.

In this embodiment, the positive temperature coefficient and the negative temperature coefficient of the reset threshold voltage are both individually adjustable, so that the power-on reset circuit 100 can meet a specific reset threshold requirement, and the power consumption and the circuit area of the power-on reset circuit 100 can be balanced conveniently, thereby achieving a low power consumption effect. Meanwhile, the power-on reset circuit 100 reduces the influence of process variation on the reset threshold voltage by branch circuit duplication, thereby utilizing matching between devices.

The power-on reset circuit provided by the application comprises a current generation circuit, a threshold control circuit and a reset output circuit, wherein the current generation circuit is used for generating a reference voltage and a first current signal with a positive temperature coefficient; the threshold control circuit is connected with the current generation circuit and used for generating a first driving voltage with a negative temperature coefficient according to the power supply voltage and determining a reset threshold voltage according to the first current signal and the first driving voltage; the reset output circuit is connected to the threshold control circuit for outputting a reset signal when the power supply voltage crosses a reset threshold voltage, wherein the power supply voltage is equal to the reset threshold voltage when the first driving voltage is equal to the reference voltage. The reset threshold voltage in the embodiment of the application is determined by the first current signal and the first driving voltage, so that the reset threshold voltage simultaneously comprises a positive temperature coefficient and a negative temperature coefficient, and the reset threshold voltage can have a zero temperature coefficient by properly taking values of the positive temperature coefficient and the negative temperature coefficient, so that the reset threshold voltage is not influenced by conditions such as process, power supply and temperature.

In other embodiments, in order to improve the stability of the power-on reset circuit and prevent the power-on reset circuit from outputting a reset signal due to power supply fluctuation during a non-power-on/power-off process, a hysteresis circuit may be further disposed in the threshold control circuit, and the hysteresis circuit is respectively connected to the voltage divider circuit and the current mirror branch circuit, and is configured to determine a difference between a power-on reset threshold voltage and a power-off reset threshold voltage.

As an example, refer to fig. 4, where fig. 4 shows another power-on reset circuit 200 provided in the embodiment of the present application. The power-on-reset circuit 200 also includes a current generation circuit 210, a threshold control circuit 220, and a reset output circuit 230. And the threshold control circuit 220 also includes a current mirror branch 221 and a voltage divider circuit 222.

The power-on reset circuit 200 differs from the power-on reset circuit 100 in that: the current mirror branch 221 further includes an eighth MOS transistor Q8, wherein, taking the eighth MOS transistor Q8 as an N-MOS transistor as an example, the drain of the eighth MOS transistor Q8 is connected to the voltage dividing node, and the source is grounded, and the gate is used for receiving the reference voltage, that is, the gate of the eighth MOS transistor Q8 may be connected to the second end of the first impedance unit to receive the reference voltage. That is, the eighth MOS transistor Q8 is another mirror branch of the current mirror branch 221 except for the fifth MOS transistor Q5.

Further, the power-on reset circuit 200 further includes a hysteresis circuit 240. The hysteresis circuit 240 is connected to the voltage divider circuit 222 and the current mirror branch 221, respectively, and is configured to determine a voltage difference between a power-on reset threshold voltage and a power-off reset threshold voltage.

Specifically, the hysteresis circuit 240 includes a second inverter INV1, a fourth impedance unit, a ninth MOS transistor Q9, and a tenth MOS transistor Q10; in an example where the fourth impedance unit is a fourth resistor R4, the ninth MOS transistor Q9 and the tenth MOS transistor Q10 are N-MOS transistors, the drain of the ninth MOS transistor Q9 is connected to the source of the eighth MOS transistor Q8 and the source of the ninth MOS transistor Q9 is grounded. The fourth resistor R4 is connected between the voltage divider circuit and ground, i.e., the first end of the fourth resistor R4 is connected to the second end of the third resistor R3, and the second end of the fourth resistor R4 is grounded. The drain and source of the tenth MOS transistor Q10 are connected in parallel to two ends of the fourth impedance unit (i.e., the fourth resistor R4). An input end of the second inverter INV1 is connected to the output end of the first inverter INV0, an output end of the second inverter INV1 is connected to the gate of the ninth MOS transistor Q9 and the gate of the tenth MOS transistor Q10.

In this embodiment, the principles of the power-on reset circuit 200 and the power-on reset circuit 100 generating the reset signal are substantially the same, and are not described again. Unlike the power-on reset circuit 100, the hysteresis circuit 240 in the power-on reset circuit 200 causes the power-on reset threshold voltage and the power-off reset threshold voltage of the power-on reset circuit 200 to generate a fixed difference, which is a hysteresis voltage, so as to prevent the reset signal from jittering due to the fluctuation of the power voltage.

Will be described below with respect to the power-on reset threshold voltage V_por+And a power-down reset threshold voltage V_por-Are separately described.

Power-on reset thresholdValue voltage V_por+：

At power up, the supply voltage VDD rises from zero. In the initial stage, the gate-source voltage V of the seventh MOS transistor Q7_gs7At this time, a high level signal is output to the first inverter INV0 at the connection node between the sixth MOS transistor Q6 and the seventh MOS transistor Q7, a low level signal is output to the second inverter INV1 by the first inverter INV0, and a high level signal is output to the ninth MOS transistor Q9 and the tenth MOS transistor Q10 by the second inverter, so that the ninth MOS transistor Q9 and the tenth MOS transistor Q10 are turned on, and the fourth resistor R4 is short-circuited.

At this time, the structure of the power-on reset circuit 200 may be as shown in fig. 5. In fig. 5, the power voltage VDD is the sum of the voltages of the second resistor R2 and the third resistor R3, and the voltage of the third resistor R3 is the gate-source voltage V of the seventh MOS transistor Q7_gs7Thus, the supply voltage VDD can be expressed as:

VDD＝I_R2R₂+V_gs7 (11)

wherein, I_R2Is the fourth current flowing through the second resistor R2; v_gs7The gate-source voltage of the seventh MOS transistor Q7, i.e. the first driving voltage, has a negative temperature coefficient. Note that, the gate-source voltage V of the seventh MOS transistor Q7_gs7I.e. the first driving voltage.

Further, a fourth current I flowing through a second resistor R2_R2Is the sum of the current mirror branch 221 and the current flowing through the third resistor R3. In the power-on process of the present embodiment, the current mirror branch 221 includes a branch where the fifth MOS transistor Q5 is located and a branch where the eighth MOS transistor Q8 is located, and the second current generated by the current mirror branch 221 is the third current I flowing through the branch where the fifth MOS transistor Q5 is located₃And the sixth current I flowing through the branch of the eighth MOS transistor Q8₆And (4) summing. Therefore, the fourth current I_R2Comprises the following steps:

wherein, I₃The third current flows through the branch of the fifth MOS transistor Q5; i is₆Is the sixth current flowing through the branch of the eighth MOS transistor Q8.

By substituting formula (12) for formula (11), it is possible to obtain:

since when the first driving voltage is equal to the reference voltage, i.e. V_gs7＝V_gs4Then, the power supply voltage VDD is the power-on reset threshold voltage V_por+Therefore, the power-on reset threshold voltage V_por+The expression of (a) is:

wherein, V_gs4Is a reference voltage; (I)₃+I₆) The second current signal is generated by the current mirror branch circuit when the first driving voltage rises to the reference voltage in the power-on process; r₂The resistance value between the first end of the voltage division circuit and the voltage division node is the resistance value of the second resistor; r₃Is the resistance between the voltage dividing node and the second end of the voltage dividing circuit, i.e. the resistance of the third resistor.

In this embodiment, the ratio of the width-to-length ratio of the eighth MOS transistor Q8 to the width-to-length ratio of the fourth MOS transistor Q4 is b:1, where b is a positive integer. Due to the gate-source voltage V of the eighth MOS transistor Q8_gs8And the gate-source voltage V of the fourth MOS transistor Q4_gs4The same potential, therefore, the sixth current I flowing through the branch of the eighth MOS transistor Q8₆Is in response to a second current I₂Proportional mirror current, i.e. sixth current I₆Comprises the following steps:

as can be seen from the foregoing, the third current I flowing through the branch of the fifth MOS transistor Q5₃Comprises the following steps:

therefore, combining equations (14), (15) and (16), the power-on reset threshold voltage V can be obtained_por+Comprises the following steps:

as can be seen from equation (17), the power-on reset threshold voltage V_por+Comprising V having a positive temperature coefficient_TAnd V having a negative temperature coefficient_gs. By properly taking the values of the first resistor R1, the second resistor R2 and the third resistor R3, the positive temperature coefficient and the negative temperature coefficient can be mutually offset, so that the power-on reset threshold voltage V is enabled to be_por+Has a zero temperature coefficient.

Lower reset threshold voltage V_por+：

At power down, the supply voltage VDD drops from a higher value. Gate source voltage V of seventh MOS transistor Q7_gs7The gate-source voltage V of the seventh MOS transistor Q7 is reduced gradually along with the reduction of VDD in the initial stage_gs7At this time, a low level signal is output to the first inverter INV0 at a connection node between the sixth MOS transistor Q6 and the seventh MOS transistor Q7, a high level signal is output to the second inverter INV1 by the first inverter INV0, and a low level signal is output to the ninth MOS transistor Q9 and the tenth MOS transistor Q10 by the second inverter, so that the ninth MOS transistor Q9 and the tenth MOS transistor Q10 are turned off, thereby disconnecting the branch where the eighth MOS transistor Q8 is located.

At this time, the structure of the power-on reset circuit 200 may be as shown in fig. 6. In fig. 6, the power voltage VDD is the sum of the voltages of the second resistor R2, the third resistor R3 and the fourth resistor R4, and the sum of the voltages of the third resistor R3 and the fourth resistor R4 is the gate-source voltage V of the seventh MOS transistor Q7_gs7Thus, the supply voltage VDD can be expressed as:

VDD＝I_R2R₂+V_gs7 (18)

wherein, I_R2Is the fourth current flowing through the second resistor R2; v_gs7Is the gate of a seventh MOS transistor Q7The source voltage, i.e. the first drive voltage, has a negative temperature coefficient.

Further, a fourth current I flowing through a second resistor R2_R2Is the sum of the current mirror branch 221 and the current flowing through the third resistor R3. In the power-down process of this embodiment, the current mirror branch 221 includes only one branch where the fifth MOS transistor Q5 is located, and at this time, the current of the current mirror branch 221 is the third current I flowing through the branch where the fifth MOS transistor Q5 is located₃. Therefore, the fourth current I_R2Comprises the following steps:

wherein R is₄Is the resistance of the fourth resistor R4.

By substituting formula (19) for formula (18), it is possible to obtain:

since when the first driving voltage is equal to the reference voltage, i.e. V_gs7＝V_gs4Then, the power supply voltage VDD is the power-down reset threshold voltage V_por-Thus, the power-down reset threshold voltage V_por-The expression of (a) is:

V_por-resetting the threshold voltage for power down; v_gs4Is a reference voltage; i is₃A second current signal generated by the current mirror branch when the first driving voltage is reduced to the reference voltage in the power-down process; r₂The resistance value between the first end of the voltage division circuit and the voltage division node is the resistance value of the second resistor; r₃The resistance value between the voltage dividing node and the second end of the voltage dividing circuit, namely the resistance value of the third resistor; r₄Is the resistance value of the fourth impedance unit.

From the foregoing, the current flowing through the branch of the fifth MOS transistor Q5Third current of the circuit I₃Comprises the following steps:

therefore, combining equations (21) and (22), the power-down reset threshold voltage V can be obtained_por-Comprises the following steps:

as can be seen from equation (23), the power-down reset threshold voltage V_por-Also comprising V having a positive temperature coefficient_TAnd V having a negative temperature coefficient_gs4. By properly taking the values of the first resistor R1, the second resistor R2 and the third resistor R3, the positive temperature coefficient and the negative temperature coefficient can be mutually offset, so that the power-down reset threshold voltage V is enabled to be lower_por-Has a zero temperature coefficient.

Furthermore, combining equation (17) and equation (23), in this embodiment, the hysteresis circuit 240 acts to reset the threshold voltage V due to power-down_por-And a power-on reset threshold voltage V_por+And are inconsistent. When the power is turned off, the mirror image branch in the current mirror image branch 221 is reduced, and the total resistance value of the voltage dividing circuit 222 is increased, so that the current of the voltage dividing circuit 222 is reduced, and further, a difference exists between a power-off reset threshold voltage when the first driving voltage is reduced to be equal to the reference voltage in the power-off process and a power-on reset threshold voltage when the first driving voltage is increased to be equal to the reference voltage in the power-on process, so that the reset signal is prevented from shaking due to the fluctuation of the power supply voltage.

The power-on reset circuit provided by the embodiment comprises a current generation circuit, a threshold control circuit and a reset output circuit, wherein the current generation circuit is used for generating a reference voltage and a first current signal with a positive temperature coefficient; the threshold control circuit is connected with the current generation circuit and used for generating a first driving voltage with a negative temperature coefficient according to the power supply voltage and determining a reset threshold voltage according to the first current signal and the first driving voltage; the reset output circuit is connected to the threshold control circuit for outputting a reset signal when the power supply voltage crosses a reset threshold voltage, wherein the power supply voltage is equal to the reset threshold voltage when the first driving voltage is equal to the reference voltage. The reset threshold voltage in the embodiment of the application is determined by the first current signal and the first driving voltage, so that the reset threshold voltage simultaneously comprises a positive temperature coefficient and a negative temperature coefficient, and the reset threshold voltage can have a zero temperature coefficient by properly taking values of the positive temperature coefficient and the negative temperature coefficient, so that the reset threshold voltage is not influenced by conditions such as process, power supply and temperature.

In this embodiment, optionally, the first impedance unit, the second impedance unit, the third impedance unit, and the fourth impedance unit may all be a resistor network. The power-on reset circuit 200 may further include a resistance value adjusting circuit (not shown), which may be connected to the first impedance unit, the second impedance unit, the third impedance unit, and the fourth impedance unit, so as to adjust the resistance values of the first impedance unit, the second impedance unit, the third impedance unit, and the fourth impedance unit, so that the reset threshold voltage has a zero temperature coefficient.

Optionally, the resistances of the first impedance unit, the second impedance unit, the third impedance unit, and the fourth impedance unit may be preset, so that the reset threshold voltage has a zero temperature coefficient.

As shown in fig. 7, an integrated circuit 300 is further provided in the embodiment of the present application, where the integrated circuit 300 includes the power-on reset circuit described above.

The integrated circuit provided by the embodiment of the application comprises a current generation circuit, a threshold control circuit and a reset output circuit, wherein the current generation circuit is used for generating a reference voltage and a first current signal with a positive temperature coefficient; the threshold control circuit is connected with the current generation circuit and used for generating a first driving voltage with a negative temperature coefficient according to the power supply voltage and determining a reset threshold voltage according to the first current signal and the first driving voltage; the reset output circuit is connected to the threshold control circuit for outputting a reset signal when the power supply voltage crosses a reset threshold voltage, wherein the power supply voltage is equal to the reset threshold voltage when the first driving voltage is equal to the reference voltage. The reset threshold voltage in the embodiment of the application is determined by the first current signal and the first driving voltage, so that the reset threshold voltage simultaneously comprises a positive temperature coefficient and a negative temperature coefficient, and the reset threshold voltage can have a zero temperature coefficient by properly taking values of the positive temperature coefficient and the negative temperature coefficient, so that the reset threshold voltage is not influenced by conditions such as process, power supply and temperature.

As shown in fig. 8, an electronic device 400 is further provided in the embodiment of the present application, where the electronic device 400 includes a device body 410 and the integrated circuit 300 described above. Wherein the integrated circuit 300 is provided within the device body 410.

The electronic equipment provided by the embodiment of the application comprises a current generation circuit, a threshold control circuit and a reset output circuit, wherein the current generation circuit is used for generating a reference voltage and a first current signal with a positive temperature coefficient; the threshold control circuit is connected with the current generation circuit and used for generating a first driving voltage with a negative temperature coefficient according to the power supply voltage and determining a reset threshold voltage according to the first current signal and the first driving voltage; the reset output circuit is connected to the threshold control circuit for outputting a reset signal when the power supply voltage crosses a reset threshold voltage, wherein the power supply voltage is equal to the reset threshold voltage when the first driving voltage is equal to the reference voltage. The reset threshold voltage in the embodiment of the application is determined by the first current signal and the first driving voltage, so that the reset threshold voltage simultaneously comprises a positive temperature coefficient and a negative temperature coefficient, and the reset threshold voltage can have a zero temperature coefficient by properly taking values of the positive temperature coefficient and the negative temperature coefficient, so that the reset threshold voltage is not influenced by conditions such as process, power supply and temperature.

Although the present application has been described with reference to the preferred embodiments, it is to be understood that the present application is not limited to the disclosed embodiments, but rather, the present application is intended to cover various modifications, equivalents and alternatives falling within the spirit and scope of the present application.

Claims

1. A power-on reset circuit is characterized by comprising a current generation circuit, a threshold control circuit and a reset output circuit, wherein the current generation circuit is used for generating a reference voltage and a first current signal with a positive temperature coefficient;

the threshold control circuit is connected with the current generation circuit and used for generating a first driving voltage with a negative temperature coefficient according to a power supply voltage and determining a reset threshold voltage according to the first current signal and the first driving voltage;

the reset output circuit is connected to the threshold control circuit and is configured to output a reset signal when a power supply voltage crosses the reset threshold voltage, wherein the power supply voltage is equal to the reset threshold voltage when the first driving voltage is equal to the reference voltage.

2. The power-on-reset circuit of claim 1, wherein the threshold control circuit comprises:

the current mirror branch circuit is used for generating a second current signal mirrored to the first current signal according to the reference voltage;

the first end of the voltage division circuit is used for being connected with a power supply, the second end of the voltage division circuit is grounded, a voltage division node is arranged between the first end and the second end of the voltage division circuit, the voltage division node is connected to the current mirror branch, the voltage division circuit is used for generating the first driving voltage according to the power supply voltage at the voltage division node, and the voltage division circuit is used for determining the reset threshold signal according to the second current signal and the first driving voltage.

3. The power-on-reset circuit of claim 2, wherein the reset output circuit is connected to the voltage-dividing node and the current generation circuit, and is configured to generate a third current signal according to the first driving voltage and output the reset signal according to the third current signal when the power supply voltage crosses the reset threshold voltage; wherein the third current signal is the same as the first current signal when the first driving voltage is equal to the reference voltage, and the power supply voltage is equal to the reset threshold voltage when the third current signal is the same as the first current signal.

4. The power-on-reset circuit of claim 2, wherein the reset threshold voltage comprises a power-on-reset threshold voltage and a power-down-reset threshold voltage; the threshold control circuit comprises a hysteresis circuit, and the hysteresis circuit is respectively connected with the voltage division circuit and the current mirror branch circuit and is used for determining the difference value between the power-on reset threshold voltage and the power-off reset threshold voltage.

5. The power-on reset circuit according to claim 2, wherein the current generating circuit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a first impedance unit;

the source electrode of the first MOS tube is connected to a power supply, the drain electrode of the first MOS tube is connected to the first end of the first impedance unit, and the grid electrode of the first MOS tube is connected with the grid electrode of the third MOS tube;

the grid electrode of the second MOS tube is connected to the first end of the first impedance unit, the drain electrode of the second MOS tube is connected to the second end of the first impedance unit, and the source electrode of the second MOS tube is grounded;

the source electrode of the third MOS tube is connected with the power supply, the drain electrode of the third MOS tube is connected with the drain electrode of the fourth MOS tube, and the drain electrode of the third MOS tube is connected with the grid electrode;

the source electrode of the fourth MOS tube is grounded, and the grid electrode of the fourth MOS tube is connected to the second end of the first impedance unit;

the second end of the first impedance unit is used for outputting the reference voltage, and the drain of the third MOS transistor and the drain of the fourth MOS transistor are used for outputting the first current signal.

6. The power-on reset circuit according to claim 5, wherein the current mirror branch comprises a fifth MOS transistor, a drain of the fifth MOS transistor is connected to the voltage dividing node, a source of the fifth MOS transistor is grounded, and a gate of the fifth MOS transistor is connected to a gate of the fourth MOS transistor;

the voltage division circuit comprises a second impedance unit and a third impedance unit, wherein the first end of the second impedance unit is connected to the power supply, and the second end of the second impedance unit is connected to the first end of the third impedance unit; the second end of the third impedance unit is grounded; wherein a connection node of the second impedance unit and the third impedance unit is the voltage division node.

7. The power-on reset circuit according to claim 5, wherein the reset output circuit comprises a sixth MOS transistor, a seventh MOS transistor, and a first inverter;

the source electrode of the sixth MOS tube is connected with the power supply, the drain electrode of the sixth MOS tube is connected with the drain electrode of the seventh MOS tube, and the grid electrode of the sixth MOS tube is connected with the drain electrode of the third MOS tube;

the source electrode of the seventh MOS tube is grounded, and the grid electrode of the seventh MOS tube is connected to the voltage division node;

the input end of the first phase inverter is connected between the drain electrode of the sixth MOS tube and the drain electrode of the seventh MOS tube, and the output end of the first phase inverter is used for outputting the reset signal.

8. The power-on reset circuit according to claim 4, wherein the current mirror branch further comprises an eighth MOS transistor, a drain of the eighth MOS transistor is connected to the voltage dividing node, a source of the eighth MOS transistor is grounded, and a gate of the eighth MOS transistor is configured to receive the reference voltage; the hysteresis circuit comprises a second inverter, a fourth impedance unit, a ninth MOS (metal oxide semiconductor) transistor and a tenth MOS transistor;

the drain electrode of the ninth MOS tube is connected to the source electrode of the eighth MOS tube, and the source electrode of the ninth MOS tube is grounded;

the fourth impedance unit is connected between the second end of the voltage division circuit and the ground;

the drain electrode and the source electrode of the tenth MOS tube are connected with two ends of the fourth impedance unit in parallel;

the input end of the second phase inverter is connected to the output end of the reset output circuit, and the output end of the second phase inverter is connected to the grid electrode of the ninth MOS transistor and the grid electrode of the tenth MOS transistor.

9. The power-on-reset circuit of claim 8, wherein the power-on-reset threshold voltage satisfies the following relationship:

wherein, V_por+Is the power-on reset threshold voltage; v_gs4Is the reference voltage; (I)₃+I₆) The second current signal is generated by the current mirror branch circuit when the first driving voltage rises to the reference voltage in the power-on process; r₂Is the resistance between the first end of the voltage division circuit and the voltage division node; r₃Is a resistance value between the voltage dividing node and the second end of the voltage dividing circuit.

10. The power-on-reset circuit of claim 8, wherein the power-down-reset threshold voltage satisfies the following relationship:

wherein, V_por-Resetting the threshold voltage for said power down; v_gs4Is the reference voltage; i is₃The second current signal is generated by the current mirror branch circuit when the first driving voltage is reduced to the reference voltage in the power-down process; r₂Is the voltage division circuitAnd a resistance value between the first terminal of (a) and the voltage dividing node; r₃Is a resistance value between the voltage dividing node and a second end of the voltage dividing circuit; r₄Is the resistance value of the fourth impedance unit.

11. The power-on reset circuit according to claim 9 or 10, further comprising a resistance value adjusting circuit, connected to the voltage dividing circuit and the fourth impedance unit, for adjusting the resistance values of the voltage dividing circuit and the fourth impedance unit so as to make the temperature coefficient of the reset threshold voltage zero.

12. An integrated circuit comprising a power-on-reset circuit as claimed in any one of claims 1 to 11.

13. An electronic device comprising a device body and an integrated circuit as claimed in claim 12 provided in the device body.