CN112837720A

CN112837720A - High-density tri-state content addressing memory and addressing method thereof

Info

Publication number: CN112837720A
Application number: CN202110087357.8A
Authority: CN
Inventors: 杨建国; 蒋海军; 薛晓勇; 刘琦
Original assignee: Zhejiang Lab
Current assignee: Zhejiang Lab
Priority date: 2021-01-22
Filing date: 2021-01-22
Publication date: 2021-05-25

Abstract

The invention discloses a high-density tri-state content addressing memory and an addressing method thereof, wherein the memory comprises: the memory cell comprises a first storage resistor and a second storage resistor, wherein the first end of the first storage resistor is connected with the search line, the second end of the first storage resistor is connected with the match line, the first end of the second storage resistor is connected with the complementary search line, and the second end of the second storage resistor is connected with the match line. The high-density tri-state content addressing memory and the addressing method thereof have the characteristics of high storage density and high reliability.

Description

High-density tri-state content addressing memory and addressing method thereof

Technical Field

The invention relates to the technical field of embedded control, in particular to a high-density tri-state content addressable memory and an implementation method thereof.

Background

In the era of big data and cloud computing, along with the popularization of various intelligent devices, a large amount of data is generated along with the popularization of various intelligent devices, and meanwhile, the data also needs to be transmitted through a network. In order to improve data transmission efficiency and security, it becomes necessary to screen data in routers. The traditional screening method based on software mainly depends on multiple access and comparison operations between a Central Processing Unit (CPU) and a main memory, and both time cost and power consumption cost are high. And TCAM (ternary content addressable memory) is a solution on a hardware level, and can implement fast and efficient search and matching by parallel comparison, thereby better solving the problems existing in the conventional software implementation method.

The fast lookup and matching of TCAMs often comes at the cost of increased chip area and increased power consumption. The traditional TCAM design is based on an SRAM (static random access memory), a single TCAM unit usually needs 12-16 transistors, the storage density of the TCAM is difficult to be improved due to overlarge unit area, and meanwhile, the parasitic capacitance is large due to the large area, so that the dynamic (active) power consumption is large. In addition, the conventional TCAM inherits the volatile characteristic of the SRAM, and the static (standby) mode cannot cut off the power supply, otherwise the stored information is lost, which also results in larger static power consumption.

In view of the problems of the conventional TCAM, a research focus is currently on how to implement a high-density TCAM based on a new high-density memory. Internationally, the famous research institutions include IBM, NEC, Tohoku university, TSMC, taiwan qinghua university, china, etc., and flag ship conference ISSCC (international solid state integrated circuit conference) and Symposium on VLSI Circuits (VLSI, large scale integrated circuit seminar) in the field of integrated Circuits report related results of high-density TCAM from 2011 to 2016 for six consecutive years. Firstly, the number of transistors in the TCAM unit is reduced to 2-6, the area of the TCAM unit is greatly reduced, and secondly, the high-density characteristic of the novel memory enables the TCAM to be completely powered off in a dormant state without worrying about information loss, thereby being beneficial to reducing static power consumption. However, the existing high-density TCAM schemes still have some problems, mainly manifested in that:

the small storage window between the "0" and "1" signals for MRAM-based high density TCAMs results in a small storage window between the "0" and "1" signals in the corresponding high density TCAM because MRAM itself has a small Roff/Ron (Ron is low resistance, Roff is high resistance) and is susceptible to fluctuations. For the high-density TCAM based on the RRAM, the voltage division between the RRAM storage resistor and the transistor is mainly relied to obtain '0' or '1', the fluctuation of the transistor and the RRAM storage resistor is large when the size is small, and the fluctuation rule is inconsistent, so that the storage window between the obtained '0' and '1' signals is easily influenced by the fluctuation and becomes poor.

The area of the TCAM cell is still large, and the existing minimum high density TCAM cell area still has 50F2 (F is the feature size at each process generation). Because the existing high-density TCAM still needs the assistance of a transistor to realize the TCAM function, and the transistor needs to be manufactured on a CMOS front-stage process, on one hand, the area of the TCAM is enlarged, on the other hand, the possibility of three-dimensional (3D) integration of the TCAM is limited, and the 3D integration capability of the RRAM is not favorably exerted.

Disclosure of Invention

In order to solve the defects of the prior art, realize the purposes of reducing the volume of a storage unit, increasing the storage density of a memory, improving the reliability of the memory and enabling the 3D integration of the memory to be possible, the invention adopts the following technical scheme:

a high density tri-state content addressable memory, comprising: the memory comprises a drive circuit, a memory cell and an amplifier, and further comprises a search line, a match line and a complementary search line, wherein the drive circuit comprises a match line drive circuit and a search line drive circuit, the amplifier is a match line sense amplifier, the memory cell comprises a first storage resistor and a second storage resistor, the match line drive circuit is connected with the match line, the search line drive circuit is respectively connected with the search line and the complementary search line, the match line sense amplifier is connected with the match line, a first end of the first storage resistor is connected with the search line, a second end of the first storage resistor is connected with the match line, a first end of the second storage resistor is connected with the complementary search line, and a second end of the second storage resistor is connected with the match line;

the matched line driving circuit is used for generating a set voltage;

the search line driving circuit is used for generating a reset voltage;

and the matchline sensitive amplifier is used for amplifying and outputting the matched signal.

Furthermore, the memory unit further comprises a first current limiting device and a second current limiting device, the first end of the first memory resistor is connected with the search line after being connected with the first current limiting device in series, and the first end of the second memory resistor is connected with the complementary search line after being connected with the second current limiting device in series, so that the reliability of the memory unit can be improved by the current limiting device.

Furthermore, the memory cells are arranged in an array, the memory cells on the same row share a match line, and the memory cells on the same column share a search line and a complementary search line.

Further, the matchline sense amplifier is a comparison amplifier, compares the output voltage of the matchline with a reference voltage, and amplifies and outputs the comparison result.

A high-density tri-state content addressing method comprises the following steps:

step S1, obtaining a search signal, where the search signal includes "1", "0", and "X";

step S2, determining whether the search signal is "1";

step S3, if the search signal is "1", charging the match line and the search line to a precharge voltage, the complementary search line remaining at a low level;

step S4, if the search signal is not "1", determining whether the search signal is "0";

step S5, if the search signal is "0", the match line and the complementary search line are precharged to a high level, and the search line is kept at a low level;

step S6, if the search signal is not "0", determining whether the search signal is "X";

step S7, if the search signal is "X", the search line, the match line and the complementary search line are precharged to a high level;

step S8, acquiring a voltage of the match line output terminal;

step S9, determining whether the output voltage is greater than the reference voltage,

the value of the reference voltage is a set value between a high level VH2 and a low level VL2, the high level VH2 is a level value of a match line after discharging in a discharging stage when the search signal is matched with the storage information of the memory cell, and the low level VL2 is a level value of a match line after discharging in a discharging stage when the search signal is not matched with the storage information of the memory cell;

step S10, if the output voltage is larger than the reference voltage, outputting '1', representing that the storage information of the memory unit is matched with the search information;

in step S11, if the output voltage is less than or equal to the reference voltage, "0" is output, which represents that the memory cell storage information does not match the search information.

Further, after the step S3, the memory enters a discharging phase, when searching for "1", if the logic value stored in the memory cell is "1", the memory cell only has a high-impedance discharging path to the match line, and in case that other memory cells in the same row also match, the match line only discharges to a high level VH1, and since the storage resistance between the match line and the search line is in a low-impedance state, the search line also discharges to a high level along with the match line; if the logic value stored in the memory cell is '0', the memory cell has a low-resistance discharge path to the match line, the match line is discharged to a low level VL1, the storage resistance between the search line and the match line is in a high-resistance state, and the search line is discharged to a high level;

after the step S5, the memory enters a discharge comparison stage, when searching for "0", if the logic value stored in the memory cell is "0", the memory cell only has a high-impedance discharge path to the match line, and when other memory cells in the same row are also matched, the match line only discharges to a high level VH1, and since the memory resistance between the match line and the complementary search line is a low-impedance state, the complementary search line also discharges to a high level along with the match line; if the logic value stored by the memory cell is '1', the memory cell has a low-resistance discharge path to the matched line, the matched line is discharged to a lower level VL1, the storage resistance between the complementary search line and the matched line is in a high-resistance state, and the complementary search line is discharged to a high level;

after step 7, the memory enters a discharge compare phase, and the memory cell will not discharge the match line regardless of whether the memory cell has a stored logic value of "1" or "0".

Further, the precharge voltage in step S3 is the power supply voltage.

Further, in step S3, when a current limiting device is included in the memory, the precharge voltage is a sum of a power supply voltage and a turn-on voltage of the current limiting device.

Furthermore, the writing operation of the memory adopts a mode of applying excitation and is divided into two steps, wherein the first step is as follows: writing a first storage resistor, and writing a second storage resistor: and writing the second storage resistor again, wherein the excitation application mode adopts a VPP/2 or VPP/3 algorithm, VSET is a set voltage, VRESET is a reset voltage, VT is a conduction voltage of a current-limiting device, VSET and VRESET voltages are generated by a matched line driving circuit and a search line driving circuit, and the VPP/2 algorithm application excitation mode of the writing operation is as follows:

when the write data is '0', the search line of the first step is '0', the complementary search line is VSET/2, and the match line is VSET; the search line of the second step is VRSET/2, the complementary search line is VRSET, the matched line is '0';

when the write data is '1', the search line of the first step is VSET/2, the complementary search line is '0', and the match line is VSET; the search line of the second step is VRSET, the complementary search line is VRSET/2, and the matched line is '0';

when the write data is "0", the search line of the second step is VRSET, the complementary search line is VRSET, and the match line is "0";

the VPP/3 algorithm for write operations applies the stimulus as follows:

when the write data is "0", the search line of the first step is "0", the complementary search line is 2/3 × VSET, and the match line is VSET; the search line of the second step is 2/3 × VSET, the complementary search line is VRSET, and the match line is "0";

when the write data is "1", the search line of the first step is 2/3 × VSET, the complementary search line is "0", and the match line is VSET; the search line of the second step is VRSET, the complementary search line is 2/3 × VSET, and the match line is "0";

when the write data is "0", the search line of the second step is VRSET, the complementary search line is VRSET, and the match line is "0".

Further, when a current limiting device is included in the memory, the VPP/2 algorithm for write operation applies the excitation pattern as follows:

when the write data is '0', the search line of the first step is '0', the complementary search line is (VSET + VT)/2, and the match line is VSET + VT; the search line of the second step is (VSET + VT)/2, the complementary search line is VRSET + VT, and the matched line is '0';

when the write data is "1", the search line of the first step is (VSET + VT)/2, the complementary search line is "0", and the match line is VSET + VT; the search line of the second step is VRSET + VT, the complementary search line is (VRSET + VT)/2, and the matched line is '0';

when the write data is "0", the search line of the second step is VRSET + VT, the complementary search line is VRSET + VT, and the match line is "0";

the VPP/3 algorithm for write operations applies the stimulus as follows:

when the write data is "0", the search line of the first step is "0", the complementary search line is 2/3 × VSET + VT, and the match line is VSET + VT; the search line of the second step is 2/3 × (VSET + VT), the complementary search line is VRSET + VT, and the match line is "0";

when the write data is "1", the search line of the first step is 2/3 × the complementary search line is "0", and the match line is VSET + VT; the search line of the second step is VRSET + VT, the complementary search line is 2/3 (VRSET + VT), and the match line is "0";

when the write data is "0", the search line of the second step is VRSET + VT, the complementary search line is VRSET + VT, and the match line is "0".

The invention has the advantages and beneficial effects that:

the high-density tri-state content addressable memory provided by the invention adopts a device which can be integrated in the CMOS back-end process to construct a memory unit, and does not contain a transistor which needs to be integrated in the CMOS front-end process, so that on one hand, the volume of the memory unit is reduced, the memory density of the memory is increased, and on the other hand, the 3D integration of the memory becomes possible. In addition, when the information is searched, the matchline driving circuit is adopted to charge the matchline to the precharge voltage, and the search line driving circuit is adopted to reset the voltages of the search line and the complementary search line, namely the signals of '0' and '1' are not obtained through the divided voltage of the transistor, so that the problem of small storage window between the signals of '0' and '1' caused by the divided voltage of the transistor is avoided, and the reliability of the memory is improved.

Drawings

FIG. 1 is a schematic diagram of a high-density ternary content addressable memory according to a first embodiment of the present invention.

FIG. 2 is a schematic structural diagram of a memory cell of a high-density ternary content addressable memory according to a first embodiment of the present invention.

FIG. 3 is a schematic structural diagram of a memory cell of a high-density ternary content addressable memory according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a second embodiment of the present invention.

FIG. 5 is a flow chart of the addressing method of the high-density tri-state content addressable memory according to the present invention.

FIG. 6 is a schematic diagram of the charging and discharging operations of the high-density ternary content addressable memory according to the first embodiment of the present invention.

Detailed Description

The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.

The first embodiment is as follows:

as shown in fig. 1, the high-density tri-state content addressable memory includes: search lines 107 and 109, match lines 102 and 103, complementary search lines 106 and 108, a match line driving circuit 110, a search line driving circuit 101, a plurality of match line sense amplifiers 104 and 105, and a plurality of memory cells 111, wherein the memory cells are arranged in an array, the memory cells on the same row share a match line, the memory cells on different rows do not share a match line, the memory cells on the same column share a search line and a complementary search line, the memory cells on different columns do not share the same search line, and the memory cells on different columns do not share the same complementary search line; the matchline sense amplifier is connected with matchlines in a one-to-one correspondence manner, the output end of the matchline is connected with the input end of the matchline sense amplifier, and the matchline sense amplifier is used for comparing the output voltage of the matchline with a reference voltage Vref1 and amplifying and outputting the comparison result; the match line driving circuit 110 is connected to the match line, and the match line driving circuit 110 is configured to generate a set voltage; the search line driving circuit 101 is connected to the search line and the complementary search line, respectively, and the search line driving circuit 101 is configured to generate a reset voltage.

As shown in fig. 2, the memory cell includes a first storage resistor 201 and a second storage resistor 202, a first end 203 of the first storage resistor 201 is connected to the

search lines

107 and 109, a second end 204 of the first storage resistor 201 is connected to the

match lines

102 and 103, a first end 205 of the second storage resistor 202 is connected to the

complementary search lines

106 and 108, and a second end 206 of the second storage resistor 202 is connected to the

match lines

102 and 103.

Example two:

as shown in fig. 3, in the memory cell of the high-density tri-state content addressable memory, the first end 203 of the first memory resistor 201 is connected in series with the first current limiting device 301 and then connected to the

search lines

107 and 109, the first end 205 of the second memory resistor 202 is connected in series with the second current limiting device 302 and then connected to the

complementary search lines

106 and 108, the second end 204 of the first memory resistor 201 is connected to the

match lines

102 and 103, and the second end 206 of the second memory resistor 202 is connected to the

match lines

102 and 103, so that the current limiting devices can improve the reliability of the memory cell.

As shown in fig. 4, the memory cell 401 of the high-density tri-state content addressable memory is a memory cell with a current-limiting device, and other elements and connection relationships are the same as those of the high-density tri-state content addressable memory in the first embodiment, and includes

search lines

107 and 109,

match lines

102 and 103,

complementary search lines

106 and 108, a match line driving circuit 110, a search line driving circuit 101, a plurality of match

line sense amplifiers

104 and 105, and a plurality of memory cells 401.

The high-density tri-state content addressing memory provided by the invention is constructed by devices such as a resistance change type memory RRAM and the like which can be integrated in a back-end process, and devices such as transistors and the like manufactured in the front-end of a complementary metal oxide semiconductor CMOS (complementary metal oxide semiconductor) process are not used, so that the volume of a storage unit is reduced, the storage density of the memory is increased, meanwhile, the high-density tri-state content addressing memory provided by the invention does not use the traditional transistor voltage division mode to obtain the storage windows of '1' and '0', the problems of large fluctuation and instability of the windows of '1' and '0' are avoided, and the reliability of information storage is enhanced.

As shown in fig. 5, the high-density tri-state content addressing method includes the following steps:

step 501: acquiring a search signal, wherein the search signal comprises '1', '0' and 'X', '1', '0' and 'X' which are logic values;

step 502: judging whether the search signal is '1';

step 503: if the search signal is "1", the matchline driver circuit charges the matchline to a precharge voltage, the search line driver circuit charges the search line to a precharge voltage, the complementary search line remains low, the precharge voltage is generally the supply voltage for memory cells without current limiting devices in embodiment one, and the precharge voltage is generally the sum of the supply voltage and the turn-on voltage of the current limiting devices for memory cells with current limiting devices in embodiment two. After that, the memory enters into a discharge phase, as shown in fig. 6, in case of searching for "1", if the logic value stored in the memory cell is "1", the memory cell only has a high-impedance discharge path to the match line, and in case of matching with other memory cells in the same row, the match line ML only discharges to a higher level VH1, and since the memory resistance between the match line ML and the search line SL is a low-impedance state, the search line SL also discharges to a higher level with the match line ML, as shown by a solid line 607 in fig. 6; if the memory cell stores a logic value of "0", the memory cell will have a low resistance discharge path to the match line ML, and the match line ML will discharge to a lower level VL1, as shown by the dashed line 608 in fig. 6, the storage resistance between the search line SL and the match line ML is in a high resistance state, and the search line SL will discharge to a higher level;

step 504: if the search signal is not "1", judging whether the search signal is "0";

step 505: if the search signal is "0", the match line and the complementary search line are precharged to a high level, the search line is kept at a low level, and then a discharge comparison stage is entered, as shown in fig. 6, when "0" is searched, if the logic value stored by the memory cell is "0", the memory cell has only a high-impedance discharge path to the match line ML, and in the case that other memory cells in the same row also have a match, the match line ML is discharged to a higher level VH1, as shown by a solid line 604 in fig. 6, since the storage resistance between the match line ML and the complementary search line SLB is in a low-impedance state, the complementary search line SLB is also discharged to a higher level along with the match line ML; if the logic value stored in the memory cell is "1", the memory cell will have a low-resistance discharge path to the match line ML, and the match line ML will discharge to a lower level VL1, as shown by the dashed line 605 in fig. 6, the storage resistance between the complementary search line SLB and the match line ML is in a high-resistance state, and the complementary search line SLB will discharge to a higher level; in fig. 6, 601 is a waveform of a search line SL precharge and discharge signal, 602 is a waveform of a complementary search line SLB precharge and discharge signal, and 603 is a waveform of a discharge signal at the time of match line ML precharge and search match.

Step 506: if the search signal is not '0', judging whether the search signal is 'X';

step 507: if the search signal is "X", the search line, match line, and complement search line are precharged to a high level, and then a discharge compare phase is entered, as shown at 609 in FIG. 6, in which the memory cell does not discharge the match line regardless of whether the memory cell stores a logic value of "1" or "0";

step 508: acquiring the voltage of the output end of the matched line;

step 509: determining whether the output voltage is greater than a reference voltage, the value of the reference voltage being a set value, the set value being a level value intermediate between the high level VH2 and the low level VL2, as indicated by a dashed line 610 in fig. 6;

step 510: if the output voltage is greater than the reference voltage, which is the voltage represented by 610 in fig. 6, the sense amplifier connected to the match line outputs "1", which represents that the storage information of the memory cell matches the search information, and the sense amplifier is a comparison amplifier;

step 511: if the output voltage is less than or equal to the reference voltage, the sense amplifier connected to the match line outputs a "0" indicating that the memory cell stored information does not match the search information.

The pre-charge voltage is generally a power supply voltage in the first embodiment of the present invention, and is the sum of the power supply voltage and the turn-on voltage of the current limiting device in the second embodiment.

The truth table stored for the memory cell in the first embodiment is shown in table one, and the truth table stored for the memory cell in the second embodiment is shown in table two.

Watch 1

Storing data	First memory resistance (RRAM resistance)	Second memory resistance (RRAM resistance)
			0	HRS (high resistance state)	LRS (Low resistance state)
1	LRS (Low resistance state)	HRS (high resistance state)
			X	HRS (high resistance state)	HRS (high resistance state)

Watch two

The write operation of the high-density three-state content addressing memory provided by the invention adopts an excitation applying mode, which comprises two steps, namely writing the left resistor firstly and then writing the right resistor, wherein the excitation applying mode is similar to the write operation of a crossbar (cross array) architecture, and a VPP/2 or VPP/3 algorithm can be adopted. VSET is set voltage; VRESET is the reset voltage and VT is the turn-on voltage of the current limiting device. The VSET and VRESET voltages are generated by the ML driver circuit 110 and the SL driver circuit 101, the VPP/2 algorithm applied activation manner for the write operation of the high-density ternary content addressable memory provided in the first embodiment is shown in table three, the VPP/3 algorithm applied activation manner is shown in table four, the VPP/2 algorithm applied activation manner for the write operation of the high-density ternary content addressable memory provided in the second embodiment is shown in table five, and the VPP/3 algorithm applied activation manner is shown in table six.

Watch III

Watch four

Watch five

Watch six

When the high-density tri-state content addressing memory provided by the invention is used for writing operation and searching information, the driving circuit is used for setting, resetting and charging, the traditional transistor voltage division mode is not used for obtaining the storage windows of 1 and 0, the problems of large fluctuation and instability of the windows of 1 and 0 are avoided, and the reliability of information storage is enhanced.

The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high density tri-state content addressable memory, comprising: the memory cell comprises a drive circuit, a memory cell (111) and an amplifier, and is characterized by further comprising a search line, a match line and a complementary search line, wherein the drive circuit comprises a match line drive circuit (110) and a search line drive circuit (101), the amplifier is a match line sense amplifier, the memory cell (111) comprises a first storage resistor (201) and a second storage resistor (202), the match line drive circuit is connected with the match line, the search line drive circuit is respectively connected with the search line and the complementary search line, the match line sense amplifier is connected with the match line, a first end (203) of the first storage resistor (201) is connected with the search line, a second end (204) of the first storage resistor (201) is connected with the match line, and a first end (205) of the second storage resistor (202) is connected with the complementary search line, a second terminal (206) of the second storage resistor (202) is coupled to the match line;

the matched line driving circuit is used for generating a set voltage;

the search line driving circuit is used for generating a reset voltage;

2. A high density ternary content addressable memory according to claim 1, wherein said memory cell further comprises a first current limiting device (301) and a second current limiting device (302), a first terminal (203) of said first memory resistor (201) being connected in series with said first current limiting device (301) and then connected to said search line, a first terminal (205) of said second memory resistor (202) being connected in series with said second current limiting device (302) and then connected to said complementary search line.

3. A high density ternary content addressable memory according to claim 1 or 2, characterized in that said memory cells (111) are arranged in an array, said memory cells (111) in a same row share a match line, said memory cells (111) in a same column share a search line and complementary search line.

4. A high density tri-state content addressable memory according to claim 1 or 2, wherein the matchline sense amplifier is a comparison amplifier, compares the output voltage of the matchline with a reference voltage, and amplifies the comparison result to output.

5. A method for high density tri-state content addressing, comprising the steps of:

step S2, determining whether the search signal is "1";

step S8, acquiring a voltage of the match line output terminal;

step S10, if the output voltage is greater than the reference voltage, "1" is output;

in step S11, if the output voltage is equal to or less than the reference voltage, "0" is output.

6. The method according to claim 5, wherein after step S3, the memory enters a discharge phase, and when searching for "1", if the logic value stored by the memory cell is "1", the memory cell has only a high-impedance discharge path to the match line, and in case of match of other memory cells in the same row, the match line is discharged to a high level VH1, and the search line is discharged to a high level with the match line due to the low-impedance state of the memory resistance between the match line and the search line; if the logic value stored in the memory cell is '0', the memory cell has a low-resistance discharge path to the match line, the match line is discharged to a low level VL1, the storage resistance between the search line and the match line is in a high-resistance state, and the search line is discharged to a high level;

7. The method of claim 5, wherein the precharge voltage in step S3 is a power supply voltage.

8. The method according to claim 5, wherein in step S3, when a current-limiting device is included in the memory, the pre-charge voltage is the sum of the power supply voltage and the turn-on voltage of the current-limiting device.

9. The method of claim 5, wherein the writing operation of the memory is performed by applying a stimulus, and the method comprises two steps, the first step: writing a first storage resistor, and writing a second storage resistor: and then writing the second storage resistor, wherein the excitation application mode adopts a VPP/2 or VPP/3 algorithm, VSET is a set voltage, VRESET is a reset voltage, VT is a conduction voltage of a current-limiting device, VSET and VRESET voltages are generated by a matchline driving circuit (110) and a search line driving circuit (101), and the VPP/2 algorithm application excitation mode of the write operation is as follows:

the VPP/3 algorithm for write operations applies the stimulus as follows:

10. The method of claim 9, wherein the VPP/2 algorithm of the write operation activates the following when the memory contains a current limiting device:

the VPP/3 algorithm for write operations applies the stimulus as follows: