CN112821793A - Mixed MMC submodule capacitor voltage bidirectional equalization topology - Google Patents
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Abstract
The invention provides a bidirectional balanced hybrid MMC topological structure based on a diode clamping circuit, which consists of n/2 half-bridge sub-modules, n/2 full-bridge sub-modules and n-1 additional series devices. The present invention is illustrated with a five-level hybrid MMC topology as an example. It consists of two half-bridge modules, two full-bridge modules and three additional units. Wherein the additional units connected between the HBSM are the same as the additional units connected between the HBSM and the FBSM. Each cell comprises two parallel branches. Branch 1 comprises only one diode, branch 2 is a diode connected in reverse series with a switch (an IGBT and a reverse parallel diode), and an inductor is connected to a common branch of branch 1 and branch 2. The additional units connected between the FBSMs, branch 1 and branch 2, are identical in structure and are each composed of a series diode, an inductor and a switch (IGBT and anti-parallel diode). Compared with the traditional software voltage balance method, the topology has two main advantages, firstly, a control frame is simplified, a voltage balance control link is omitted, and control resources are saved; secondly, the number of voltage sensors is reduced, the complexity of a control system is reduced, and the communication pressure is reduced. In addition, compared with other hardware voltage balancing circuits, the topology not only can realize bidirectional balancing, but also reduces the quantity of inductors in the circuit and effectively reduces the hardware cost.
Description
Technical Field
The invention belongs to the technical field of power electronic flexible direct current transmission, and relates to a capacitor voltage bidirectional balancing topological structure based on a hybrid MMC submodule, wherein bidirectional balancing control of capacitor voltage is realized only by a simple hardware circuit.
Background
With the development of medium and high voltage frequency converters, a series of harsh requirements are put forward on high-power frequency converters. The Modular Multilevel Converter (MMC) has the advantages of modularization, expandability, high fault-tolerant capability and the like. MMC is therefore considered to be the most attractive topology among HVDC, VSC, APF, STATCOM, energy storage systems.
However, the reliable operation of MMC based HVDC is seriously threatened by the capacitive voltage imbalance. The capacitor voltage imbalance is caused by non-ideal driving pulses of the sub-modules (SMs) during pre-charge and normal operation phases of the system control. In the uncontrolled pre-charging stage of the system, the difference of parasitic parameters of the power electronic device is closely related to the static voltage unbalance of the capacitor. In particular, the difference in energy losses that the system derives from the capacitors of the SM is a major factor in causing the static voltage imbalance of the capacitors. Capacitance-voltage balancing has become one of the major technical challenges of MMCs.
The current balance control of the capacitor voltage comprises balance of interphase direct current capacitor voltage, balance of capacitor voltage between bridge arms and balance of capacitor voltage between modules in the bridge arms. The main stream of the balancing method can be divided into three categories, by injecting additional control components to the modulation wave of each submodule, voltage sequencing and pulse switching, and balancing by hardware. For the first category, the control of the voltage for each sub-module is better than for the conventional balanced control method. However, these methods introduce a feedforward of the capacitor voltage in the modulation, which reduces the voltage utilization rate of the modulation wave; for the second category, although the software balancing method has flexibility and wide application, signal delay due to the number of voltage sensors, additional computational burden, and sampling and transmission is still a disadvantage of the software balancing method; to reduce the number of voltage sensors and reduce the impact of control delays, hardware balancing approaches are becoming increasingly popular. Therefore, the topology of implementing the equalization control by the external equalization control circuit is the most feasible scheme, but the external equalization topology existing at present can only implement unidirectional voltage equalization.
Disclosure of Invention
The invention aims to overcome the technical problems in the prior art, and provides a capacitor voltage bidirectional balancing topological structure based on a hybrid MMC submodule, wherein the proposed topology ensures that voltages at two ends of capacitors of each submodule in the same phase are clamped to be equal to each other through a diode clamping circuit, the balancing process through the diode clamping circuit is bidirectional, and the balancing is realized only through the diode clamping circuit. Compared with the traditional software voltage balance method, the topology has two main advantages, firstly, a control frame is simplified, a voltage balance control link is omitted, and control resources are saved; secondly, the number of voltage sensors is reduced, the complexity of a control system is reduced, and the communication pressure is reduced. In addition, compared with other hardware voltage balancing circuits, the topology not only can realize bidirectional balancing, but also reduces the quantity of inductors in the circuit and effectively reduces the hardware cost.
In order to achieve the purpose, the invention is implemented according to the following technical scheme:
based on two-way balanced topological structure of mixed type MMC submodule piece electric capacity voltage constitutes: the capacitor voltage bidirectional balancing topology adopts a five-level balancing topology and consists of two half-bridge modules, two full-bridge modules and three additional units. Wherein the additional units connected between the HBSM are the same as the additional units connected between the HBSM and the FBSM. Each cell comprises two parallel branches. Branch 1 comprises only one diode, branch 2 is a diode connected in reverse series with a switch (an IGBT and a reverse parallel diode), and an inductor is connected to a common branch of branch 1 and branch 2. The additional units connected between the FBSMs, branch 1 is a series diode and inductor, and branch 2 is an anti-series diode, inductor and switch (IGBT and anti-parallel diode). For switching of these units, switch Sl1Can be composed of corresponding IGBT S2(SM2) PWM signal control, switch Sl2Can be composed of corresponding IGBT S4(SM3) The PWM signal is used for controlling, and an additional switching signal is not needed. The cells connected between FBSMs have identical legs 1 and 2, each consisting of an anti-series diode, an inductor and a switch. An additional switch S is addedl3And Sh3To avoid connecting the two terminals of the capacitor directly through the diode clamp. Sl3And Sh3Drive signal of SM3S in (1)2And SM4S in (1)4And (4) performing NAND. When the switch is switched on, the capacitor voltage of the sub-modules can be freely exchanged, so that the capacitor voltage balance is realized. Meanwhile, the balance precision is improved, the size of the device is reduced, and control resources are saved.
The method comprises the following steps:
it is assumed that all switches in the topology are ideal devices. Achieving bidirectional capacitance voltage equalization includes three cases:
case 3 capacitive voltage balancing procedure between FBSMs. If two consecutive capacitors Uc3And Uc4Voltage of (1) satisfies Uc3>Uc4If U is detected, branch 1 will be activatedc3<Uc4 Branch 2 will be activated.
In the above three cases, although the topological structures are different, the balance analysis principle is the same, so we take case 1 as an example to perform a detailed mathematical analysis.
If U is presentc1>Uc2From KVL law, one can calculate:
in the formula of UeAnd CeRespectively, an equivalent voltage and an equivalent capacitance. Equation set (1) indicates that the circuit is a second order circuit and the solution to the linear differential equation can be expressed as:
wherein U is0Is UeInitial value of (a), gamma1And gamma2Is the characteristic root of equation (2), and is specifically expressed as follows:
the solution to the linear differential equation can be further expressed as:
the results show that UeThe waveform of (A) fluctuates with the sine wave, with a fluctuation period ToscAnd a clamping inductance LeValues are closely related, LeIs closely related to the system performance. That is, if LeThe greater the value of (A), the greater the period of fluctuation ToscThe larger the voltage will be, the worse the voltage balancing effect of the sub-module SM is; on the contrary, if LeThe smaller the value of (A), the fluctuation period ToscThe smaller, the possibility of oscillation and the additional power lossThe consumption may be higher. Therefore, it is necessary to restrict the selection of the inductance.
The voltage U is given according to equation (4)eAnd a clamp current iLThe relationship (2) of (c). Therefore, the switch activation period Δ T should be less than 0.25Tosc. However, in practical applications Δ T is kept less than 0.25ToscIs not practical. Therefore, the average value of Δ T should be expressed as:
where m is the modulation index, λ is the averaging coefficient (0< λ <1), and Tsw is the inverse of the switching frequency.
Therefore, according to the two equations of equation (5) and equation (6), the clamp inductance Le constraint can be expressed as:
in conclusion, by setting appropriate power parameters according to actual requirements, the range of the equivalent inductance of the bidirectional balanced topology can be obtained.
The invention achieves the following beneficial effects:
compared with the prior art, the hybrid MMC topological structure based on the bidirectional diode clamping circuit is disclosed by the invention. The proposed topology ensures that the voltages at both ends of each submodule capacitor in phase are clamped equal to each other by means of a diode clamp circuit, the balancing process by means of the diode clamp circuit is bi-directional and is achieved only by means of the diode clamp circuit. Compared with the traditional software voltage balance method, the topology has two main advantages, firstly, a control frame is simplified, a voltage balance control link is omitted, and control resources are saved; secondly, the number of voltage sensors is reduced, the complexity of a control system is reduced, and the communication pressure is reduced. In addition, compared with other hardware voltage balancing circuits, the topology not only can realize bidirectional balancing, but also reduces the quantity of inductors in the circuit and effectively reduces the hardware cost.
Drawings
FIG. 1 is a diagram of a hybrid MMC bidirectional equalization topology according to a preferred embodiment of the present invention;
FIG. 2 is a circuit diagram of the capacitor voltage balance circuit and the equivalent circuit of case 1 according to the preferred embodiment of the present invention;
FIG. 3 is a circuit diagram of the capacitor voltage balance circuit and the equivalent circuit of case 2 according to the preferred embodiment of the present invention;
FIG. 4 is a circuit diagram of the capacitor voltage balance circuit and the equivalent circuit of case 3 according to the preferred embodiment of the present invention;
FIG. 5 is an equivalent circuit of the negative-acting switch state in the preferred embodiment of the present invention;
FIG. 6 is a graph of voltage versus current for a diode clamp circuit in accordance with a preferred embodiment of the present invention;
FIG. 7 is a schematic diagram of a hybrid MMC bidirectional balanced topology simulation model according to a preferred embodiment of the present invention;
FIG. 8 is a diagram illustrating the simulation results of the hybrid MMC bi-directional balanced topology in the preferred embodiment of the present invention;
FIG. 9 is a graph showing the result of different sub-module capacitor voltage balancing modes in accordance with the preferred embodiment of the present invention;
FIG. 10 is a simulation diagram of clamp inductor current for a hybrid MMC bi-directional balanced topology in accordance with a preferred embodiment of the present invention;
Detailed Description
The invention will be further described with reference to the drawings and specific embodiments, which are illustrative of the invention and are described in the following description, but are not to be construed as limiting the invention.
The technical scheme of the invention provides a hybrid MMC submodule capacitor voltage bidirectional balancing topological structure, as shown in figure 1, a five-level balancing topology is adopted, and the hybrid MMC submodule capacitor voltage bidirectional balancing topological structure is composed of two half-bridge modules, two full-bridge modules and three additional units. Wherein the additional units connected between the HBSM are the same as the additional units connected between the HBSM and the FBSM. Each cell comprises two parallel branches. Branch 1 only comprises a diode, and branch 2 is a diode and a switchReverse series (IGBT and reverse parallel diode) with inductance connected to the common branch of branch 1 and branch 2. The additional units connected between the FBSMs, branch 1 is a series diode and inductor, and branch 2 is an anti-series diode, inductor and switch (IGBT and anti-parallel diode). For switching of these units, switch Sl1Can be composed of corresponding IGBT S2(SM2) Controlled by PWM signals, the switch Sl2 may be controlled by a corresponding IGBT S4(SM3) The PWM signal is used for controlling, and an additional switching signal is not needed. The cells connected between FBSMs have identical legs 1 and 2, each consisting of an anti-series diode, an inductor and a switch. An additional switch S is addedl3And Sh3To avoid connecting the two terminals of the capacitor directly through the diode clamp. Sl3And Sh3Drive signal of SM3S in (1)2And SM4S in (1)4The modulation signal of (2) is generated by performing a nand operation. When the switch is turned on, the capacitor voltage can be freely exchanged, thereby realizing the voltage balance of the capacitor.
The implementation of the above capacitance voltage equalization includes the following three cases:
in the first case, the capacitive voltage balancing process between HBSMs, as shown in FIG. 2. If two consecutive capacitors Uc1And Uc2Voltage of (1) satisfies Uc1>Uc2When branch 1 will be activated, Uc1And Uc2The voltage will be balanced. Equivalent circuits are shown in FIG. 2(a) and FIG. 2(c), respectively, if two capacitors U are connected in seriesc1And Uc2Voltage of (1) satisfies Uc1<Uc2Then branch 2 is activated, Uc1And Uc2And (4) voltage balancing. The equivalent circuits are depicted as fig. 2(b) and fig. 2(d), respectively.
The second case, the capacitive voltage balancing procedure between HBSM and FBSM, is shown in FIG. 3. If two consecutive capacitors Uc2And Uc3Voltage of (1) satisfies Uc2>Uc3When branch 1 will be activated, Uc2And Uc3The voltage will be balanced. Equivalent circuits are shown in FIG. 3(a) and FIG. 3(c), respectively, if two capacitors U are connected in seriesc2And Uc3Voltage of (1) satisfies Uc2<Uc3Then branch 2 is activated, Uc2And Uc3And (4) voltage balancing. The equivalent circuits are depicted as fig. 3(b) and fig. 3(d), respectively.
As shown in fig. 4, the third case, a capacitive voltage balancing process between FBSMs. If two consecutive capacitors Uc3And Uc4Voltage of (1) satisfies Uc3>Uc4When branch 1 will be activated, Uc3And Uc4The voltage will be balanced. Equivalent circuits are shown in FIG. 4(a) and FIG. 4(c), respectively, if two capacitors U are connected in seriesc3And Uc4Voltage of (1) satisfies Uc3<Uc4Then branch 2 is activated, Uc3And Uc4And (4) voltage balancing. The equivalent circuits are depicted as fig. 4(b) and fig. 4(d), respectively.
It should be noted that in case 3, two consecutive FBSMs are in the switching state, which will have a negative effect on the normal operation of the system. As shown in fig. 5, if switch S2(SM3) And S4(SM4) Both in a conducting state, the two terminals of the capacitor are directly connected through the diode clamp circuit. To avoid the above discharge situation, S in fig. 5(a)2(SM3) And S4(SM4) Will be simultaneously Sl3And Sh3The drive signal of (1).
FIG. 6 shows the capacitor voltage Uc1、Uc2Inductance voltage ULAnd the inductor current iLA waveform diagram of (a). U shapeLThe waveform of (A) fluctuates with the sine wave, with a fluctuation period ToscThe value of L of the clamping inductance is closely related, and L is closely related to the system performance. . Therefore, the switch activation period Δ T should be less than 0.25Tosc。
FIG. 7 is a hybrid MMC bidirectional equilibrium topology simulation model built in MATLAB/Simulink. The simulation model specific parameter settings are shown in table 1.
TABLE 1 simulation parameters
FIG. 8 is a simulation result of voltage and current of a hybrid MMC model of the present invention, and FIG. 9 is a simulation result of the present invention using different sub-module capacitor voltage balancing strategies. Fig. 10 is a waveform diagram of a clamp inductor current simulation of the hybrid MMC bi-directional balanced topology of the present invention. As can be seen from fig. 8, 9 and 10, the topology structure proposed by the present invention can operate normally and has a better sub-module capacitance voltage balancing effect.
Claims (5)
1. Hybrid MMC submodule piece capacitance-voltage two-way balanced topological structure, its characterized in that:
the mixed MMC submodule capacitor voltage bidirectional balance topology comprises: the topology structure is composed of n/2 half-bridge sub-modules, n/2 full-bridge sub-modules and n-1 additional series devices. The primary concern here is a five-level hybrid MMC, with a bidirectional diode clamp shown in fig. 2. It consists of two half-bridge modules, two full-bridge modules and three additional units. Wherein the additional units connected between the HBSM are the same as the additional units connected between the HBSM and the FBSM. Each cell comprises two parallel branches. Branch 1 comprises only one diode, branch 2 is a diode connected in reverse series with a switch (an IGBT and a reverse parallel diode), and an inductor is connected to a common branch of branch 1 and branch 2. The additional units connected between the FBSMs, branch 1 and branch 2, are identical in structure and are each composed of a series diode, an inductor and a switch (IGBT and anti-parallel diode).
2. The diode clamp circuit based bi-directional balanced hybrid MMC topology of claim 1, wherein:
each single MMC submodule in the mixed MMC topological structure is marked as SM in sequence1，SM2，···，SMi(ii) a The value of the voltage across each capacitor is marked Uc1，Uc2，···，Uci(ii) a Wherein the number of FBSM on each bridge arm is NfNumber of HBSM is Nh(ii) a IGBT switch in FBSM is marked as S1,S2,S3,S4(ii) a IGBT switch mark S in HBSM1,S2。
3. The hybrid balanced topology of claim 2, wherein:
a five-level equalization topology is adopted, and the five-level equalization topology is composed of two half-bridge modules, two full-bridge modules and three additional units. Wherein the additional units connected between the HBSM are the same as the additional units connected between the HBSM and the FBSM. Each cell comprises two parallel branches. Branch 1 comprises only one diode, branch 2 is a diode connected in reverse series with a switch (an IGBT and a reverse parallel diode), and an inductor is connected to a common branch of branch 1 and branch 2. The additional units connected between the FBSMs, branch 1 is a series diode and inductor, and branch 2 is an anti-series diode, inductor and switch (IGBT and anti-parallel diode). For switching of these units, switch Sl1Can be composed of corresponding IGBT S2(SM2) PWM signal control, switch Sl2Can be composed of corresponding IGBT S4(SM3) The PWM signal is used for controlling, and an additional switching signal is not needed. The cells connected between FBSMs have identical legs 1 and 2, each consisting of an anti-series diode, an inductor and a switch. An additional switch S is addedl3And Sh3To avoid connecting the two terminals of the capacitor directly through the diode clamp. Sl3And Sh3Drive signal of SM3S in (1)2And SM4S in (1)4The modulation signal of (2) is generated by performing a nand operation. When the switch is turned on, the capacitor voltage can be freely exchanged, thereby realizing the voltage balance of the capacitor.
4. The additional bi-directional capacitive voltage equalization unit of claim 3, wherein:
achieving bidirectional capacitance voltage equalization includes three cases:
case 1 capacitive voltage balancing procedure between HBSMs. If two consecutive capacitors Uc1And Uc2Voltage of (1) satisfies Uc1>Uc2In that branch 1 is to be activated, Uc1And Uc2Will equilibrate; if it is continuousTwo capacitors Uc1And Uc2Voltage of (1) satisfies Uc1<Uc2Then branch 2 is activated, Uc1And Uc2Voltage balancing;
case 2 capacitance-voltage balancing procedure between HBSM and FBSM. If two consecutive capacitors Uc2And Uc3Voltage of (1) satisfies Uc2>Uc3In this relationship, leg 1 will be activated, whereas leg 2 will be activated. U shapec2And Uc3Will equilibrate;
case 3 capacitive voltage balancing procedure between FBSMs. If two consecutive capacitors Uc3And Uc4Voltage of (1) satisfies Uc3>Uc4If U is detected, branch 1 will be activatedc3<Uc4Branch 2 will be activated.
5. The bi-directional capacitance-voltage equalization process of claim 4, wherein:
every two branch total units can be represented as:
all units of branch 1:
Uc1≥Uc2≥Uc3≥Uc4 (1)
all units of branch 2:
Uc1≤Uc2≤Uc3≤Uc4 (2)
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