CN112817760A - Multi-core processor and signal processing method thereof - Google Patents
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Abstract
The invention provides a multi-core processor and a signal processing method thereof, wherein the multi-core processor comprises a thread distribution kernel and a plurality of thread execution kernels which are integrated on the same wafer, and the thread distribution kernel is respectively connected with the thread execution kernels; the thread distribution kernel is used for distributing the threads executed by the multi-core processor to the thread execution kernels in a normal state; the thread execution kernel is used for executing the thread distributed by the thread distribution kernel. The invention distributes the thread to the thread execution core in the normal state through the thread distribution core, avoids the abnormal or damaged thread execution core in the thread distribution process, and ensures that the multi-core processor can normally run under the condition of the abnormal core.
Description
Technical Field
The present disclosure relates to the field of multi-core processors, and more particularly, to a multi-core processor and a signal processing method thereof.
Background
The multi-core processor is characterized in that two or more complete computing engines (kernels) are integrated in one processor, the processor can support a plurality of processors on a system bus, and a bus controller provides all bus control signals and command signals.
With the increasing computing power of processors, more and more cores are provided in the processors. However, when the number of cores of the processor is too large, it is difficult to ensure that each core can work normally, and if one or a few cores are abnormal, the whole processor cannot run, which limits the practical application of the multi-core processor.
Disclosure of Invention
The technical problem to be solved by the embodiments of the present invention is to provide a multi-core processor and a signal processing method of the multi-core processor, aiming at the problem that a few cores in the multi-core processor cannot operate and thus the whole processor cannot operate.
In a first aspect, an embodiment of the present invention provides a multi-core processor, where the multi-core processor includes a thread allocation kernel and a plurality of thread execution kernels that are integrated on a same wafer, and the thread allocation kernel is connected to the thread execution kernels respectively; the thread distribution kernel is used for distributing threads executed by the multi-core processor to the thread execution kernel in a normal state; and the thread execution kernel is used for executing the threads distributed by the thread distribution kernel.
The multi-core processor comprises a thread distribution kernel and a multi-core thread execution kernel, the thread is distributed to the thread execution kernel in a normal state through the thread distribution kernel, and the abnormal or damaged thread execution kernel is avoided in the thread distribution process, so that the multi-core processor can normally run under the condition that the abnormal kernel exists in the multi-core processing.
Furthermore, the thread distribution kernel and the thread execution kernel are respectively connected to a system bus, a switch element is connected between the thread execution kernel and the system bus in series, a control end of each switch element is connected with the thread distribution kernel, and the thread distribution kernel distributes threads to the thread execution kernel by controlling the on-off of the switch elements.
The multi-core processor also comprises a first storage unit which is integrated on the same wafer with the thread distribution kernel and the thread execution kernel, wherein the first storage unit stores the state information of each thread execution kernel, and the state information comprises normal state information and abnormal state information; the thread distribution kernel is connected with the first storage unit and determines the thread execution kernel in a normal state by reading the state information stored in the first storage unit.
According to another embodiment of the invention, the multi-core processor comprises a plurality of thread distribution cores and a plurality of thread execution cores which are integrated on the same wafer, and each thread distribution core is connected with at least one thread execution core; each thread distribution kernel is used for distributing the thread executed by the multi-core processor to the thread execution kernels which are connected with the thread distribution kernels and are in a normal state; the thread execution kernel is used for executing the thread distributed by the thread distribution kernel.
Preferably, each thread execution core is connected to a set of system buses through a switch element, a switch element is connected between each thread execution core and the system buses in series, and a control end of each switch element is connected with at least one thread distribution core, and the thread distribution core distributes threads to the thread execution cores by controlling the on and off of the switch element.
Preferably, the thread allocation kernel includes a second storage unit, where the second storage unit stores state information of a thread execution kernel connected to the thread allocation kernel, and the state information includes normal state information and abnormal state information;
and the thread distribution kernel reads the state information stored in the second storage unit to determine the thread execution kernel in a normal state.
In another aspect, the present invention provides a signal processing method for a multi-core processor, where the multi-core processor includes at least one thread allocation core and a plurality of thread execution cores integrated on the same wafer, and each thread allocation core is connected to at least one thread execution core; the method comprises the following steps:
each thread distribution kernel acquires state information of a thread execution kernel connected with the thread distribution kernel, and determines the state of the thread execution kernel according to the state information, wherein the state comprises a normal state and an abnormal state;
the thread distribution kernel distributes the thread needing to be executed by the multi-core processor to the thread execution kernel in a normal state;
the thread execution kernel executes the thread allocated by the thread allocation kernel.
Preferably, the method further comprises:
each thread distribution kernel distributes a group of test instruction threads to each connected thread execution kernel respectively;
and marking the thread execution kernel which executes the test instruction thread exception as an exception state, and/or marking the thread execution kernel which executes the test instruction thread normal as a normal state.
Preferably, the multi-core processor includes a storage unit integrated in the same chip as the thread allocation core and the thread execution core, and the method further includes:
writing the state information of the thread execution kernel into the storage unit;
and the thread distribution kernel acquires the state information of the thread execution kernel connected with the thread distribution kernel by reading the storage unit, and determines the state of the thread execution kernel according to the state information.
Preferably, after each of the thread allocation kernels obtains state information of a connected thread execution kernel and determines a state of the thread execution kernel according to the state information, the method further includes:
the thread allocation kernel allocates the latest thread needing to be executed by the multi-core processor to the earliest ready thread execution kernel.
Drawings
FIG. 1 is a schematic structural diagram of a multi-core processor provided by an embodiment of the invention;
FIG. 2 is a schematic structural diagram of a multi-core processor provided by another embodiment of the invention;
FIG. 3 is a schematic diagram of a multi-core processor according to another embodiment of the invention;
FIG. 4 is a schematic structural diagram of a multicore processor provided by another embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a multicore processor provided by another embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a multicore processor provided by another embodiment of the present invention;
FIG. 7 is a flowchart illustrating a signal processing method of a multi-core processor according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a signal processing method of a multi-core processor according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The embodiment of the invention provides a multi-core processor, which comprises a single thread distribution kernel and a plurality of thread execution kernels, wherein the single thread distribution kernel and the plurality of thread execution kernels are integrated on the same wafer, and the thread distribution kernels are respectively connected with the plurality of thread execution kernels; the thread distribution kernel is used for distributing threads executed by the multi-core processor to the thread execution kernel in a normal state; and the thread execution kernel is used for executing the threads distributed by the thread distribution kernel.
As shown in fig. 1 in particular, the multi-core processor 100 of the present embodiment may include a thread allocation core 10 and a thread execution core 20, where the number of the thread execution cores 20 may be multiple, for example, the thread execution core 20 may include a first thread execution core 21 and a second thread execution core 22, and in addition, the thread allocation core 10 may be further connected to the first thread execution core 21 and the second thread execution core 22 respectively, and specifically, the thread allocation core 10 and the first thread execution core 21 and the second thread execution core 22 may be connected to a system bus of the multi-core processor 100 respectively. The thread distribution core 10 is responsible for thread distribution, and distributes threads that the multi-core processor 100 needs to execute to the first thread execution core 21 and the second thread execution core 22, and the thread execution cores execute corresponding threads and output execution results. In the embodiment of the present invention, the thread allocation kernel 10 may first obtain state information of all thread execution kernels 20 of the multicore processor 100, where the state information includes a normal state and an abnormal state, and then allocate a thread to be executed to a thread execution kernel in the normal state according to the obtained state information, as shown in fig. 1, when both the first thread execution kernel 21 and the second thread execution kernel 22 are in the normal state, the two thread execution kernels may respectively and independently execute the allocated thread.
Specifically, each thread execution core may be connected to the system bus of the multicore processor 100 through a switch element, and the thread allocation core 10 may implement allocation of threads between the first thread execution core 21 and the second thread execution core 22 by controlling the switch state of the switch element according to a preset timing. For example, when a thread is allocated to the first thread execution core 21, the thread allocation core 10 may control a switching element between the first thread execution core 21 and the system bus to be turned on, and control a switching element between the second thread execution core 22 and the system bus to be turned off, so that the first thread execution core 21 may obtain a corresponding thread allocation signal from the system bus and then execute the corresponding thread. When the second thread execution core 22 is allocated with a thread, the thread allocation core 10 may control the switch element between the second thread execution core 22 and the system bus to be turned on, and control the switch element between the first thread execution core 21 and the system bus to be turned off, so that the second thread execution core 22 may obtain a corresponding thread allocation signal from the system bus and then execute the corresponding thread.
In the above embodiment, the division of the thread allocation kernel 10 and the thread execution kernel 20 is only functional division, and in a specific application, the kernels may be divided into the thread allocation kernel 10 and the thread execution kernel 20 according to specific functions borne by each kernel of the multi-core processor 100, that is, the kernel in the multi-core processor 100 responsible for thread allocation may be defined as the thread allocation kernel 10, and the kernel in the multi-core processor 100 responsible for thread execution may be defined as the thread execution kernel 20. In addition, in the present embodiment, the number of the thread allocation cores 10 and the number of the thread execution cores 20 may be multiple, which will be clear to those skilled in the art and will not be described herein again.
In this embodiment, the state information or other information of each thread execution core may also be stored in a storage unit, as shown in fig. 2, the storage unit may be formed by a first memory 41 integrated into the thread distribution core 10, and the first memory 41 stores the state information of each thread execution core, and the state information of the embodiment of the present invention is divided into two types: normal state information and abnormal state information. The thread allocation core 10 determines the thread execution core in the normal state by reading the state information stored in the first memory 41.
The state information stored in the first memory 41 may indicate the operating state of each thread execution core, and referring to fig. 2, if the thread allocation core 10 reads that the state information of a certain thread execution core (e.g., the first thread execution core 21) is normal state information, it indicates that the thread execution core can execute a thread normally; if the state information of a certain thread execution core (the second thread execution core 22) is read as abnormal state information, it indicates that the thread execution core is in a fault, damage or abnormal state, and the thread cannot be executed. The state information of the thread execution cores in the first memory 41 may be recorded in the first memory 41 before the multi-core processor 100 of the embodiment of the present invention leaves factory, all the thread execution cores are detected before the multi-core processor leaves factory, the detection process may be that the thread allocation core 10 allocates a thread to each thread execution core, and if the result output by a certain thread execution core 21 or 22 is correct, the thread execution core 21 or 22 is recorded as a normal state in the first memory 41; otherwise, the state is marked as an abnormal state, and then the information such as the state and number of each thread execution core 21, 22 is stored in the first storage unit 41 to form the state information of each thread execution core of the multicore processor 100.
As shown in fig. 2, the first thread execution core 21 in this embodiment is in a normal operation state, and is capable of operating normally and executing threads; the second thread execution core 22 is in an abnormal state and cannot execute a thread (the thread execution core with the five star "-" symbol tag is in an abnormal state). In addition, each thread execution core in the embodiment of the present invention can execute multiple threads, and therefore, under the above-mentioned condition, the thread allocation core 10 may allocate a thread that needs to be executed by the second thread execution core 22 to the first thread execution core 21, and the first thread execution core 21 may execute two or more threads in different time gaps, so that normal operation is still achieved when part of cores in the multicore processor 100 are damaged, and normal operation is ensured when an abnormal core exists in multicore processing. Specifically, the thread allocation core 10 controls the switch between the thread execution core 22 and the system bus to be always in an off state when allocating a thread, which corresponds to bypassing the thread execution core 22.
The first memory 41 may be a register of the thread allocation core 10, which records the state information of each thread execution core by a plurality of bits, and corresponds to the thread execution core 21 or 22 by the bit sequence number of each register. That is, each bit of the register records the state of a corresponding thread execution core 21 or 22, for example, a "1" indicates that the corresponding thread execution core is in a normal state, and a "0" indicates that the corresponding thread execution core is in an abnormal state.
Referring to fig. 3, as an alternative implementation, in the present embodiment, the multicore processor 100 may further store the state information of each thread execution core by the second memory 42 independent of the thread allocation core 10, and the state information includes normal state information and abnormal state information; the thread allocation kernel 10 determines the thread execution kernel in the normal state by reading the state information stored in the second memory 42, so as to determine the thread execution kernel of the thread to be allocated, and other working principles are the same as or similar to those of the above embodiments, which can be referred to in the above description, and are not described herein again. The independent second storage 42 may also be other units with storage function in the system, and is not limited herein.
Another embodiment of the present invention provides a multi-core processor, wherein the multi-core processor includes a plurality of thread allocation cores and a plurality of thread execution cores integrated on the same wafer, and each thread allocation core is connected to at least one thread execution core; each thread distribution kernel is used for distributing the thread executed by the multi-core processor to the thread execution kernels which are connected with the thread distribution kernels and are in a normal state; and the thread execution kernel is used for executing the threads distributed by the thread distribution kernel. For the allocation of threads, each thread execution core is connected to a system bus through a switch element, and a control end of the switch element between each thread execution core and the system bus is connected with one thread allocation core which allocates threads to the thread execution cores by controlling on and off of the switch element.
As shown in fig. 4 in particular, the multi-core processor may include three thread allocation cores, namely, a first thread allocation core 11, a second thread allocation core 12, and a third thread allocation core 13, and nine thread execution cores (where the number of the thread allocation cores and the number of the thread execution cores may be determined according to the requirements of the product, and is only exemplarily illustrated here), referring to fig. 4, the thread execution cores 20 may be further averagely divided into three groups, such as a third thread execution core 23, a fourth thread execution core 24, and a fifth thread execution core 25 as a first group, a sixth thread execution core 26, a seventh thread execution core 27, and an eighth thread execution core 28 as a second group, and a ninth thread execution core 29, a tenth thread execution core 30, and an eleventh thread execution core 31 as a third group.
In addition, to describe the present embodiment in more detail, in this implementation, each thread allocation kernel may further connect and control a group of thread execution kernels respectively, for example: the first thread allocation core 11 may correspond to and be connected to a first group of thread execution cores, the second thread allocation core 12 may correspond to and be connected to a second group of thread execution cores, and the third thread allocation core 13 may correspond to and be connected to a third group of thread execution cores. Therefore, when thread allocation is performed, each thread allocation kernel can allocate a thread to a thread execution kernel group connected to the corresponding thread allocation kernel, and if a certain group of thread execution kernels are all in an abnormal state, the thread allocation kernel corresponding to the group of thread execution kernels does not perform thread allocation work. For example: the thread allocation kernel 11 may correspond to the first group of thread execution kernels, and when the thread is allocated, the thread allocation kernel 11 may allocate the thread to the third thread execution kernel 23, the fourth thread execution kernel 24, and the fifth thread execution kernel 25 of the first group, and when all the three thread execution kernels of the first group are in an abnormal state, the thread allocation kernel 11 does not perform the thread allocation work.
In a specific implementation, the thread allocation kernel and the thread execution kernel may be connected to a system bus respectively, a switch element is connected in series between each thread execution kernel and the system bus, a control end of each switch element is connected to at least one thread allocation kernel, and the thread allocation kernel allocates threads to the thread execution kernels by controlling on/off of the switch elements. For example, in the present embodiment, the first thread distribution core 11 corresponds to and is connected to the first group of thread execution cores, that is, the first thread distribution core 11 is connected through the switch element and controls thread distribution among the third thread execution core 23, the fourth thread execution core 24, and the fifth thread execution core 25 of the first group. The second thread allocation core 12 may control the thread allocation among the sixth, seventh and eighth thread execution cores 26, 27 and 28 of the second group through a switch element, and the third thread allocation core 13 may be correspondingly connected to the thread execution cores of the third group, and control the thread allocation among the ninth, tenth and eleventh thread execution cores 29, 30 and 31 through a switch element. Obviously, when the thread execution cores controlled by the thread allocation cores through the switch element connection are different, the thread execution cores controlled by the thread allocation cores are different, for example: when the first thread allocation core 11 is connected to the switching element to which all the thread execution cores (including the third to eleventh thread execution cores) are connected, then the first thread allocation core 11 can control the allocation of the thread to be allocated among all the thread execution cores. In addition, the first thread allocation core 11 may also obtain the state information of each thread execution core, and perform the allocation of specific threads according to the state information. The specific implementation manner may be modified according to actual needs, and is not specifically limited herein.
Referring to FIG. 4, a thread execution kernel marked with a five star "symbol represents that the kernel is in an abnormal state and cannot execute a thread. Therefore, when the thread is allocated by the thread allocation kernel of this embodiment, the thread allocation kernel may bypass the thread execution kernel in the abnormal state in the corresponding group, allocate the thread to other thread execution kernels in the normal state, and reallocate the thread that is originally allocated to the thread execution kernel in the abnormal state for execution, and during reallocation, the thread execution kernel waiting for the thread allocation that has been determined in the corresponding group may generally be selected. As shown in fig. 4, the first thread distribution core 11 can obtain the status information of the third thread execution core 23, the fourth thread execution core 24, and the fifth thread execution core 25 corresponding to the first group before allocating threads, and when it is confirmed that the fourth thread execution core 24 is in an abnormal state (damaged or abnormal) according to the obtained status information, the thread distribution core 11 corresponding to the group of thread execution cores can bypass the fourth thread execution core 24 and allocate threads to the third thread execution core 23 and the fifth thread execution core 25, respectively, when allocating threads, and furthermore, as described in the above embodiment, the third thread execution core 23 can also execute multiple threads (where the multiple threads are executed at different time intervals).
Referring to fig. 5, the multi-core processor according to another embodiment of the present invention further includes second storage units respectively built in the plurality of thread allocation cores, where the second storage units may include a third memory 43, a fourth memory 44, and a fifth memory 45, and each thread allocation core 10 determines a thread execution core in a normal state by reading state information of the thread execution cores stored in the third memory 43, the fourth memory 44, and the fifth memory 45 built therein. Specifically, the third storage unit 43 may store state information at least corresponding to the first group of thread execution cores (the third thread execution core 23, the fourth thread execution core 24, and the fifth thread execution core 25), and may also store other groups of core state information, which is not limited herein. The state information of the thread execution kernel may be obtained as described in the above embodiments, and details are not described herein. In addition, the third memory 43, the fourth memory 44, and the fifth memory 45 may also be registers in the corresponding thread allocation cores, and the related principles may refer to the above description, which is not described herein again.
Specifically, the state information stored in the third memory 43, the fourth memory 44, and the fifth memory 45 may indicate the operating state of each thread execution core, and if the state information of the thread execution core received by the thread allocation core is normal state information, it indicates that the thread execution core can execute the thread normally; if the received state information of the thread execution kernel is abnormal state information, the state information indicates that the thread execution kernel is in a fault state, a damaged state or an abnormal state, and the thread cannot be executed. The state information in the thread execution kernel may be stored in a corresponding storage before the multi-core processor 100 of the embodiment of the present invention leaves a factory, all the thread execution kernels may be detected before the multi-core processor 100 leaves the factory, a detection thread may be allocated to a kernel allocation detection thread by a thread directly or indirectly connected to the thread execution kernel in the detection process, and if the result output by the thread execution kernel is correct, the thread execution kernel is marked as a normal state; otherwise, the state is marked as an abnormal state, and then the state, the number and other information of each thread execution kernel are stored in the memory to form the state information of the thread execution kernel 20, specifically, when the storage capacity of the storage unit of the embodiment of the present invention is small, only the state information of the thread execution kernel corresponding to the storage unit can be stored; when the storage capacity of the storage unit is large, a single storage unit can store the state information of all the thread execution cores.
Referring to fig. 6, the multi-core processor according to another embodiment of the present invention may include a sixth memory 46 independent of the thread allocation core 10, and the multi-core processor stores state information of each thread execution core through the sixth memory 46, where the state information includes normal state information and abnormal state information; the thread allocation core 10 determines a thread execution core in a normal state among all thread execution cores by reading the state information stored in the sixth memory 46. The operation principle of the multi-core processor 100 including the sixth memory 46 is the same as or similar to that described above, and for the relevant description, reference may be made to the above description, which is not described herein again.
Based on the multi-core processor, the invention provides a signal processing method of the multi-core processor to process signals of the multi-core processor. The multi-core processor comprises at least one thread distribution core and a plurality of thread execution cores which are integrated on the same wafer, and each thread distribution core is respectively connected with at least one thread execution core. As shown in fig. 7, the signal processing method of the present embodiment includes the steps of:
in step S51, each thread allocation kernel obtains the state information of the thread execution kernel connected to the thread allocation kernel, and determines the state of the thread execution kernel according to the state information.
Specifically, when the number of cores in one processor is large, each core cannot be guaranteed to run normally, and the thread allocation core allocates a thread to the thread execution core according to the state information of the thread execution core, where the state of the thread execution core includes a normal state and an abnormal state, and the thread execution core in the normal state can run normally (i.e., can execute the thread); a thread cannot be executed if it is in an abnormal state. The state information of the thread execution kernel is acquired through state testing and stored in the corresponding storage unit, and the thread distribution kernel is connected with the storage unit and can acquire the state information of the thread execution kernel at any time.
The specific process of the thread execution kernel state test in this embodiment includes: each thread distribution kernel distributes a group of test instruction threads to each connected thread execution kernel respectively; and marking the thread execution kernel which executes the test instruction thread exception as an exception state, and/or marking the thread execution kernel which executes the test instruction thread normal as a normal state.
Specifically, the state testing process of the thread execution kernel is generally performed before the multi-core processor is used or before the multi-core processor is shipped (the method is suitable for the condition that the state of the thread execution kernel is stable and not easy to damage), the thread allocation kernel allocates a group of test instruction threads to the thread execution kernels directly or indirectly connected during testing, and the thread execution kernels execute the test instruction threads and output corresponding results. If the result output by the execution kernel of a certain thread meets the requirement, the execution kernel of the thread is recorded as a normal state, otherwise, the execution kernel of the thread is recorded as an abnormal state. The state testing process of the embodiment of the invention can also be periodically carried out according to a period set by a user in the using process of the multi-core processor, and the state information of the thread execution core stored in the storage unit is updated (the state testing process is suitable for the condition that the state of the thread execution core is unstable and is easy to damage or break down).
In a multi-core processor, each core has a corresponding number, the state information of the thread execution core of the embodiment includes the state and the number of each thread execution core, the multi-core processor includes a storage unit integrated in the same chip with a thread distribution core and the thread execution core, and the signal processing method of the embodiment writes the state information of the thread execution core into the storage unit; and the thread distribution kernel can acquire the state information of the thread execution kernel connected with the thread distribution kernel by reading the storage unit, and then determine the state of the thread execution kernel according to the state information.
In step S52, the thread allocation kernel allocates the thread that needs to be executed by the multi-core processor to the thread execution kernel in the normal state.
In step S53, the thread execution kernel executes the thread assigned by the kernel execution thread.
Specifically, each thread execution core is connected to a system bus of the multi-core processor through a switch element, and the thread distribution cores distribute threads for the thread execution cores by controlling the state of the switch element according to a preset time sequence. For example, when a thread is allocated to a thread execution core, if a certain thread execution core is in a normal state, the thread allocation core controls the conduction of a switch element between the thread execution core and a system bus; if a certain thread execution core is in an abnormal state, the switch element between the thread execution core and the system bus is controlled to be switched off, so that the thread execution core can obtain a corresponding signal from the system bus.
Before allocating threads to the thread execution cores, each thread allocation core acquires the state information of each thread execution core from the storage unit. After confirming the state of each thread execution kernel, the thread allocation kernel bypasses the thread execution kernels in the abnormal state when allocating the threads, and allocates all the threads to the threads in the normal state for execution.
When the thread allocation kernel of this embodiment is allocated, the thread allocation kernel allocates a latest thread that needs to be executed by the multi-core processor to the earliest ready thread execution kernel, that is, a next thread to be allocated in the thread allocation kernel is allocated to the thread execution kernel that has finished the thread execution task and is in the earliest waiting state. Therefore, some thread execution cores in a normal state need to execute two or more threads, each thread being executed in different time slots; or in order to maintain thread balance, each thread allocation kernel acquires state information of the corresponding thread execution kernel, and allocates corresponding threads according to the number of the thread execution kernels in the normal state, for example, one thread allocation kernel is connected with four thread execution kernels, and if three of the four thread execution kernels are in the normal state, the thread allocation kernel allocates three threads.
Specifically, as shown in fig. 8, the thread allocation core 10 and the thread execution cores 20 are included in the figure, and the thread allocation core 10 allocates threads to each group of thread execution cores respectively. It is noted that the thread execution core 20 is in an abnormal state and cannot execute the thread. In fig. 8, a first thread execution core in the thread execution core array has one thread execution core in an abnormal state, and a third thread execution core has two thread execution cores in an abnormal state, and in this embodiment, a thread may be allocated according to a core in which each thread execution core is in a normal state, for example, the thread allocation core 10 allocates 3 threads to the first thread execution core, allocates 2 threads to the third thread execution core, and allocates 4 threads to the second and fourth thread execution cores, respectively, so that the thread execution cores in the abnormal state are avoided.
The multi-core processor signal processing method of the embodiment of the present invention is merely illustrative, and the number of the thread execution cores is not limited to the actual number in fig. 8, that is, the present invention may be applied to a processor including more than 16 cores, such as a processor with 32 cores, 64 cores, or even more cores.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. The multi-core processor is characterized by comprising a thread distribution core and a plurality of thread execution cores which are integrated on the same wafer, wherein the thread distribution core is respectively connected with the thread execution cores;
the thread distribution kernel is used for distributing the threads executed by the multi-core processor to the thread execution kernels in a normal state;
the thread execution kernel is used for executing the thread distributed by the thread distribution kernel.
2. The multi-core processor of claim 1, wherein the thread distribution core and the thread execution core are respectively connected to a system bus, a switch element is connected in series between the thread execution core and the system bus, a control terminal of each switch element is connected to the thread distribution core, and the thread distribution core distributes threads to the thread execution cores by controlling on/off of the switch elements.
3. The multi-core processor of claim 1, further comprising a first storage unit integrated on the same die as the thread distribution cores and the thread execution cores, the first storage unit storing status information of each of the thread execution cores, the status information including normal status information and abnormal status information;
the thread distribution kernel is connected with the first storage unit, and the thread execution kernel in a normal state is determined by reading the state information stored in the first storage unit.
4. A multi-core processor comprising a plurality of thread distribution cores and a plurality of thread execution cores integrated on the same wafer, wherein each thread distribution core is connected with at least one thread execution core;
each thread distribution kernel is used for distributing the thread executed by the multi-core processor to the thread execution kernels which are connected with the thread distribution kernels and are in a normal state;
the thread execution kernel is used for executing the thread distributed by the thread distribution kernel.
5. The multi-core processor of claim 4, wherein the thread distribution cores and the thread execution cores are respectively connected to a system bus, a switch element is connected in series between each thread execution core and the system bus, a control terminal of each switch element is connected with at least one thread distribution core, and the thread distribution cores distribute threads to the thread execution cores by controlling on and off of the switch elements.
6. The multi-core processor of claim 4, wherein the thread allocation kernel comprises a second storage unit, the second storage unit stores state information of a thread execution kernel connected to the thread allocation kernel, and the state information includes normal state information and abnormal state information;
and the thread distribution kernel reads the state information stored in the second storage unit to determine the thread execution kernel in a normal state.
7. A multi-core processor signal processing method is characterized in that the multi-core processor comprises at least one thread distribution core and a plurality of thread execution cores which are integrated on the same wafer, and each thread distribution core is respectively connected with at least one thread execution core; the method comprises the following steps:
each thread distribution kernel acquires state information of a thread execution kernel connected with the thread distribution kernel, and determines the state of the thread execution kernel according to the state information, wherein the state comprises a normal state and an abnormal state;
the thread distribution kernel distributes the thread needing to be executed by the multi-core processor to the thread execution kernel in a normal state;
the thread executing kernel executes the thread allocated by the thread allocating kernel.
8. The method of multi-core processor signal processing according to claim 7, further comprising:
each thread distribution kernel distributes a group of test instruction threads to each connected thread execution kernel respectively;
and marking the thread execution kernel which executes the test instruction thread exception as an exception state, and/or marking the thread execution kernel which executes the test instruction thread normal as a normal state.
9. The method of signal processing of a multi-core processor of claim 7, wherein the multi-core processor includes a memory unit integrated within a same die as the thread allocation core and the thread execution core, the method further comprising:
writing the state information of the thread execution kernel into the storage unit;
and the thread distribution kernel acquires the state information of the thread execution kernel connected with the thread distribution kernel by reading the storage unit, and determines the state of the thread execution kernel according to the state information.
10. The method according to claim 7, wherein after each of the thread assignment cores obtains state information of a connected thread execution core, and determines a state of the thread execution core according to the state information, the method further comprises:
the thread allocation kernel allocates the latest thread needing to be executed by the multi-core processor to the earliest ready thread execution kernel.
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